NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: WT6511 WT6511 General Description The WT6511 WT6511 is a single Micro-controller chip used for Universal Serial Bus (USB) keyboard applications. It inciudes an 6-bit 6502 CPU cone, 256 bytes SRAM, BK bytes MASK ROM, 30-36 Programmable I/O with built-in pull-up resistors and interrupt capability (8 with high drive capability up to 16mA). Features B-bit 6502 CPU with 3Mhz operating frequency 6lWHz crystal oscillator 256 bytes SRAM 8K bytes MASK ROM 30-36 programmable I/O (Package Dependant) pins wilh interrupted ... | OCR Scan |
1 pages, |
crystal 3mhz CPU 6502 WT6511 6502 CPU WT6511 abstract |
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| Abstract: WT65F1 WT65F1 General Description The WT65F1 WT65F1 is single chip Micro-controller for Universal Serial Sus (USB) keyboard applications. It includes an S-bil 6502 CPU core, 256 bytes SRAM. BK bytes FLASH memory, 30-36 Programmable I/O with built-in pull-up resistors and interrupt capability (8 with high drive capability up to 16mA). Features B-bit 6502 CPU with 3MHz operating frequency 6MHz crystal oscillator 256 bytes SRAM 8K bytes Flash ROM 30-36 programmable I/O (Package Dependant) pins wi!h interrupted ... | OCR Scan |
1 pages, |
WT65F1 CPU 6502 6502 CPU 6502 crystal 3mhz WT65F1 abstract |
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| Abstract: WT5091 WT5091 General Description The WT5091 WT5091 is a CMOS 8-bit single-chip microcontroller with Port or Interface for SPI y UART, It includes an 3-bit 6502 CPU core, 1QK bytes RAM, 896K bytes ROM, 16 bit programmable I/O with controllable Pull-UP resistors, dual 16-bit timer/counters, interrupt controller, and 8 channel of 12-bit Aj'D converter. Features e-bit 6502 CPU 10K bytes SRAM Internal ROM S96K bytes Operating Voltage 3.3V ±10% Crystal OSC circuit with maximum frequency up to 16 MHz Offer 8 interrupt ... | OCR Scan |
1 pages, |
WT5091 WT5091 abstract |
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| Abstract: WT5090 WT5090 General Description The WT5090 WT5090 is a CMOS 8-bit single-chip microcontroller with Hardware LCD module driver Port & SPI interface & UART. It induces an 8-bit 6502 CPU core, 12K bytes RAM, 16K bytes ROM, External ROM Access capability maximum size up to 8M bytes. 32 programmable I/O with controllable Pull-UP resistors, dual 16-bit timer/counters, interrupt controller, and 8 channel of 12-bit AIO converter. Features B-bit 6502 CPU 12Kbytes SRAM and IBKbytes ROW External ROM Access capability maximum ... | OCR Scan |
1 pages, |
WT5090 WT5090 abstract |
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| Abstract: WT6512 WT6512 General Description The WT6512 WT6512 is a single chip micro-controller for Universal Serial Bus (USB) low speed HID applications; it includes an 8-bits 6502 CPU core, 256 bytes SRAM. SK bytes Mask ROM memory, 30 programmable I/O with built-in pull-up resistors and Interrupt capability, 4 output with high drive capability up to 10mA, Features 8-bit 6502 CPU with 3Mhz operating frequency 6MHz crystal oscillator 256 bytes SRAM 8K bytes Mask ROM memory programmable I/O (package-dependant) pins, 8 ... | OCR Scan |
1 pages, |
WT6512 WT6512 abstract |
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| Abstract: WT6512F WT6512F General Description The WT6512F WT6512F is a sing I s chip micro-controller for Universal Serial Bus (USB) low speed HID applications; it includes an 6-bits 650? CPU core, 256 bytes SRAM. 3K bytes Flash ROW memory, 30 programmable I/O with built-in pull-up resistors and interrupt capability, 4 oulput with high drive capability up Eo 10mA. 1.2 Features a-brt 6502 CPU with 3Mhz operating frequency elMHz crystal oscillator 256 bytes SRAM 6K bytes Flash ROM memory 30 programmable I/O ... | OCR Scan |
1 pages, |
WT6512F WT6512F abstract |
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| Abstract: with the USB specification version 1.1. 1,2 Features 6-bit 6502 CPU 64K bytes flash memory(64K-byfes , WT65F5 WT65F5 General Description The WT6SF5/WT6550 WT6SF5/WT6550 is highly integrated Micro controller with Universal Serial Bus (USB) interface. It contains an 6052 based CPU core, 64K bytes Flash memory (64K bytes mask ROW for WT6550 WT6550), 2304 bytes {2K+256 bytes) RAM, USB transceiver, Serial bus Interface Entire (SIE), System interface Logic (SIL) and transmit I receive FIFOs. The USB function supports low/full-speed data ... | OCR Scan |
1 pages, |
WT65F5 6502 CPU "USB Transceiver" WT6SF5/WT6550 WT6550 WT655Q WT65F5 abstract |
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| Abstract: Ver2.8 NT6881 NT6881 Features ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Built-in 6502 8-bit CPU 3 , applications. It incorporates a 6502 8-bit CPU core, 6K bytes of mask ROM, and 256 bytes of RAM used as working , Generator Power Down/Up Transceiver VCP VDP VDM OSCO SIE 6502 CPU Interrupt Controller , Description 1. 6502 CPU The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary , included. The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for ... | Original |
27 pages, |
NT6881H NT6881 keyboard CIRCUIT diagram CPU 6502 6502 CPU NT6881 abstract |
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| Abstract: micro-controller for USB keyboard applications. It incorporates a 6502 8-bit CPU core, 6K bytes of mask ROM, and , Power Down/Up Transceiver VCP VDP VDM OSCO SIE 6502 CPU Interrupt Controller 6K , oscillator input 3 NT6881 NT6881 Functional Description 1. 6502 CPU The 6502 is an 8-bit CPU that , = TRUE 1 = BRK Overflow 1 = TRUE Negative 1 = NEG Figure 1.1. 6502 CPU Registers and , the 6502 CPU, has a capacity of 6K X 8-bit and is addressed from E800H E800H to FFFFH. 4. SRAM: 256 X 8 ... | Original |
23 pages, |
PS "usb Keyboard" NT6881 CPU 6502 datasheet NT6881H 6502 6502 dip CPU 6502 6502 CPU NT6881 abstract |
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| Abstract: Generator Power Down/Up Transceiver VCP VDP VDM OSCO SIE 6502 CPU Interrupt Controller , ROM program code, executed by the 6502 CPU, has a capacity of 6K x 8-bit and is addressed from E800H E800H , interrupt 6502 CPU. The TMR flag can be read by the software. Once set by an interrupt source, it can read , trigger, NT68P81 NT68P81 sets the INT0 flag ($0000H 0000H, bit1). After that, the 6502 CPU is interrupted if this , cleared, the 6502 CPU can't be INT0 interrupted even if the INT0 flag is set. INT0 flag can be only be set ... | Original |
30 pages, |
27C64 6502C keypad 4 times 4 for calculator NT68 NT68P81 6502 timing diagram low voltage mega bass circuit INTEL 27C64 ROM 6502 dip 8 bit flash program memory PC mini keyboard CIRCUIT diagram CPU 6502 6502 CPU NT68P81 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| 6502/ - Architectural files for the 6502 CPU. c16x/ - Architectural files for the C16x/ST10 uC. Supports lwIP Raw API only. CS8900a Ethernet driver for 16-bit mode. msvc6/ - Architectural files for Microsoft Visual C+ 6.0. rtxc/ - Architectural files for the RTXC operating system. unix/ - Architectural files for testing on unix-like systems ://www.xilinx.com/ise/vii_pro/kit.htm) coldfire/ - Architectural files for Motorola Coldfire 5272 CPU running under Nucleus OS www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (FILES) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| 6502/ - Architectural files for the 6502 CPU. c16x/ - Architectural files for the C16x/ST10 uC. Supports lwIP Raw API only. CS8900a Ethernet driver for 16-bit mode. msvc6/ - Architectural files for Microsoft Visual C+ 6.0. rtxc/ - Architectural files for the RTXC operating system. unix/ - Architectural files for testing on unix-like systems ://www.xilinx.com/ise/vii_pro/kit.htm) coldfire/ - Architectural files for Motorola Coldfire 5272 CPU running under Nucleus OS www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (FILES) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| /IP stack. * * Author: Adam Dunkels * */ #ifndef _CPU_H_ #define _CPU_H_ #define BYTE_ORDER LITTLE_ENDIAN #endif /* _CPU_H_ */ www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (cpu.h) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| /IP stack. * * Author: Adam Dunkels * */ #ifndef _CPU_H_ #define _CPU_H_ #define BYTE_ORDER LITTLE_ENDIAN #endif /* _CPU_H_ */ www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (cpu.h) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| /cc.h/1.1/Sat Jan 18 18:33:29 2003// /cpu.h/1.1/Sat Jan 18 18:33:29 2003// /lib.h/1.1/Sat Jan 18 18:33:29 2003// /perf.h/1.1/Sat Jan 18 18:33:29 2003// /sys_arch.h/1.1/Sat Jan 18 18:33:29 2003// D www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (Entries) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| /cc.h/1.1/Sat Jan 18 18:33:29 2003// /cpu.h/1.1/Sat Jan 18 18:33:29 2003// /lib.h/1.1/Sat Jan 18 18:33:29 2003// /perf.h/1.1/Sat Jan 18 18:33:29 2003// /sys_arch.h/1.1/Sat Jan 18 18:33:29 2003// D www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (Entries) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| 0301 /* Hitachi 6305 */ #define OT_6502 0x0400 /* Rockwell 6502 */ #define OT_65c02 0x0401 */ #define OT_68040 0x0520 /* Motorola 68040 */ #define OT_68060 0x0521 /* Motorola 68060 */ #define OT_CPU32 0x0522 /* Motorola CPU32 generic */ #define OT_CPU32P 0x0523 /* Motorola CPU32+ generic _EC040 EC040 EC040 EC040 0x0532 /* Motorola 68EC040 68EC040 68EC040 68EC040 */ #define OT_LC040 LC040 LC040 LC040 0x0533 /* Motorola 68LC040 68LC040 68LC040 68LC040 */ #define OT_CPU00 0x www.datasheetarchive.com/download/48478472-483223ZC/sdsmon07.zip (TARGET.H) |
Motorola | 13/09/1996 | 209.17 Kb | ZIP | sdsmon07.zip |
| 0301 /* Hitachi 6305 */ #define OT_6502 0x0400 /* Rockwell 6502 */ #define OT_65c02 0x0401 */ #define OT_68040 0x0520 /* Motorola 68040 */ #define OT_68060 0x0521 /* Motorola 68060 */ #define OT_CPU32 0x0522 /* Motorola CPU32 generic */ #define OT_CPU32P 0x0523 /* Motorola CPU32+ generic _EC040 EC040 EC040 EC040 0x0532 /* Motorola 68EC040 68EC040 68EC040 68EC040 */ #define OT_LC040 LC040 LC040 LC040 0x0533 /* Motorola 68LC040 68LC040 68LC040 68LC040 */ #define OT_CPU00 0x www.datasheetarchive.com/download/28041905-484830ZC/revamon.zip (TARGET.H) |
Motorola | 04/08/1998 | 316.64 Kb | ZIP | revamon.zip |
| 0301 /* Hitachi 6305 */ #define OT_6502 0x0400 /* Rockwell 6502 */ #define OT_65c02 0x0401 */ #define OT_68040 0x0520 /* Motorola 68040 */ #define OT_68060 0x0521 /* Motorola 68060 */ #define OT_CPU32 0x0522 /* Motorola CPU32 generic */ #define OT_CPU32P 0x0523 /* Motorola CPU32+ generic _EC040 EC040 EC040 EC040 0x0532 /* Motorola 68EC040 68EC040 68EC040 68EC040 */ #define OT_LC040 LC040 LC040 LC040 0x0533 /* Motorola 68LC040 68LC040 68LC040 68LC040 */ #define OT_CPU00 0x www.datasheetarchive.com/download/70472419-484523ZC/revamon.zip (TARGET.H) |
Motorola | 04/03/1998 | 316.64 Kb | ZIP | revamon.zip |