NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 56-octet 1 4 cells Yes N/A Virtex-E V100E-8CS144 V100E-8CS144 95 2 74 127 3.1i 2 Block RAMs Notes: 1. ... | Original |
5 pages, |
datasheet abstract |
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| Abstract: RAMs SPHY 32-bit 56-octet 1 4 cells N/A Virtex-E V100E-8CS144 V100E-8CS144 84 2 74 112 3.1i 2 Block ... | Original |
6 pages, |
datasheet abstract |
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| Abstract: 2 255 4 104.6 MHz SPHY 32-bit 1 56-octet 4 cells N/A XCV100E-8CS144 XCV100E-8CS144 74 2 100 2 ... | Original |
6 pages, |
vhdl code for asynchronous fifo datasheet abstract |
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| Abstract: S4804CBI41 S4804CBI41 Rhine Datasheet Revision 2.0 January 8, 2002 AMCC Dear customer, Thank you for choosing an AMCC device. We appreciate your confidence in our products. To ensure your complete satisfaction with our products and technologies, we have prepared this publication to provide you additional information, which will help you use the device more efficiently. (This publication may be held to our confidential and proprietary requirements and non-disclosure agreements.) If y ... | Original |
279 pages, |
S4804CBI 2F0F 2F27 331a transistor S4804 P12 REI motorola g06 624 AMCC 2225 diode 2a05 cd 1619 ATM machine using microprocessor lcd stream system lcd 3203 S4804CBI41 291b S4804CBI41 abstract |
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| Abstract: сч PRELIMINARY XRT95L34 XRT95L34 OC-12/STM-4 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR'S APRIL 2002 GENERAL DESCRIPTION The XRT95L34 XRT95L34 is an OC-12/STM-4 OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR's. ATM direct mapping and cell delineation are supported, so are packets (PPP) over SONET for POS mapping and frame processing. The XRT95L34 XRT95L34 contains an integral SONET framer which provides framing and error accumulation in accordance with ANSI/ITU-T specifications. The confi ... | Original |
399 pages, |
XRT95L34IV XRT95L34 SDH 209 AC03 nec prbs parity checker and generator XRT95L34 abstract |
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| Abstract: UTOPIA Level 3 ATM Receive Interface December 2003 IP Data Sheet Features General Description Fully Compatible with ATM Forum UTOPIA Level 3 Specifications Supports Single-PHY and Multi-PHY Operation Modes Multi-PHY Operation with Single rxclav signal in Polling Mode Multi-PHY Operation with Up to 4 rxclav Signals in Direct Status Indication Mode Configurable 8-, 16-, or 32-Bit Wide Data Path Configurable Cell Format; HEC or no HEC User-configurable Polarity for H ... | Original |
7 pages, |
UTOP3-ATMR-04-N2 LFX500B-05F516C LC51024MB-52F484C datasheet abstract |
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| Abstract: UTOPIA Level 3 ATM Transmit Interface December 2003 IP Data Sheet Features General Description Fully Compatible with ATM Forum UTOPIA Level 3 Specifications Supports Single-PHY and Multi-PHY Operation Modes Multi-PHY Operation with Single txclav Signal in Polling Mode Multi-PHY Operation with up to Four txclav signals in Direct Status Indication Mode Configurable 8-, 16-, or 32-Bit Wide Data Path Configurable Cell Format; HEC or no HEC User-configurable Polarity ... | Original |
7 pages, |
LFX500B-05F516C LC51024MB-52F484C datasheet abstract |
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| Abstract: ispLever CORE TM UTOPIA Level 3 PHY Receive Interface User's Guide October 2003 ipug21_01 Lattice Semiconductor UTOPIA Level 3 PHY Receive Interface Introduction The UTOPIA Level 3 PHY Receive core, UTOP3-PHYR, is one of four UTOPIA Level 3 cores available from Lattice. It provides high-speed transmission of ATM cells from the UTOPIA bus of the physical layer device (PHY) to the ATM layer device in different configurable cell formats. This UTOP3-PHYR core comes with the ... | Original |
8 pages, |
ddr phy design master ATM controller ddr phy datasheet abstract |
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| Abstract: UTOPIA Level 3 PHY Transmit Interface December 2003 IP Data Sheet Independent Clocks for UTOPIA and PHY Side Interfaces UTOPIA Interface Error and FIFO Empty Flag Warnings High-speed Operation; up to 104 MHz IP Core Package Contains Features Fully Compatible with ATM Forum UTOPIA Level 3 Specifications Supports Single-PHY and Multi-PHY Operation Modes Multi-PHY Operation with Single txclav Signal in Polling Mode Multi-PHY Operation with Up to Four txclav Signals i ... | Original |
7 pages, |
LFX500B-05F516C LC51024MB-52F484C datasheet abstract |
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| Abstract: ispLever CORE TM UTOPIA Level 3 ATM Transmit Interface User's Guide October 2003 ipug20_01 Lattice Semiconductor UTOPIA Level 3 ATM Transmit Interface Introduction The UTOPIA Level 3 ATM Transmit core, UTOP3-ATMT, is one of four UTOPIA Level 3 cores available from Lattice. It provides high-speed transmission of ATM cells from the ATM layer device to the UTOPIA bus in different configurable cell formats. The UTOPIA Level 3 ATM Transmit Interface core comes with the docume ... | Original |
12 pages, |
h48 diode P44 transistor h48 signal diode diode H48 datasheet abstract |
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| Abstract: ispLever CORE TM UTOPIA Level 3 ATM Receive Interface User's Guide October 2003 ipug19_01 Lattice Semiconductor UTOPIA Level 3 ATM Receive Interface Introduction The UTOPIA Level 3 ATM Receive core, UTOP3-ATMR, is one of four UTOPIA Level 3 cores available from Lattice. It provides high-speed transmission of ATM cells from the UTOPIA bus to the ATM layer device in different configurable cell formats. This UTOP3-ATMR core comes with the following documentation and files: ... | Original |
11 pages, |
p p48 transistor p11 ATM timing diagram P44 transistor datasheet abstract |
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| Abstract: UTOPIA Level 3 PHY Receive Interface December 2003 IP Data Sheet UTOPIA Interface Error and FIFO Full Flag Warnings PHY Interface Error Detection and FIFO Overflow Control High-speed Operation; 104 MHz IP Core Package Contains Features Fully Compatible with ATM Forum UTOPIA Level 3 Specifications Supports Single-PHY and Multi-PHY Operation Modes Multi-PHY Operation with Single rxclav Signal in Polling mode Multi-PHY Operation with Four rxclav Signals in Direct Sta ... | Original |
8 pages, |
UTOP3-PHYR-04-N2 master ATM controller LFX500B-05F516C LC51024MB-52F484C datasheet abstract |
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| /* * * Name: xmac_ii.h * Project: GEnesis, PCI Gigabit Ethernet Adapter * Version: $Revision: 1.46 $ * Date: $Date: 2003/01/28 09:47:45 $ * Purpose: Defines and Macros for Gigabit Ethernet Controller * */ /* * * (C)Copyright 1998-2003 SysKonnect GmbH. * * www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (xmac_ii.h) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |