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Abstract: Range Standard Frequency (MHz) 12~54MHz Standard Frequency 12.0000 Table 1 14.31818 , Oper. Temp. Range Load Capacitance 14.7456 24.54545 12~14MHz 150 14~30MHz 100 30~54MHz 50 , ~24MHz : 0.3mW MAX. 24~54MHz : 0.1mW MAX. Drive Level 36.000 48.000 Three drops onto a hard ... Original
datasheet

1 pages,
171.97 Kb

CX-53F 54-MHz CX-53F abstract
datasheet frame
Abstract: 9-bit 12-bit 10-bit 12-bit Conversion Rate 27MHz 27MHz 54MHz 54MHz 54MHz 110MHz 110MHz 27MHz (2x) 27MHz (2x) 54MHz (4x) 54MHz (4x) 54MHz (4x) 54MHz (4x) 54MHz (4x) 10 8 8 8 10 8 10 80-LQFP 80-LQFP Pb-Free 100-LQFP 100-LQFP PbFree 100-LQFP 100-LQFP ... Original
datasheet

2 pages,
102.79 Kb

Video cvbs 656 ADV7183 ADV7183A ADV7185 ADV7189 ADV7400 ADV7181 cvbs to rgb analog lcd Hsync Vsync csync tv tuner cards chroma cvbs to lcd decoder digital RGB input analog CVBS output ADV7185 abstract
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Abstract: Sheet1 TYPE HBF TOKO Part Number 604E-013 604E-013 604E-020 604E-020 604E-054 604E-054 604E-055 604E-055 604E-056 604E-056 604E-057 604E-057 604E-058 604E-058 604E-064 604E-064 604E-065 604E-065 604E-067 604E-067 604E-085 604E-085 604E-086 604E-086 604E-087 604E-087 Function 5.5MHz LPF 20MHz LPF+APR 5.4MHz LPF 5.4MHz LPF+APR 12MHz LPF 12MHz LPF+APR 8.4MHz LPF 8.578MHz LPF 10.125MHz LPF 5.5MHz LPF+APR 30MHz LPF 15MHz LPF 8.15MHz LPF Input/Output Rin & Rout () 330 150 330 330 150 150 470 220 220 330 270 270 330 Page 1 ... Original
datasheet

1 pages,
200.2 Kb

604E-013 604E-020 604E-054 604E-055 604E-056 604E-057 604E-058 604E-064 604E-065 604E-067 604E-085 604E-086 604E-087 604E-013 abstract
datasheet frame
Abstract: and RX or separate type available. Compact surface-mount type Both 42MHz/54MHz for US and 65MHz/85MHz for EU available · CATV · TXRX · · US42MHz/54MHzEU65MHz/85MHz Connection 1 , 2 , R947DCCFN-1021 R947DCCFN-1021 5 R947DCCFN-1021 R947DCCFN-1021 US (42MHz/54MHz) High pass port 7 EU (65MHz/85MHz) Cable ... Original
datasheet

1 pages,
73.95 Kb

datasheet abstract
datasheet frame
Abstract: BC 35 Series - Bomar Crystal 5.0X3.2X1.2 mm FEATURES The BC 35 crystal is a ultra miniature ceramic package SMD type. The height is less than 1.4mm and fundamental till 54MHz that allows is ease of circuit design. Excellent electric performance optimum for OA and AV application. Parameter Frequency Range Symb Condition Fo Frequency Tolerance at 25º Min - Typ 12 At 25 ºC F/ Fo Ultra-miniature size Fundamental till 54MHz Wide Frequency Range Ceramic ... Original
datasheet

1 pages,
77.46 Kb

datasheet abstract
datasheet frame
Abstract: 196.2 576.57 54Mhz Max Power Numbers - Max Voltage on Ivcc & Evcc2 Bus Frequency Clock Ratio , 722.19 54Mhz Notes: 1. Typical power measurements recorded while running Dhrystone 2.1 code found ... Original
datasheet

1 pages,
2.99 Kb

power dissipation measurement MCF5407 MCF5407 abstract
datasheet frame
Abstract: CX-101F CX-101F SMD sFeatures î"›ltra-thin, thickness 0.75mm. (3.2�5�75mm) î"ˆecause it is the leadless type, automatic mounting is possible. î"‹xcels even in an environment that requires reliability. î"˜eflow is possible. sSpecifications Type sTable 1 Standard Frequencies CX-101F CX-101F Frequency Range Standard Frequency (MHz) 16~54MHz 20.000 Standard Frequency Table 1 Operating Temp. Range , Temp. Range � Load Capacitance 12pF 16~30MHz 100 30~54MHz 50 Equivalent Series Resistance ... Original
datasheet

1 pages,
155.21 Kb

CX-101F CX-101F abstract
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Abstract: 10-BitADCs applications Supports the standard ITU-R BT.656 format or time multiplexed output with 54MHz Provides simultaneous four channel Full D1 and CIF time-multiplexed outputs with 54MHz Supports a two-wire serial host ... Original
datasheet

2 pages,
233.1 Kb

Video-Decoders digital security system block diagram DVR block diagram TW2815 BT 656 PIN DIAGRAM techwell tw2816 Techwell TW2816 TW2816 abstract
datasheet frame
Abstract: Diplexer for digital CATV CATV TYPE DIMENSIONS / ( Unit : mm ) 1.5 5.5 36max. 5.7 20.0�0 1.15 8.5max. 31.0�0 9max. FEATURES / Diplexers for digital CATV set top box and cable modem. Integrated type of TX and RX or separate type available. Compact surface mount type. MHzMHz MHz 42MHz/54MHz for US and 65MHz , /85MHz) US(42MHz/54MHz) Integrated type Integrated type R947DCCFN-1021 R947DCCFN-1021 R947DCCFN-1022 R947DCCFN-1022 CAUTION ... Original
datasheet

2 pages,
98.3 Kb

datasheet abstract
datasheet frame
Abstract: Performance vs SDRAM page hits and buffer size for 54Mhz, 10(7)-1-1-1 configuration Performance vs SDRAM page hits and buffer size for 54Mhz, 9(7)-1-1-1 configuration · Ethernet DMA Controller Operation - Tx , : 54Mhz, 10(7)-1-1-1 45.0 40.0 40.0 36.6 36.4 35.0 % Bus Utilization for 100 Mbps Full Duplex , Bus Usage Page 5 February 5, 2001 Performance vs Buffer Size and Page Hits: 54Mhz, 9(7 ... Original
datasheet

7 pages,
43.02 Kb

MCF5272 MCF5272 abstract
datasheet frame
Abstract: XTL Series Products SMD Capability 5.0x3.2 (mm) 4.0x2.5 (mm) 3.2x2.5 (mm) 2.5x2.0 (mm) Fundamental Frequency Range (3rd) 8 MHz~54 MHz 75 MHz~106.65 MHz 11 MHz~50 MHz 12 MHz~54 MHz 16 MHz~54 MHz Shunt Capacitance 5.0 pF Max 5.0 pF Max 5.0 pF Max 3.0 pF Max Load Capacitance 5~37 pF 7~30 pF 6~30 pF 8~20 pF Contact RFM for Custom Device / Specifications Packages and Dimensions ... Original
datasheet

1 pages,
96.06 Kb

XTL SERIES datasheet abstract
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Abstract: PHASE SHIFTER JSPHS-51 JSPHS-51+ Typical Performance Curves Phase Shift 300 270 Phase Shift (Deg.) 240 210 180 150 120 90 36 MHz 45 MHz 54 MHz 60 30 0 0.0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 Control Voltage (V) Insertion Loss VSWR 1.9 1.6 1.8 1.4 1.7 VSWR (:1) 2.0 1.8 Insertion Loss (dB) 2.0 1.2 1.0 0.8 0.6 36 MHz 45 MHz 54 MHz 1.6 1.5 1.4 1.3 36 MHz 45 MHz 54 MHz 0.4 0.2 ... Original
datasheet

1 pages,
21.71 Kb

datasheet abstract
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Abstract: 25/0251 CY2411 CY2411 54-MHz MPEG Clock Generator with VCXO 2 Features Benefits · Integrated phase-locked loop Highest Performance PLL tailored for multimedia applications · Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs · VCXO with analog adjust Large ± 150 ppm range, better linearity · 3.3V Operation Part Number CY2411 CY2411 Outputs 1 , Semiconductor against all charges. CY2411 CY2411 Document Title: CY2411 CY2411 54-MHz MPEG Clock Generator with VCXO ... Original
datasheet

5 pages,
86.04 Kb

CY2411SCT CY2411SC CY2411 CY2411 abstract
datasheet frame
Abstract: 6 54-MHz clock output XOUT Note: 1. Float XOUT if XIN is externally driven. Cypress , indemnifies Cypress Semiconductor against all charges. CY2411 CY2411 Document Title: CY2411 CY2411 54-MHz MPEG Clock ... Original
datasheet

4 pages,
86.44 Kb

CY2411 CY2411-1 CY2411 abstract
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Abstract: PHASE SHIFTER JSPHS-51 JSPHS-51+ Typical Performance Data CONTROL VOLTAGE PHASE SHIFT* VSWR INSERTION LOSS 36 MHz (Deg.) 45 MHz 54 MHz 36 MHz (:1) 45 MHz 54 MHz 36 MHz (dB) 45 MHz 54 MHz 0.0 0.00 0.00 0.00 1.27 1.02 1.08 1.26 0.82 0.67 1.0 18.04 7.16 3.25 1.29 1.02 1.08 1.40 0.89 0.70 3.0 62.86 26.70 11.66 1.39 1.04 1.10 1.58 1.09 0.79 5.0 113.34 59.95 25.08 ... Original
datasheet

1 pages,
14.77 Kb

JSPHS-51 JSPHS-51 abstract
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Abstract: YCL FH203441 FH203441 1/10Mbps Home Phone Networking Bandpass Filter Feature Designed for Home Run networking . Designed for use with Broadcom BCM4210 BCM4210 Designed to meet Home PNA 2.0 Specification Internal high voltage capacitor. Specification Parameters Impedance Insertion loss Cut off Frequency Attenuation Return loss Isolation Condition Min. @4.25MHz-9.75MHz @3.5MHZ , 11.5MHz @1.1MHz @22MHz @54MHz @6MHz-9MHz Typ. 100 -1 Max. -2.2 -3dB -60 -35 -50 -12.0 1500 dB dB ... Original
datasheet

1 pages,
25.7 Kb

BCM4210 FH203441 FH203441 abstract
datasheet frame
Abstract: 200910 TX19 TX19A TX19A 32 / 289 TMP19A61C10XBG TMP19A61C10XBG TMP19A61CDXBG TMP19A61CDXBG ADSIO/RISC TX19A TX19A CPU = 1.351.65V I/O = 1.653.3V ADC = 2.73.3V 54MHz (PLL4) 10AD : 32 DMA : 8 16 : 36 32 : 2 : 4 : 4 SIO/UART : 9 HSIO/UART : 2 I2C/SIO : 2 : 4 ROM TMP19A61C10XBG TMP19A61C10XBG 1M RAM 48K TMP19A61CDXBG TMP19A61CDXBG 512K 40K FBGA289 FBGA289 C SW1ACN0-ZCC: 1 SW1ACN3-ZCC: 10 SW00MN0-ZCC SW00MN0-ZCC: 1 SW00MN3-ZCC SW00MN3-ZCC: 10 OS(ITRON 4.0) SW1ARN5-ZCC: SW1ARNF-ZCC: DSU PROBE for ... Original
datasheet

4 pages,
238.99 Kb

TX19A TMP19A61CDXBG TMP19A61C10XBG TX19A abstract
datasheet frame
Abstract: 200910 TX19 TX19A TX19A 32 / 289 TMP19A61F10XBG TMP19A61F10XBG ADSIO/RISC TX19A TX19A CPU = 1.351.65V I/O = 1.653.3V ADC = 2.73.3V 54MHz (PLL4) ROM:1M RAM:48K 10AD : 32 DMA : 8 16 : 36 32 : 2 : 4 : 4 SIO/UART : 9 HSIO/UART : 2 I2C/SIO : 2 : 4 NANO FLASHTM ROM TMP19A61C10XBG TMP19A61C10XBG 1M RAM 48K TMP19A61CDXBG TMP19A61CDXBG 512K 40K FBGA289 FBGA289 C SW1ACN0-ZCC: 1 SW1ACN3-ZCC: 10 SW00MN0-ZCC SW00MN0-ZCC: 1 SW00MN3-ZCC SW00MN3-ZCC: 10 OS(ITRON 4.0) SW1ARN5-ZCC: SW1ARNF-ZCC ... Original
datasheet

4 pages,
314.8 Kb

tmp19a61 SW00MN0-ZCC TX19A TMP19A61F10XBG TX19A abstract
datasheet frame

Extended Electronics Archive (Experimental)

Abstract Saved from Date Saved File Size Type Download
Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer.
 
8HS: 54MHz 8-bit DAC - BD8HS: 54MHz current amplifier - AD8HS: 54MHz 8-bit ADC - AD1010 AD1010 AD1010 AD1010: 10MHz 10
www.datasheetarchive.com/files/atmel/atmel/cbic3-v3.htm
Atmel 26/05/1998 9.31 Kb HTM cbic3-v3.htm
the PLL to sync to the reference clock. This module is designed to work with a 54MHz reference , // 54MHz reference clock input reset, // async reset data, // serial data the 54MHz reference clock. // pd_54to270 pdref2vco ( .vco (vco), .refclk
www.datasheetarchive.com/download/18522930-995943ZC/xapp247.zip (xapp250_cdr.v)
Xilinx 03/12/2003 59.31 Kb ZIP xapp247.zip
_p, // 54MHz clock clk54M_n, // vco270M_p, // 270MHz VCO clock vco ]), .O(video_out[9]); // // 54MHz input clock buffer // // The 54Mhz clock is used as a not locked to the // SDI bitstream. There is nothing special about using 54MHz. This just happens for the // SDI receiver. It uses the 54MHz clock as a reference clock. This is a very // slightly cable equalizer carrier detect // signal to force the PLL to lock to the 54MHz reference whenever the
www.datasheetarchive.com/download/18522930-995943ZC/xapp247.zip (x247_rx_int_cdr.v)
Xilinx 03/12/2003 59.31 Kb ZIP xapp247.zip
Video Encoder with Six 10-bit DACs, 54 MHz Oversampling and Progressive General Description The ADV7192 ADV7192 ADV7192 ADV7192 is part of the new generation of video encoders from Analog Devices. The ADV7192 ADV7192 ADV7192 ADV7192 is an integrated Digital Video Encoder that converts Digital CCIR-601 CCIR-601 CCIR-601 CCIR-601 4:2:2 Component Video Data (8-, 16-bit) into a standard analog base band television signal compatible with NTSC, PAL B/D/G/H/I, PAL M, PAL N& PAL internal PLL to output data at 54MHz. Furthermore, it is possible to input data in progressive scan format
www.datasheetarchive.com/files/analog-devices/doc/productdescriptions/1629.html
Analog Devices 2.84 Kb HTML 1629.html
Description= 6- x 10-bit 54 MHz DAC Video Encoder with Macrovision® Copy Protection General Description The ADV7190 ADV7190 ADV7190 ADV7190 and ADV7191 ADV7191 ADV7191 ADV7191 are part of the new generation of video encoders from Analog Devices. The ADV7190 ADV7190 ADV7190 ADV7190 and ADV7191 ADV7191 ADV7191 ADV7191 are integrated Digital Video Encoders that convert Digital CCIR-601 CCIR-601 CCIR-601 CCIR-601 4:2:2 Component Video Data (8 or 16 bit) into a standard analog base band television signal compatible with NTSC and programmable Digital Noise Reduction 4xOversampling with an internal PLL to output data at 54MHz
www.datasheetarchive.com/files/analog-devices/gendesc/1619.htm
Analog Devices 05/06/2003 3.05 Kb HTM 1619.htm
Description= Video Encoder with Six 10-bit DACs, 54 MHz Oversampling and Progressive General Description The ADV7192 ADV7192 ADV7192 ADV7192 is part of the new generation of video encoders from Analog Devices. The ADV7192 ADV7192 ADV7192 ADV7192 is an integrated Digital Video Encoder that converts Digital CCIR-601 CCIR-601 CCIR-601 CCIR-601 4:2:2 Component Video Data (8-, 16-bit) into a standard analog base band television signal compatible with NTSC, PAL B/D/G/H/I, PAL M an internal PLL to output data at 54MHz. Furthermore, it is possible to input data in progressive
www.datasheetarchive.com/files/analog-devices/gendesc/1620.htm
Analog Devices 05/06/2003 2.93 Kb HTM 1620.htm
6- x 10-bit 54 MHz DAC Video Encoder with Macrovision Copy Protection General Description The ADV7190 ADV7190 ADV7190 ADV7190 and ADV7191 ADV7191 ADV7191 ADV7191 are part of the new generation of video encoders from Analog Devices. The ADV7190 ADV7190 ADV7190 ADV7190 and ADV7191 ADV7191 ADV7191 ADV7191 are integrated Digital Video Encoders that convert Digital CCIR-601 CCIR-601 CCIR-601 CCIR-601 4:2:2 Component Video Data (8 or 16 bit) into a standard analog base band television signal compatible with NTSC, PAL and programmable Digital Noise Reduction 4xOversampling with an internal PLL to output data at 54MHz
www.datasheetarchive.com/files/analog-devices/doc/productdescriptions/1628.html
Analog Devices 2.95 Kb HTML 1628.html
; //- // Signal definitions // wire clk_54M; // 54MHz clock after IOB wire attribute IOSTANDARD of XO54 is LVDSEXT_25_DT // // BUFG to buffer the 54 MHz clock and distribute encoder every other clock cycle. The txusrclk is 54 MHz, twice // the word-rate of SD-SDI. So, this generated. // // This module is clocked at 54 MHz and is enabled every other clock cycle by // the sd place in the video from // the video pattern generator. // // This module is clocked at 54 MHz and
www.datasheetarchive.com/download/58955026-996027ZC/xapp683.zip (sdv_sdsdi_rio_tx.v)
Xilinx 15/03/2004 67.57 Kb ZIP xapp683.zip
_ulogic; - 54MHz clock input clk54M_n: in std_ulogic; vco270M_p: in std ( O => video_out(9), I => rx_video(9); - - 54MHz input clock buffer - - The 54Mhz clock is used as a reference clock to the phase detector in bitstream. There is nothing special about using 54MHz. This just happens - to be a clock value that and data recovery unit for the - SDI receiver. It uses the 54MHz clock as a reference clock
www.datasheetarchive.com/download/18522930-995943ZC/xapp247.zip (x247_rx_int_cdr.vhd)
Xilinx 03/12/2003 59.31 Kb ZIP xapp247.zip
.305E-9 305E-9 305E-9 305E-9 G3 98 24 23 52 1 * * NEGATIVE ZERO AT -54MHZ * R6 25 26 1 R7 26 98 1E-6 * | | | | output * | | | | | .SUBCKT AD745J AD745J AD745J AD745J 3 2 99 50 37 * * INPUT STAGE AND POLE AT 54MHZ * I1 97 1 1 J1 5 2 1 JX J2 6 4 1 JX CIN 2 3 20E-12 20E-12 20E-12 20E-12 IOS
www.datasheetarchive.com/files/analog-devices/spice/models/ad745j.cir
Analog Devices 09/10/1995 3.24 Kb CIR ad745j.cir