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Part : DM54LS74AJ Supplier : Rochester Electronics LLC Manufacturer : Avnet Stock : - Best Price : - Price Each : -
Part : SN54LS74AJ Supplier : Texas Instruments Manufacturer : Avnet Stock : - Best Price : $5.49 Price Each : $6.39
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Part : JD54LS74B2A Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 320 Best Price : $6.88 Price Each : $6.88
Part : 54LS74A/BCAJC Supplier : Motorola Manufacturer : Bristol Electronics Stock : 495 Best Price : $2.0205 Price Each : $4.9280
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54LS/74LS73

Catalog Datasheet MFG & Type PDF Document Tags

TTL 74ls74

Abstract: 7474 14 PIN o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J , Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
TTL 74ls74 7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 54LS/74LS109 54LS/74LS74 54LS/74LS73 54LS/74LS107 54H/74H103 54LS/74LS76

74LS73

Abstract: pin diagram of 7473 54/7473 54H/74H73 54LS/74LS73 LOGIC SYMBOL DESCRIPTION The "73" is a dual Flip-Flop with , conventional operation. The 74LS73 is a negative edge triggered flip-flop. The J and K inputs must be stable , CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (b> PARAMETER TEST CONDITIONS 54/74 54H/74H 54S/74S 54LS/74LS , see inside back cover for 54S/74S and 54LS/74LS specification. signotics 107 This Material , Section 4 for Waveforms and Conditions) PARAMETER TEST CONDITIONS 54/74 54H/74H 54S/74S 54LS/74LS
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OCR Scan
74H73 N7473N N74H73N N74LS73N N7473F N74H73F pin diagram of 7473 74LS73 dual JK 7473 JK flip flop 7473 pin diagram 7473

CI 7474

Abstract: CI 7473 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J , Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , ) 1 Dual JK 54S/74S114 J,K X X X 125 5.0 150 D64 3I,6A,9A 2 Dual JK 54LS/74LS114 J,K ~L X X 60 12 20
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OCR Scan
CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54LS/74LS 54LS/74LS78 93L14 54LS/74LS279 54LS/74LS196 54LS/74LS197

TTL 74ls74

Abstract: 74ls74 o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J , Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are , 13 150 D61 3I, 6A, 9A 11 Dual D 54S/74S74 D T X X 100 7.0 150 D61 3I, 6A, 9A 12 Dual D 54LS/74LS74
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OCR Scan
74ls74 7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM 74H71 54H/74H101 54H/74H72 54H/74H102 54S/74S113 54LS/74LS113

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram 54/7473, 54H/74H73, 54LS/74LS73 *54/74107, ` 54LS/74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP , 4-Bit D Latch 54LS/74LS77 4-Bit D Latch 54LS/74LS75 4-Bit D Latch 4-Bit R S Latch 4-Bit D Latch 54LS/74LS197 4-Bit D Latch 54/74197 4-Bit D Latch 54/74196 4-Bit D Latch 4 , Function 54LS/74LS196 5477 9314 54/74279 54LS/74LS279 93L14 X O X O 4 *. X X Z D , ro - Item Dual JK 54LS/74LS78 c_ Dual JK Dual JK Dual JK Dual JK 54LS/74LS76
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OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74109 dual JK 74LS109 IC 74196 54LS/74LS77 54LS/74LS75

7473 JK flip flop

Abstract: IC 74LS73 73 CO NNECTIO N DIAGRAM PINOUT A 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP (With Separate Clears and Clocks) D E S C R IP TIO N - The '73 and 'H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled by the clock pulse. The clo ck pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of op eration is as follow s: 1) isolate slave from
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OCR Scan
IC 74LS73 74LS73D 7473PC JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 I/54LS/74LS73 54/74H 54/74LS CLS73

pin diagram for IC 7473

Abstract: 74LS73D ' NATIONAL SENICOND {LOGIO DEE D | b S D l l S E OOfc.3712 7 | 73 54/7473 54H/74H73 54LS/74LS73 DUAL JK FLIP-FLOP (W ith S ep arate Clears and Clocks) D ESC R IP TIO N - The '73 and 'H73 dual J K master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of op eration is as follows: 1) isolate
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OCR Scan
pin diagram for IC 7473 fan out 74ls73 IC 7473 ic 7473 pin diagram 5473DM

pin diagram for IC 7473

Abstract: 7473PC 73 54/7473 ^ /54H/74H73 c/fûic/ 1/54LS/74LS73 C?//c>/Z> DUAL JK FLIP-FLOP (With Separate Clears and Clocks) DESCRIPTION â'"The '73 and 'H73 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and K inputs
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OCR Scan
74LS73DC 74LS73PC 7473DC 7473FC 74H73DC 74H73FC 1/54LS/74LS73

74LS115

Abstract: 74LS273 reference to 54LS/74LS75. Refer to Page 5-48 for DC footnotes. Iih at Max Input Voltage, Vcc=Max _ _ =0.1 , Power TTL, 93L00 (MSI) Schottky T TL 54S/74S, 93S00 Low Power Schottky T TL 54LS/74LS V|L 0.8 0.8 , CATIONS B Device 5 4LS /74LS 00 5 4LS /74LS 02 5 4LS /74LS 03 5 4LS /74LS 04 54LS /74LS 05 54L S /7 4 LS 0 8 5 4 LS /74LS 09 5 4 LS /74LS 10 54LS/74LS 11 5 4 LS /74LS 13 54L S /7 4 LS 1 4 5 4 LS /74LS 15 5 4 LS /74LS 20 54LS/74LS 21 54LS /74LS 22 5 4 LS /74LS 26 5 4 LS /74LS 27 5 4 LS /74LS 28 54L
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OCR Scan
74LS115 74LS273 74LS00 QUAD 2-INPUT NAND GATE 74LS189 equivalent 74LS265 74LS93A

74ls373 parallel port

Abstract: d92 02 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12 , ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De
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OCR Scan
74ls373 parallel port d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl 54LS/74LS541 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374

74LS160

Abstract: Synchronous 74163 Up/Down U p/D own 93L16 93S16 54/74160 54LS/74LS160 54/74161 54LS/74LS161 54/74162 54LS/74LS162 54/74163 54LS/74LS163 54LS/74LS168 54LS/74LS169 54/74192 54LS/74LS192 54/74193 54LS/74LS193 54/74190 , /7490A, 54LS/74LS90 6 7 D122 54/7492, 74LS92 D123 54/74293, 54LS/74LS293 CPo CP, MR Qo Qi 0 2 0 , Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93 D125 54/74176, 54/74177, 54/74196, 54LS/74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 D126 9305
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OCR Scan
93S05 74LS160 Synchronous 74163 74192 74LS190 pins 74LS193 74LS191 pins 54LS/74LS160 54LS/74LS161 54LS/74LS162 54LS/74LS163 54LS/74LS192 54LS/74LS193

MUX 74157

Abstract: 74157 mux FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S/74S153, 54LS/74LS153, 54S/74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U
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OCR Scan
MUX 74157 74157 mux 74153 mux mux 74153 74298 quad 2 in mux TTL 74153 54LS/74LS170 54LS/74LS670 93L09 54LS/74LS298 54LS/74LS157 54LS/74LS158

74153 mux

Abstract: MUX 74157 FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa , /74153, 54S/74S153, 54LS/74LS153, 54S/74S253, 54LS/74L8253 1 6 5 4 3 10 11 12 13 15 JM I I I I I I U
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OCR Scan
74174 shift register CI 74151 74LS152 MUX 74151 D flip-flop 74175 pin quad D flip-flop 74175 pin 54LS/74LS257 54LS/74LS258 54LS/74LS153 54LS/74L8253 93L12 93S12

ci 74174

Abstract: D flip-flop 74175 pin /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc = Pin 4 GND = Pin 11 NC = Pins 7, 10 D152 54/74174, 54S/74S174, 54LS/74LS174 3 4 6 11 13 14 Do Di D2
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OCR Scan
ci 74174 7475 D flip-flop 9374 74116 74174 7477 D latch 93L08 54LS/74LS175 54LS/74LS174 93L38 54LS/74LS256

trigger 74114

Abstract: 74114 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D65 54/7413, 54LS/74LS13 Vcc NC HKiEiraiaram 3 LlI lil Id li] li] LàJ Ui NC QND D66 54/74125, 54LS/74LS125 Vcc E D O E D O ism a ra a in ~?i r?i Lj ui lii y ili iii u E D O E D O QND D67 54/74126, 54LS/74LS126 Vcc E D O E DO ZrhTrh liiiiiiiiiiiiiiiijiij E D O E D O GND D68 54LS/74LS365 Vcc I2 |i«l Fsl [i«l [wl Fai R |io| f»l rih yrrrr lil liJ LiJ U liJ LsJ lil Id Ei GND D69 54LS/74LS366 Vcc E2 EI EI ra ra EI R
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OCR Scan
9S05A trigger 74114 74114 IC 7404 74ls04 hex inverter gates 74LS13 IC 7413 54LS/74LS13 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366 54LS/74LS367

IC TTL 7432

Abstract: 74LS86 gate diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR lillkililliJliJlilliJliJ GND D20 54/7432, 54S/74S32 54LS/74LS32 ei ei ei m ei iti fi Elfi LlJ liJ LiJ LiJ Iii Iii Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI
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OCR Scan
74LS266 IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram IC 7486 54LS/74LS08 54LS/74LS09 54LS/74LS21 54LS/74LS32 54LS/74LS11 54LS/74LS15

ALU IC 74181

Abstract: 74181 ic pin diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 54/7409, 54S/74S09, 54LS/74LS09 Vcc ) EI EI na fri EI iyi FI ¿J a lil liJ Li] Iii liJ 111 llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR lillkililliJliJlilliJliJ GND D20 54/7432, 54S/74S32 54LS/74LS32 ei ei ei m ei iti fi Elfi LlJ liJ LiJ LiJ Iii Iii Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI
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OCR Scan
ALU IC 74181 74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder IC 74181 54S/74S86 54LS/74LS86 54LS/74LS136 54S/74S135 54LS/74LS379 54LS/74LS386

ITT 7400

Abstract: 74h01 - 9004 - - 9009 - 9007 - - - 54LS/74LS04 54/7404 54LS/74LS05 54/7405 - - 54/7416 54/7406 54H , a > a < 0 U < 0 0. 54LS/74LS14 54/7414 54LS/74LS00 54/7400 54LS/74LS03 54/7403 - 54/7401 54LS/74LS26 7426 54LS/74LS37 54/7437 74LS38 - 74LS132 54/7438 54/7439 54/74132 54LS/74LS10 54/7410 - 54/7412 54LS/74LS20 54/7420 54LS/74LS13 54/7413 54LS/74LS22 54/7422 54LS/74LS40 54/7440 - - - - 54LS/74LS30 54/7430 54LS/74LS133 - - - N otes on follow ing pages 9-3 FAIRCHILD LOGIC
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OCR Scan
ITT 7400 74h01 74H04 TTL 7414 fairchild 7404 74h00 OC/48 54LS/74LS04 54LS/74LS05 54H/74H04 54H/74H05 54H/74H00

IC 7404 7406

Abstract: 74LS00 7400 74S00 , 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS/74LS03, 7426, 54LS/74LS26 54/7437, 54LS/74LS37, 54/7438, 74LS38, 54/74132, 54S/74S132, 74LS132 03 54 , /74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S/74S20, 54LS/74LS20, 54/7422, 54H/74H22, 74S22, 54LS/74LS22, 9009, 54/7440, 54H/74H40, 54S/74S40, 54LS
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OCR Scan
IC 7404 7406 74LS00 7400 74S00 IC TTL 74LS00 ic 74132 Fairchild 9002 TTL 74h04 54S/74S04 54LS/74LS14 54LS/74LS00 54LS/74LS03 54LS/74LS26 54LS/74LS37

74LS255

Abstract: 54LS Digital Circuits 9LS/54LS/74LS Low Power Schottky (Cont.) Prop D elay1 (ns) or Max. Op. Freq. Type Number 9LS/54 LS/74LS190 9LS/54LS/74LS191 9LS/54LS/74LS192 9LS/54LS/74LS193 9 LS/54 LS/74 LSI 94 A 9 LS/54 LS/74LS195A 9LS/54LS/74LS196 9 LS/54 LS/74 L S 19 7 9LS/54LS/74LS221 9LS/54LS/74LS251 9LS/54LS/74LS253 9LS/54LS/74LS255 9LS/54LS/74LS257 9LS/54LS/74LS258 9LS/54 LS/74 LS26t 9LS/54LS/74 LS266 9LS/54LS/74LS279 9LS/54LS/74LS283 9 LS/54 LS/74 LS295A 9LS/54LS/74LS298 9LS/54LS/74LS365 9 LS/54 LS/74
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OCR Scan
74LS255 54LS 74LS367 74LS258 ls386 54LS/74LS191 9LS/54LS/74LS 9LS/54LS/74LS191 9LS/54LS/74LS192 9LS/54LS/74LS193 9LS/54LS/74LS196 9LS/54LS/74LS221
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