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Part : 54LS74LMQB Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 1,775 Best Price : $6.03 Price Each : $6.03
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54LS/74LS373

Catalog Datasheet MFG & Type PDF Document Tags

SN74LS573

Abstract: Advance Information SN54LS573/SN74LS573 OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS G EN E R A L DESCRIPTION - The 54LS/74LS573 is a High-Speed Octal Latch with Buffered Common Latch Enable (LE) and Buffered Common Output Enable (OE) inputs. This device is functionally identical to the 54LS/74LS373, but , , please refer to the 54LS/74LS373 Data Sheet. LO GIC SYMBOL 2 3 4 5 6 7 8 9 Do , ICROPROCESSORS FU N C TIO N A LLY ID EN TICA L TO 54LS/74LS373 INPUT CLAMP DIODES LIM IT HIGH-SPEED TERMINATION
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OCR Scan
SN74LS573 54LS/74LS573 54LS/74LS373

IC 74ls373

Abstract: 74LS373 screening to MIL-STD-883 requirements FUNCTIONAL DESCRIPTION The Am25LS/54LS/74LS373 and Am25LS/54LS , Don't Care DEFINITION OF FUNCTIONAL TERMS Am25LS/54LS/74LS373 D, The latch data inputs. G The latch , Transparent L H H L L L L X NC NC Latched 2-66 Am25 LS/54 LS/74 LS373/533 Am25LS/54LS/74LS373 SWITCHING , D4 12 Y4 11 G APPLICATION Metallization and Pad Layouts Am25LS/54LS/74LS373 Am25LS/54LS/74LS533 , Am25LS373 â'¢ Am54LS/74LS373 Am25LS533 â'¢ Am54LS/74LS533 Octal Latches with Three-State
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OCR Scan
74LS533 SN74LS373N AM25LS533DC IC 74ls373 74LS373 40 pin 74LS 25LS373 25LS533 54LS/74LS533 LS373 LS533 54LS/74LS

LOGIC DESCRIPTION OF 74LS373

Abstract: 74ls373 screening to MIL-STD-883 requirements FUNCTIONAL DESCRIPTION The Am25LS/54LS/74LS373 and Am25LS/54LS , non-inverted data at the outputs while the 'LS533 is inverting. LOGIC DIAGRAM Am25LS/54LS/74LS373 Inputs Dq , TERMS Am25LS/54LS/74LS373 Dj The latch data inputs. G The latch enable input. The latches are , Copyrighted By Its Respective Manufacturer Am25 LS/54 LS/74 LS373/533 Am25LS/54LS/74LS373 SWITCHING , Am25LS373 â'¢ Am54LS/74LS373 Am25LS533 â'¢ Am54LS/74LS533 Octal Latches with Three-State
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OCR Scan
SN74LS373J SN74LS533N LOGIC DESCRIPTION OF 74LS373 am8085 LS74 AM25LS 25LS/54LS/74LS373 25LS/54LS/74LS533 AM25LS373PC AM25LS373DC AM25LS373XC AM25LS373DM

SN74LS573

Abstract: SN54LS573 Advance Information SN54LS573/SN74LS573 OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS This device is functionally identical to the 54LS/74LS373. but has different oin- ^â"¢TCSF0AÃ:7wrTH0Ã'i2^RMlBoSsF PACKAGE ALLOW,NG FIJLLY tt^and^MOS^ompati^LE^'^''^^^ TERM.NAT.ON EFFECTS PIN NAMES Do - D7 LE_ OE Oo - Or LOADING (Note a) Data Inputs Latch Enable (Active HIGH) Input Output Enable (Active LOW) Input Outputs (Note b) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L
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OCR Scan
SN54LS573 sta 741 a 34S67 VW44444

74LS191

Abstract: D129 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
93L16 93S16 74LS191 D129 74162 74192 pin diagram of 74163 74160 pin 54LS/74LS541 54LS/74LS78 54LS/74LS168 54LS/74LS169 54LS/74LS490 54LS/74LS374

D flip-flop 74175 pin

Abstract: 74LS78 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , '" K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi
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OCR Scan
D flip-flop 74175 pin 74LS78 74LS374 D134 D150 D190 54LS/74LS256 54LS/74LS375 54LS/74LS298 93L08 54S/74S174 54LS/74LS174

74ls373 parallel port

Abstract: d92 02 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi
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OCR Scan
74ls373 parallel port d92 02 74175 ttl pin diagram 74ls175 pin diagram 74198 74198 ttl 54LS/74LS194 93L34 54LS/74LS259

74LS93 P

Abstract: TTL 74LS93 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
93L10 74LS93 P TTL 74LS93 TTL 74293 74293 pin diagram 74176 74293 54/7490A 54LS/74LS90 74LS92 54/7493A 54LS/74LS93 54LS/74LS196

7475 D latch

Abstract: D146 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
7475 D latch D146 D147 74LS109 ci 7475 rs latch 54S/74S114 54LS/74LS114 54S/74S109 54LS/74LS109 54LS/74LS76 54LS/74LS107

ttl 741

Abstract: 1. IC 74IS244 ,10 Vcc = Pin 16 GND = Pin 8 D85 54LS/74LS373 3 4 7 8 13 14 17 18 INN 11- Do LE Di D2 D3 D4 Ds De , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
74S140 74S40 ttl 741 1. IC 74IS244 74LS244 diagram Fairchild 96106 90CI9 54H/74H40 54LS/ 74LS245

74LS373PC

Abstract: 74LS373P 373 / 54LS/74LS373 OCTAL TRANSPARENT LATCH (With 3-State Outputs) otU* 1 DESCRIPTION â'"The '373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LB is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. â'¢ EIGHT LATCHES IN A SINGLE PACKAGE â'¢ 3
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OCR Scan
74LS373PC 74LS373DC 74LS373FC 54LS373DM 54LS373FM 74LS373P e10s LS 373 74LS373D 54/74LS

7475 d-flip flop

Abstract: 7475 D flip-flop D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc =
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OCR Scan
93L14 7475 d-flip flop 7475 D flip-flop 74LS573 D145 D148 54LS/74LS279 54LS/74LS75 54LS/74LS77 54LS/74LS175 93L38

74LS573

Abstract: 74LS573 "LATCH" '" K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D177 9328, 93L28 D178 54/7491 D179 54LS , ~ GND Pin 5 = Pin 10 Vcc = Pin 20 GND = Pin 10 0180 54LS/74LS352 D181 54LS/74LS353 1 6 5 4 3 10 11 , (Typ) Logic/Connection Diagram Package(s) 1 4-Bit D Latch 54LS/74LS375 4xD â'" 2(H) 20 10 10 32 D190 , 54LS/74LS175 4xD L K-T) 20 21 â'" 55 D150 4L,6B,9B 4 4-Bit D Flip-Flop 54S/74S175 4xD L 1U~) 7.0 10 â
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OCR Scan
74LS573 "LATCH" 74LS573 latch d flip-flop 7491 8-bit 7491 fairchild D177 54LS/74LS352 54LS/74LS353 54LS/74LS170

D flip-flop 74175 pin

Abstract: 74175 D flip flop (2)/74LS374 8xD â'" K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 , 6 Vcc = Pin 16 GND = Pin 8 I ? I 13 5 6 Vcc = Pin 16 GND = Pin 8 0189 54LS/74LS173 9 10 14 13 , » . Oz Oy MR Oo 0i 02 03 MR 15 3 4 5 8 Vcc = Pin 16 GND = Pin 8 D190 54LS/74LS375 D194 54LS , Pin 8 D195 54LS/74LS393 (each half) 1, 13- CP MR Oo 0i 02 03 2, 12 4, 10 6, I 3, 11 5, 9 Vcc = Pin 14 GND = Pin 7 2-10- D196 54LS/74LS395 7 3 4 5 6 I I I I I a Po Pi Pi p3 t>s CP OE MR O0 O
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OCR Scan
74175 D flip flop 8-bit ttl latch latch 74LS374 D187 D188 D194 54LS/74LS173 54LS/74LS390 54LS/74LS393 54LS/74LS395

74153 mux

Abstract: MUX 74157 )/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 8xD â'" 1(L) â'" â'" â'" â , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa
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OCR Scan
74153 mux MUX 74157 74174 shift register 74157 mux CI 74151 74LS152 54LS/74LS670 93L09 54LS/74LS157 54LS/74LS158 54LS/74LS257 54LS/74LS258

74191 8 bit

Abstract: 7443 Flip-Flop '" K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8 , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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OCR Scan
74LS190 74191 8 bit 7443 Flip-Flop 7443 d Flip-Flop 74LS42 D135 93L11 54LS/74LS139 54LS/74LS155 54LS/74LS156 54LS/74LS42 54LS/74LS145

ci 74174

Abstract: D flip-flop 74175 pin 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc =
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OCR Scan
ci 74174 9374 74116 74174 7477 D latch CI 74LS194 54ILS/74LS670

7475 D flip-flop

Abstract: quad D flip-flop 74175 pin (2)/74LS374 8xD â'" K-T) 10 23 23 135 D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc =
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OCR Scan
quad D flip-flop 74175 pin 4 bit shift register 7494 pin diagram latch 74ls574 74LS173 4 bit 3 state quad register 74LS279 D151

74191 8 bit

Abstract: 74155 PIN DIAGRAM 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2)/74LS573 , 9321, 93L21, 54/74S139, 54LS/74LS139 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 11 15 1 10 9 , 12 Vcc = Pin 16 GND = Pin 8 D133 9301, 93L01, 9302 D134 9334, 93L34, 54LS/74LS259 TTTTTTTTTT 13 , D135 54/7442, 54LS/74LS42, 54/7443, 54/7444, 54/7445 54/74145, 54LS/74LS145 15 14 13 12 TTTTTTTTTT 1 23456 79 10 11 Vcc = Pin 16 GND = Pin 8 D136 54S/74S138, 54LS/74LS138 1 2 3 4 5C â Iii- e
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OCR Scan
74155 PIN DIAGRAM D133 7442 logic diagram 74155 D132 pin diagram of 74LS191 54LS/74LS138 93S138 93S137 54/74151A

MUX 74157

Abstract: 74157 mux D86 9Z 15 8-Bit D Latch 54LS(2)/74LS373 8xD â'" 1(H) 15 24 16 120 D85 9Z 16 8-Bit D Latch 54LS(2 , FAIRCHILD LOGIC/CONNECTION DIAGRAMS D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 , 54/74298, 54LS/74LS298 3 2 4 1 9 5 7 6 ioli - loa Ila lob lib s toc 11 c lOd lld CP Oa Ob Oc Od 15 14 13 12 Vcc = Pin 16 GND = Pin 8 D157 9322, 93L22, 54/74157, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257,54LS/74LS257, 54S/74S258, 54LS/74LS258 15 2 3 5 6 14 13 11 10 E loa
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OCR Scan
mux 74153 74298 quad 2 in mux TTL 74153 ttl 74157 pin diagram of 74153 74157 pin diagram 54S/74S153 54LS/74LS153 54S/74S253 54LS/74L8253 93L12 93S12
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