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Part : 54LS74LMQB Supplier : National Semiconductor Manufacturer : Rochester Electronics Stock : 1,775 Best Price : $4.90 Price Each : $6.03
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54LS/74LS197

Catalog Datasheet MFG & Type PDF Document Tags

CI 74LS90

Abstract: ci 74193 /74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 Alili PL Po Pi P2 P3 14-0 CPo 6â'"O CPo 1â'"O CPi , Asynchronous 54/74197 2x8 A 70 52 240 D125 3I,6A,9A 14 Asynchronous 54LS/74LS197 2x8 A ~L 70 60 60 D125 3I,6A , 4-Bit D Latch 54LS/74LS197 4xD L 1(U 20 28 24 60 D125 3I,6A,9A 21 4-Bit D Latch 54LS/74LS75 4xD â , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo
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OCR Scan
CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 54LS/74LS90 54LS/74LS293 S4/7493A 54LS/74LS93 93L10 93S10

sn 7492 ttl

Abstract: 74293 pin diagram /74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 Alili PL Po Pi P2 P3 14-0 CPo 6â'"O CPo 1â'"O CPi , Asynchronous 54/74197 2x8 A 70 52 240 D125 3I,6A,9A 14 Asynchronous 54LS/74LS197 2x8 A ~L 70 60 60 D125 3I,6A , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10
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sn 7492 ttl 74293 pin diagram TTL 7493A TTL 74293 7493A 74162 93L16 93S16 54LS/74LS160 54LS/74LS161 54LS/74LS196 54LS/74LS197

TTL 74293

Abstract: 74LS90 /74290 54/7490A 54LS/74LS90 54/7492 74LS92 54/74293 54/7493A 54LS/74LS93 54/74176 54/74177 54/74196 54LS/74LS196 54/74197 54LS/74LS197 54LS/74LS290 54LS/74LS293 54LS/74LS390 54LS/74LS393 54LS/74LS490 9305 93S05
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OCR Scan
74LS90 D127 74290 7490 D124 74LS93 54LS/74LS290 54LS/74LS390 54LS/74LS393 54LS/74LS490

74LS183

Abstract: 74LS193 /74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 Alili PL Po Pi P2 P3 14-0 CPo 6â'"O CPo 1â'"O CPi , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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OCR Scan
74LS183 74LS193 TTL 7490 54LS TTL 74LS93 ttl 7493 54LS/74LS162 54LS/74LS163 54L8/74LS192 54LS/74LS193

TTL 74293

Abstract: 7490A 54/74197 2x8 A 70 52 240 D125 3I,6A,9A 14 Asynchronous 54LS/74LS197 2x8 A ~L 70 60 60 D125 3I,6A,9A , 6 Vcc = Pin 16 GND = Pin 8 I ? I 13 5 6 Vcc = Pin 16 GND = Pin 8 0189 54LS/74LS173 9 10 14 13 , » . Oz Oy MR Oo 0i 02 03 MR 15 3 4 5 8 Vcc = Pin 16 GND = Pin 8 D190 54LS/74LS375 D194 54LS , Pin 8 D195 54LS/74LS393 (each half) 1, 13- CP MR Oo 0i 02 03 2, 12 4, 10 6, I 3, 11 5, 9 Vcc = Pin 14 GND = Pin 7 2-10- D196 54LS/74LS395 7 3 4 5 6 I I I I I a Po Pi Pi p3 t>s CP OE MR O0 O
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OCR Scan
7490A ttl 74LS173 74LS293 pin D188 D190 D194 54LS/74LS173 54LS/74LS375 54LS/74LS395

multiplexers 74 LS 150

Abstract: 74LS255 /74LS197 4-bit presettable binary counter 35 MHz 60 X X 9LS/54LS/74LS221 Dual one-shot 40 95* X X , Digital Circuits 9LS/54LS/74LS Low Power Schottky (Cont.) Type Number Description Prop Delay1 , ) J w J w J w 9LS/54LS/74LS190 BCD decade counter, mode control 25 MHz 90 X X 9LS/54LS/74LS191 4-bit binary counter, mode control 25 MHz 90 X X 9LS/54LS/74LS192 BCD decade counter, up/down 30 MHz 85 X X 9LS/54LS/74LS193 4-bit binary counter, up/down 30 MHz 85 X X 9 LS/54 LS/74 LSI 94 A 4
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LS196 LS367 LS386 LS670 multiplexers 74 LS 150 74LS255 74LS190 up down decade counter 74LS190 pins bcd counter 74 90 74LS192 pins 9LS/54LS/74LS 9LS/54LS/74LS190 9LS/54LS/74LS191 9LS/54LS/74LS192 9LS/54LS/74LS193 9LS/54LS/74LS195A

74LS160

Abstract: Synchronous 74163 Pin 10 NC = 2, 3, 4, 13 Vcc = Pin 14 GND = Pin 7 NC = Pins 1, 2, 3, 6 D124 54/7493A, 54LS/74LS93 D125 54/74176, 54/74177, 54/74196, 54LS/74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 D126 9305 , Up/Down U p/D own 93L16 93S16 54/74160 54LS/74LS160 54/74161 54LS/74LS161 54/74162 54LS/74LS162 54/74163 54LS/74LS163 54LS/74LS168 54LS/74LS169 54/74192 54LS/74LS192 54/74193 54LS/74LS193 54/74190 , /7490A, 54LS/74LS90 6 7 D122 54/7492, 74LS92 D123 54/74293, 54LS/74LS293 CPo CP, MR Qo Qi 0 2 0
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OCR Scan
74LS160 Synchronous 74163 74192 74LS191 pins Fairchild 74190 D129 54LS/74LS168 54LS/74LS169 54LS/74LS192 74LS190 74LS191

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram 4-Bit D Latch 54LS/74LS77 4-Bit D Latch 54LS/74LS75 4-Bit D Latch 4-Bit R S Latch 4-Bit D Latch 54LS/74LS197 4-Bit D Latch 54/74197 4-Bit D Latch 54/74196 4-Bit D Latch 4 , Function 54LS/74LS196 5477 9314 54/74279 54LS/74LS279 93L14 X O X O 4 *. X X Z D , ro - Item Dual JK 54LS/74LS78 c_ Dual JK Dual JK Dual JK Dual JK 54LS/74LS76 c_ Dual JK Dual JK O c w c_ Function cn (0 £k C/5 © CO 54LS/74LS109 9024,54
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OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram 74LS107 ic 74109 74109 dual JK 74LS109 54LS/74LS77 54LS/74LS75 54LS/74LS279 54S/74S109 54LS/74LS109 54H/74H74

74LS190 pins

Abstract: 74LS192 PIN diagram /74LS196, 54/74197, 54LS/74LS197 1 4 10 3 11 Alili PL Po Pi P2 P3 14-0 CPo 6â'"O CPo 1â'"O CPi , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D121 54/7490A, 54LS/74LS90 14-1- 6 7 ü MS , , 74LS92 14- 1 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D123 S4/74293, 54LS/74LS293 ioli» CPo , , 54LS/74LS93 IT 2 3 12 9 8 11 Vcc Pin 5 GND = Pin 10 NC = Pins 4, 6, 7, 13 D127 9310, 93L10, 93S10, 9316, 93L16, 93S16 54/74160, 54LS/74LS160, 54/74161, 54LS/74LS161 9 3 4 5 6 PE Po Pi P2 P3 7- CEP
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OCR Scan
74LS192 PIN diagram TTL 74ls163 74LS161 74160 74LS162 74LS192 54LS/74L

d146

Abstract: RS latch /74LS197 4xD L 1(U 20 28 24 60 D125 3I,6A,9A 21 4-Bit D Latch 54LS/74LS75 4xD â'" 2(H) 20 10 10 32 D148 4L , /74H106 4 â'" 0 â'"15 â'" Q 1-0 CP 6-0 CP 16â'" K _ CD Q 0-14 « 0 D62 54S/74S112, 54LS/74LS112 , 0-3 8_ K Cd 0 D63 54S/74S113, 54LS/74LS113 3 â'" 0 -5 11 a 1-0 CP 13-0 CP 2â'" K 0 0â'"6 12- K Q Vcc = Pin 14 GND = Pin 7 Vcc = Pin 14 GND = Pin 7 D64 54S/74S114, 54LS/74LS114 4 J , 150 D64 3I,6A,9A 2 Dual JK 54LS/74LS114 J,K ~L X X 60 12 20 D64 3I,6A,9A 3 Dual JK 9024,54/74109 J,K
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OCR Scan
d146 RS latch 74LS78 7475 D latch d147 74LS114 54H/74H78 54H/74H106 54LS/74LS112 54H/74H108 54LS/74LS113 54LS/74LS114

ci 7475

Abstract: D147 4-Bit D Latch 54LS/74LS197 4xD L 1(U 20 28 24 60 D125 3I,6A,9A 21 4-Bit D Latch 54LS/74LS75 4xD â , /74279, 54LS/74LS279 7 1 2 6 3 5 il Ao Ai A2 A3 El RBI RBO a b c d e I 9 TTTTTTTT 4 13 12 11 10 9 , /7475, 54LS/74LS75 Di O2 D3 DA 13 â'"O E0-1 4 â'"0 E2-3 Qi 02 03 04 VI Â¥ IVIY 16 1 15 14 , /7477, 54LS/74LS77 12 5 6 12 â'"O 3 2 3 4 6 8 10 Eoi IE, BINI "tí 14 15 16 18 20 22 Eoi I El I , 9 11 13 17 19 21 23 I I I I D150 54/74175, 54S/74S175, 54LS/74LS175 4 5 12 13 14 13 9 8 Vcc =
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OCR Scan
ci 7475 74L576 TTL 7475 fairchild 9314 pin diagram 7475 74279 93L08 54LS/74LS175 54S/74S174 54LS/74LS174 93L38 54LS/74LS76
Abstract: - ì NATIONAL SEflICOND { L O G I C * OSE D | ¿,501125 0 0 ^ 3 7 T | _ - T - V 5 - ^ 3 -l3 _ 1 9 7 CO NNECTIO N DIAGRAM PINOUT A 54/74197 54LS/74LS197 PRESETTABLE BINARY COUNTERS DESCRIPTION - The '197 rippie counter contains divide-by-tw o and divideby-e igh t sections w h ich can be com bined to form a m odulo-16 binary counter. State changes are initiated by the falling edge of the clock. T h e '197 has a Master Reset (MR) in put which overrides all other -
OCR Scan
74197PC 74LS197PC 74197DC 74LS197DC 74197FC 74LS197FC

TTL 74293

Abstract: 7490A /74LS197 2x8 A ~L 70 60 60 D125 3I,6A,9A 15 Asynchronous 54LS/74LS290 2x5 _ 42 12 45 D120 3I,6A,9A 16 , 9 12 Vcc = Pin 14 GND = Pin 7 D120 54/74290, 54LS/74LS290 1 3 Ã b a, a2 a3 a4 IOâ'"o MS CPo , Asynchronous 54/7490A 2x5 â'" 40 33 160 D121 3I,6A,9A 3 Asynchronous 54LS/74LS90 2x5 â'" "L 50 33 45 D12I 3I , 2x8 â'" 40 46 160 D124 3I,6A,9A 8 Asynchronous 54LS/74LS93 2x8 _ ~L 50 46 45 D124 3I,6A,9A 9 , ,9A 11 Asynchronous 54/74196 2x5 A "L 70 38 240 D125 3I,6A,9A 12 Asynchronous 54LS/74LS196 2x5 A "U
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OCR Scan
93S43 93S62 74196 TTL D114 D115 D116 93H87/74H87

74LS93 P

Abstract: TTL 74LS93 Asynchronous 54LS/74LS197 2x8 A ~L 70 60 60 D125 3I,6A,9A 15 Asynchronous 54LS/74LS290 2x5 _ 42 12 45 D120 3I , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
74LS93 P 74LS373 74176 74293 74LS490 74ls90 PIN DIAGRAM 54LS/74LS541 54LS/74LS78 54LS/74LS373 54LS/74LS374 54LS/74LS256

7475 D latch

Abstract: D146 20 4-Bit D Latch 54LS/74LS197 4xD L 1(U 20 28 24 60 D125 3I,6A,9A 21 4-Bit D Latch 54LS/74LS75 4xD â , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D81 54LS/74LS541 Vcc -.,., 1 â'"_ _ â'¢â'" J r r* 5 Ii] Iii liJ L±J Iii LAJ Lil liJ liJ bsl QND D82 54LS/74LS78 J SD 0 CP K CD Q -13 lo- ftâ'"12 6 i SD J 0 CP K CD Q D83 54LS/74LS168, 54LS/74LS169 9 3 4 5 6 mil PE Po Pi Pi P3 1 - U/D 7â'"0 10â'"0 CEP CET TC 2- CP Oo Qi 02 O3 D84 54LS/74LS490 (each half) 4,12
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OCR Scan
7475 data latch CI 74109 74ls76 Fairchild 902 1L20 TTL 74109 54LS/74LS107

CI 7474

Abstract: CI 7473 240 D125 3I,6A,9A 20 4-Bit D Latch 54LS/74LS197 4xD L 1(U 20 28 24 60 D125 3I,6A,9A 21 4-Bit D Latch , Cd D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 11 ~LT 2 â'" J SD 0 _6 14 0 4 â'" CP 12 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J , /7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 54LS/74LS74 54LS/74LS73 54H/74H103 54LS/74LS

counter 54LS/74LS

Abstract: N74LS197F 54/74197-See 8291 54S/74S197-See 82S91 54LS/74LS197 LOGIC SYMBOL 10 3 11 FEATURES â'¢ High , AND FAN-OUT TABLE(a) PINS DESCRIPTION 54/74 54S/74S 54LS/74LS CPo Clock (active LOW going edge , 54LS/74LS UNIT Min Max Min Max Min Max ICC Supply current Vcc = Max 27 mA AC CHARACTERISTICS: TA=25°C (See Section 4 for Test Circuits and Conditions) 54/74 54S/74S 54LS/74LS , Manufacturer 359 PARAMETER 54/74 54S/74S 54LS/74LS TEST CONDITIONS Min Max Min Max Min Max UNIT
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OCR Scan
N74LS197N N74LS197F S54LS197F S54LS197W counter 54LS/74LS 74S197 54/74197-S 54S/74S197-S

74LS196

Abstract: LS196 a bi-quinary mode producing a 50% duty cycle output. The SN54LS/74LS197 contains divide-by-two and , inputs when PL is LOW and storing the data when PL is HIGH. SN54LS/74LS196 SN54LS/74LS197 4 , SN54LS/74LS196 · SNS4LS/74LS197 LOGIC DIAG R AM LS196 © © ® CPri- iS D Q J SD Q , Pin 7 Q = Pin Num bers MOTOROLA SCHOTTKY TTL DEVICES SNB4LS/74LS196 · SN64LS/74LS197 , /74LS197 GUARANTEED OPERATING RANGES SYMBOL V CC ta PARAMETER Supply Voltage O perating A m b ie n
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OCR Scan
74LS196 LS197 SN54LS/74LS197

74LS196

Abstract: ls197 ,2 ,1 ) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains , SN54/74LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS LOW POWER SCHOTTKY J S U FFIX C E R A M IC C A , pinouts (C onnection D iagram ) as the D ual In-Line P ackage. ORDERING INFORMATION S N 54LS X X X J S , /74LS196 · SN54/74LS197 LOGIC DIAGRAM LS196 MR CP0 CPi L S I 97 V q c = PIN 14 G N D = PIN 7 0 = PIN N U M BERS FAST AND LS TTL DATA SN54/74LS196 · SN54/74LS197 FUNCTIONAL
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OCR Scan
SN54/74LS197
Abstract: (g ) MOTOROLA SN54/74LS196 SN54/74LS197 4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54 , output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to , Po QO CPì ORDERING INFORMATION S N 54LS X X X J S N 74LS X X X N S N 74LS X X X D C , /74LS197 LOGIC DIAGRAM LS197 V c c = PIN 14 GND = PIN 7 0 = PIN NUMBERS FAST AND LS TTL DATA 5-229 SN54/74LS196 â'¢ SN54/74LS197 FUNCTIONAL DESCRIPTION The LS196 and LS197 are -
OCR Scan
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