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54H/74H78

Catalog Datasheet MFG & Type PDF Document Tags

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 ¿ 10 i , Dual JK 54LS/74LS112 J, K X X 60 12 20 D62 4L,6B,9B 26 Dual JK 54H/74H78 J, K X X 30 22 160 D59a 3I , < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H , Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q , 16 100 D50 3I, 6A 2 Single JK 9001 2J, 2K, J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H
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OCR Scan
7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 54H/74H78 54H/74H106 54S/74S112 54H/74H108 54S/74S113 54LS/74LS113

7472 PIN DIAGRAM

Abstract: 74574 60 12 20 D62 4L,6B,9B 26 Dual JK 54H/74H78 J, K X X 30 22 160 D59a 3I,6A,9A 27 Dual JK 54H/74H108 , a. H o D52a 54H/74H71 D52b 54H/74H101 1 2 3 â'¢ 4 13 9-10 11 -12- SD J O CP K Q So J O â'" 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 1ÌE0 J S° o â'" 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED , , J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H/74H71 (AOI) (2+2) J, (2+2) K X _ 30 22 95
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OCR Scan
74574 TTL 7472 7473 dual JK 7472 ttl O9111 7472 ci 54H/74H71 54H/74H101 54H/74H72 54H/74H102 74H71 54H/74H74

d146

Abstract: RS latch FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 ¿ 10 i 4â'" O â'"2 11^ 0 9â'" CP Lo CP 1 â'" 0 0-3 8_ K _ Co Q _TL Ul O O ul (9 Z 5 (9 > H < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H/74H106 4 â'" 0 â'"15 â'" Q 1-0 CP 6-0 CP 16â'" K _ CD Q 0-14 « 0 D62 54S/74S112, 54LS/74LS112 , Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q
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OCR Scan
d146 RS latch 74LS78 7475 D latch d147 74LS114 54S/74S114 54LS/74LS114 54S/74S109 54LS/74LS109 54LS/74LS76 54LS/74LS107

TTL 74ls74

Abstract: 74ls74 ,6B,9B 26 Dual JK 54H/74H78 J, K X X 30 22 160 D59a 3I,6A,9A 27 Dual JK 54H/74H108 J, K "L X X 50 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54/7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
TTL 74ls74 CI 7473 7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 54H/74H73 54H/74H103 54H/74H76

ic 74ls78

Abstract: NATIONAL SEMICOND {LOGIC} D5E D | bSOllEE 0Dfc.37a4 3 I 78 54H/74H78 54LS/74LS78 DUAL JK FLIP-FLOP (With Common Clear and Clock and Separate Set Inputs) DESCRIPTIO N - The 'H78 is a dual JK master/slave flip -flo p w ith separate D irect Set Inputs, a com m on Direct Clear input and a com m on C lock Pulse Input. Inputs to the master section are controlled by the clock pulse. The clo ck pulse also regulates the c irc u itry w hich connects the master and slave sections. The sequence of
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OCR Scan
ic 74ls78 54/74LS 54/74H

74HC4052E

Abstract: 74HC194E CT253E, M CD74HC T257E,M CD74HCT258E.M CD74HC T259E.M C D 74HC T273E.M CERDIP CD 54H C 00F CD 54H C 02F CD 54H C 03F ·C D 5 4 H C 0 4 F CD 54H C 08F CD 54H C 10F CD 54H C 11F CD 54H C 14F CD 54H C 20F CD 54H C 21F CD 54H C 27F CD 54H C 30F CD 54H C 32F CD 54H C 42F CD 54H C 73F C D 54H C 74F C D 64H C 75F C D 54H C 85F C D 54H C 86F C D 54H C 93F CD 54H C 107F C 0 54H C 109F CD 54H C 112F CD 54H C 123F CD 54H C 125F CD54H C 126F C D 54H C 132F C D 54H C 137F C D 54H C 138F CD54H C 139F C D 54H C 147F C
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OCR Scan
74HC4052E 74HC194E 74HC4046AE 74HC4067E 74HCT4511E 74HC4538E CD74HC221 CT00E CT02E CD74HCT03E 74HCT04E CT10E

7450 ttl

Abstract: 74LS series logic gates 3 input or gate GND D26 54H/74H52 ra ra ra in Fa m rn rÌ W i rrf1 Lil làl Iii Lil Iii Iii IzJ GND D27 9005, 54/7450, 54H/74H50 Vcc na nana m ra rn m Iii (AI lil Iii lil lil Lü GND D28 54/7451*, 54H/74H51*, 54S/74S51*, 54LS/74LS51 Vcc ra ra na m ra fi ra j liJ Ul Iii Iii Iii Iii Iii GND #Make no external connection to pins 11 & 12 D29 9008, 54/7453, 54H/74H53 Vcc ra ra ra na na min Iii Iii lil Lil liJ Iii 111 GND 9008, 54/7453, 54H/74H53 D30 54/7454, 54H/74H54 ra ra ra na ra fi
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OCR Scan
74S64 74S65 7450 ttl 74LS series logic gates 3 input or gate 74LS series logic gates 74LS51 74LS125 74LS126 54H/74H52 54H/74H50 54H/74H51 54H/74H53 54H/74H54 54LS/75LS54

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gate symbols FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 D34 54LS/74LS55 Vcc Vcc 0 1 D35 S4H/74H61 D36 9006, 54/7460, 54H/74H60 ra ra ra m y m Vcc ST Iii Iii Iii LiJ Iii lil Id QND -'I r i D37 54H/74H62 D39 96106 ra näi na nri pa rri ITI Vcc Lil , High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , '" 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H
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OCR Scan
74LS266 74LS series logic gate symbols 74ls gate symbols 74H55 74125 ic 74H62 TTL 74125 54H/74H55 54H/74H60 54H/74H62 54LS/74LS 54H/74H

ITT 7400

Abstract: 74h01 - 9004 - - 9009 - 9007 - - - 54LS/74LS04 54/7404 54LS/74LS05 54/7405 - - 54/7416 54/7406 54H/74H04 54H/74H05 - - - 54H/74H00 54H/74H01 - - - - - - 54H/74H10 - 54H/74H20 - 54H/74H22 54H/74H40 - - 54H/74H30 - - 54S/74S04 9S04A 54S/74S05 9S05A - - - 54S/74S00 54S/74S03 - - - - - , /CONNECTION DIAGRAMS D IG IT A L -T T L D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S0SA, 54/7405, 54H/74H05, 54S/74S05, 54LS/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54
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OCR Scan
74LS38 74LS132 ITT 7400 74h01 74H04 TTL 7414 fairchild 7404 OC/48 54H/74H04 54H/74H05 54H/74H00 54H/74H01 54H/74H10

IC 7404 7406

Abstract: 74LS00 7400 74S00 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
IC 7404 7406 74LS00 7400 74S00 IC TTL 74LS00 ic 7404 74LS04 Hex Inverter Gates ic 74132 54LS/74LS03 54LS/74LS26 54LS/74LS37 54S/74S132 54H/74H20 54S/74S20

TTL 74126

Abstract: 74ls gate symbols Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , 4-2 Input â'" â'" â'" â'" 9S42 D25 4L,6B,9B 3 2-2-2-3 Input (Exp) â'" â'" - 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H/74H50 â'" D27 3I,6A,9A 5 Dual 2-2 Input â'" 54LS/74LS51 54/7451 54H/74H51 54S/74S51 D28 3I,6A,9A 6 2-2-2-3 Input (Exp) 9008 â'" 54/7453 54H/74H53 â'" D29 3I,6A,9A 7 2-2-2-3 Input â'" â'" 54/7454 54H/74H54 â'" D30 3I,6A,9A
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OCR Scan
TTL 74126 Fairchild logic/connection diagrams ttl 74LS55 74LS367 74126 high speed 9006 54LS/74LS54 54H/74H61 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gates Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , 4-2 Input â'" â'" â'" â'" 9S42 D25 4L,6B,9B 3 2-2-2-3 Input (Exp) â'" â'" â'" 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H/74H50 â'" D27 3I,6A,9A 5 Dual 2-2 Input â'" 54LS/74LS51 54/7451 54H/74H51 54S/74S51 D28 3I,6A,9A 6 2-2-2-3 Input (Exp) 9008 â'" 54/7453 54H/74H53 â'" D29 3I,6A,9A 7 2-2-2-3 Input â'" â'" 54/7454 54H/74H54 â'" D30 3I,6A,9A
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OCR Scan
r025 74H52 ic 74125 ic 74126 74H60 9S42 54LS/74LS367 54LS/74LS368

IC TTL 7432

Abstract: 74LS86 gate diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 , llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR , Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI , Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , 4-2 Input â'" â'" â'" â'" 9S42 D25 4L,6B,9B 3 2-2-2-3 Input (Exp) â'" â'" â'" 54H/74H52 â'" D26 3I,6A
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OCR Scan
IC TTL 7432 74LS86 gate diagram 7411 3 INPUT AND gate IC 7432 7411 pin diagram IC 7486 54H/74H08 54S/74S09 54LS/74LS09 54H/74H21 54S/74S32 54LS/74LS32

ALU IC 74181

Abstract: IC 74181 alu 93H183 54H/74H183 Dual 1-Bit with Carry 2 12 250 D102 3I,6A,9A 4 Adder 54/7482 Full2-Bit with Carry 2 38 , Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , 4-2 Input â'" â'" â'" â'" 9S42 D25 4L,6B,9B 3 2-2-2-3 Input (Exp) â'" â'" â'" 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H/74H50 â'" D27 3I,6A,9A 5 Dual 2-2 Input â'" 54LS/74LS51 54/7451 54H/74H51 54S/74S51 D28 3I,6A,9A 6 2-2-2-3 Input (Exp
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OCR Scan
ALU IC 74181 IC 74181 alu ic 74LS83 74181 alu IC 74181 ic 7485 54H/74H183 54/7483A S/74LS83 54LS/74LS283 93L41 74LS181

74ls04 hex inverter gates

Abstract: trigger 74114 Inverters 9016 54LS/74LS04 54/7404 54H/74H04 54S/74S04 9S04A D1 3I,6A,9A 2 Hex Inverts (OC) 9017 54LS/74LS05 54/7405 54H/74H05 54S/74S05 9S05A D1 3I,6A,9A 3 Hex Inverter (15 V) â'" â'" 54/7416 â'" â'" D1 3I , 54/74114 â'" â'" D1 3I,6A,9A 6 Quad 2-lnput 9002 54LS/74LS00 54/7400 54H/74H00 54S/74S00 D2 3I,6A,9A 7 Quad 2-lnput (OC) 9012 54LS/74LS03 54/7403 54H/74H01 54S/74S03 D2 3I,6A,9A 8 Quad 2-lnput (OC) â , -lnput Schmitt 74LS132 54/74132 â'" 54S/74S132 D2 3I,6A,9A 14 Triple 3-lnput 9003 54LS/74LS10 54/7410 54H/74H10
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OCR Scan
trigger 74114 74l804 7404 74L814 74114 TTL 74h04 54LS/74LS20 74S20 S/74LS13 S/74LS22 54H/74H22 74S22

TTL 7410

Abstract: TTL 7401 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
TTL 7410 TTL 7401 TTL 7420 74LS00 TTL TTL 7404 fairchild 9016 TTL 74LS04 54LS/74LS22 54H/74H40 54S/74S40 54LS/74LS40 54S/74S140 74S140

ALU IC 74181

Abstract: 74181 ic pin diagram FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D16 547408, 54H/74H08, 54S/74S08, 54LS/74LS08 , llJ OND D19 54/7421, 54H/74H21 54LS/74LS21 Vcc NC s J â'" D17 9S41 Vcc RRPIIiRRRR , Lü D18 54/7411, 54H/74H11, 54S/74S11, 54LS/74LS11, 54S/74S15, 54LS/74LS15 Vcc El El El [il El FI , 93H183 54H/74H183 Dual 1-Bit with Carry 2 12 250 D102 3I,6A,9A 4 Adder 54/7482 Full2-Bit with Carry 2 38 , Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW
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OCR Scan
74181 ic pin diagram DS 7409 7480 full adder 1 bit 74LS86 full adder TTL 74ls83 pin diagram of 7411 54H/74H11 54S/74S86 54LS/74LS86 54LS/74LS136 54S/74S135 54LS/74LS379

7404 TTL CMOS

Abstract: TTL 74h04 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
7404 TTL CMOS TTL 7400 fairchild 7404 ttl inverter CI 74LS00 TTL 7404 fairchild 74H00 TTL A1488 A1489 S/74LS40 S/74LS30 54H/74H30 54S/74S30

74LS00 7400 74S00

Abstract: 74LS04 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
74LS04 74LS04 NOT gate 74LS00 74LSoo 74H00 TTL 7404

trigger 74114

Abstract: 74114 0) O) IS u NAND Gates 1 Hex Inverters 9016 54LS/74LS04 54/7404 54H/74H04 54S/74S04 9S04A D1 3I,6A,9A 2 Hex Inverts (OC) 9017 54LS/74LS05 54/7405 54H/74H05 54S/74S05 9S05A D1 3I,6A,9A 3 Hex Inverter , /7400 54H/74H00 54S/74S00 D2 3I,6A,9A 7 Quad 2-lnput (OC) 9012 54LS/74LS03 54/7403 54H/74H01 54S/74S03 , 3-lnput 9003 54LS/74LS10 54/7410 54H/74H10 54S/74S10 D4 3I,6A,9A 15 Triple 3-lnput (OC) â'" â'" 54/7412 â'" â'" D4 3I,6A,9A 16 Dual 4-lnput 9004 54LS/74LS20 54/7420 54H/74H20 74S20 D5 3I,6A,9A 17 Dual
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OCR Scan
74LS13 IC 7413 schmitt trigger 7413 rs 7410 7438 IC 7422 54LS/74LS13 54LS/74LS260 54LS/74LS133 54S/74S133 54S/74S134
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