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54H/74H74

Catalog Datasheet MFG & Type PDF Document Tags

TTL 74ls74

Abstract: 74ls74 "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , 65 D54 3I, 6A, 9A 9 Dual D 54/7474 D s X X 25 20 85 D61 3I, 6A, 9A 10 Dual D 54H/74H74 D s X X 43 , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54/7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
TTL 74ls74 74ls74 CI 7473 7476 JK TTL 7474 ttl 7474 14 PIN 54S/74S109 54LS/74LS109 54H/74H74 54H/74H73 54H/74H103 54H/74H76

TTL 74ls74

Abstract: 7474 14 PIN "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54/7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
7474 14 PIN 74ls76 7476 ttl ttl 74ls109 74LS107 74LS73

7472 PIN DIAGRAM

Abstract: 74574 a. H o D52a 54H/74H71 D52b 54H/74H101 1 2 3 â'¢ 4 13 9-10 11 -12- SD J O CP K Q So J O â'" 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 1ÌE0 J S° o â'" 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED , , J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H/74H71 (AOI) (2+2) J, (2+2) K X _ 30 22 95 D52a 3I, 6A, 9A 4 Single JK 54H/74H101 (AOI) (2+2)J, (2+2)K "U X _ 50 16 100 D52b 31, 6A, 9A 5 Single
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OCR Scan
7472 PIN DIAGRAM 74574 74LS112 TTL 7472 7473 dual JK 7472 ttl 54H/74H71 54H/74H101 54H/74H72 54H/74H102 74H71 54S/74S113

CI 7474

Abstract: CI 7473 "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54/7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
CI 7474 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 54S/74S114 54LS/74LS 54LS/74LS78 93L14 54LS/74LS279 54LS/74LS196

74ls74 pin configuration

Abstract: 7474 D flip-flop 54/7474 54H/74H74 54S/74S74 54LS/74LS74 LOGIC SYMBOL DESCRIPTION The "74" is a Dual Positive , (a) PINS 54/74 54H/74H 54S/74S 54LS/74LS D°ata Input i'i'^a! 40 -1.6 50 -2.0 50 -2.0 20 -0.36 CP , CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (b) PARAMETER TEST CONDITIONS 54/74 54H/74H 54S/74S 54LS , °C (See Section 4 for Waveforms and Conditions.) PARAMETER TEST CONDITIONS 54/74 54H/74H 54S/74S 54LS , REQUIREMENTS: TA =25°C (See Section 4 for Waveforms and Conditions.) PARAMETER TEST CONDITIONS 54/74 54H
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OCR Scan
N7474N N74H74N N74S74N N74LS74N N7474F N74H74F 74ls74 pin configuration 7474 D flip-flop S5474F 7474 D flip flop

logic ic 7476 pin diagram

Abstract: logic ic 74LS76 pin diagram D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 -5 CP , Q 0 -6 Co ~ L T O < z o z -o , 54/7473, 54H/74H73, 54LS/74LS73 *54/74107, ` 54LS/74LS107 14 - J 1 - 0 CP 3- K Q -1 2 2- J 5 -0 CP 0 0-13 ^ Cd Q z 5 o > p < o UJ O Vcc = Pm 4 GND = Pin 11 D57b 54H/74H103 12 7_ C , 0 -8 UJ z D58 54/7476, 54H/74H76, 54LS/74LS76 3- K , Q Cd Cd C O UJ 2 J l
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OCR Scan
logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74109 dual JK 74LS109 IC 74196 54LS/74LS77 54LS/74LS75 54LS/74LS197

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram 25 20 85 D61 3I, 6A, 9A 10 Dual D 54H/74H74 D s X X 43 13 150 D61 3I, 6A, 9A 11 Dual D 54S/74S74 D , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 ¿ 10 i , < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H , Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q , 16 100 D50 3I, 6A 2 Single JK 9001 2J, 2K, J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H
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OCR Scan
74ls112 pin diagram TTL 74107 7473 pin diagram 7476 Jk 7476 74h106 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54LS/74LS113

74LS74 truth table

Abstract: 7474PC NATIONAL SENICOND -CLOGIO D2E D | LSDllES D0b371S 2 | T-46-07-09 74 CO NNECTIO N DIAGRAM S PINO UT A 54/7474 54H/74H74 54S/74S74 54LS/74LS74 DUAL D-TYPE POSITIVE EDGETRIG GERED FLIP-FLOP DESCRIPTION - The '74 devices are dual D-type flip -flo p s w ith Direct Clear and Set inputs and com plem entary (Q, Q) outputs. Inform ation at the input is transferred to the outputs on the positive edge of the clock pulse. Clock trig gering occurs at a voltage level o f the clock pulse and is not d ire c
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OCR Scan
74LS74 truth table 7474PC 74LS74PC DE flip-flop 7474 pin IC 7474 logic diagram of ic 7474 5474DM 54S74DM 54LS74DM 54S74FM 54/74H 54/74S

F7474PC

Abstract: 74ls74d 74 C O N N E C T IO N DIAGRAM S P IN O U T A 54/7474 < ? / / 6 ' \/54H/74H74 © t f e. j w w^4S/74S74 £> /, o 'b, U 34LS/74LS74 ^ ^ < - 3 ^ - "Si / / DUAL D-TYPE POSITIVE ED G e"TRIGGERED FLIP-FLOP DESCRIPTIO N - The '74 devices are dual D-type flip-flops with Direct C le a r and Set inputs and com plem entary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clo ck pulse. C lo ck trig gering occu rs at a voltage level of the clo ck pulse and
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OCR Scan
F7474PC 74ls74d 7474 pin out diagram ic 7474 pin diagram 74H74D IC 74LS74 54/74LS

54H00

Abstract: 74H00 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , Pin 7 MCC3054/74H 71 /MCC3154/54H 71 OR Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS (3) SET 5
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OCR Scan
54H00 74H00 MC1741C MC1741CP1 MCC1741C MCC3000 MIL-STD-883 MCC3031 MCC3131/54H52 MCC3032/74H53 MCC3132/54H53

MCC3063

Abstract: MCC3052 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , /74H 20/MCC3110/54H 20 Dual 4-lnput NAND Gate 39 x 42 (1GH) PIN CONNECTIONS 1 -2- 4- 5-9
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OCR Scan
MCC3052 MCC3011 MCC3010 74HOO MCC3029 MCC3129 MCC3030 MCC3130 MCC3033/74H54

MCC3155

Abstract: 54H00 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , /74H 72/MCC3155/54H 72 ANO Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS tpd = 10 ns typ f = 30
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OCR Scan
MCC3160 MCC3155 MCC3023 master slave jk flip flop MCC3028 MCC3128 MCC3133/54H54 MCC3034/74H55 MCC3134/54H55

74H74

Abstract: MCC3052 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , Pin 7 MCC3054/74H 71 /MCC3154/54H 71 OR Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS (3) SET 5
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OCR Scan
transistor k49 MCC74H11 MCC54H11 MCC74H20 MCC54H20 MCC74H20F MCC54H20F

MCC3155

Abstract: 54h00 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , /74H 72/MCC3155/54H 72 ANO Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS tpd = 10 ns typ f = 30
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OCR Scan
AOI gate d flip flop MCC3152 MCC3055 MCC74H21 MCC54H21 MCC74H22 MCC54H22 MCC74H22F MCC54H22F

74H00

Abstract: 54H00 MCC3063 MCC3163 Dual J-K Flip-Flop 60N 59x65 MCC3064/74H74 MCC31 64/54H74 Dual D Flip-Flop 80V 65x62 , /74H 20/MCC3110/54H 20 Dual 4-lnput NAND Gate 39 x 42 (1GH) PIN CONNECTIONS 1 -2- 4- 5-9
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OCR Scan
74H55 MCC74H30 MCC54H30 MCC74H40 MCC54H40 MCC74H40F MCC54H40F

IC 7402, 7404, 7408, 7432, 7400

Abstract: CI 74122 54H ELECTRICAL CHARACTERISTICS V|L(V) LOW LEVEL (See Notes - Page 50) OUTPUT VOLTAGE V|C (V) CLAMP , o X o X o X o h- < 0 X 5 o 54H ELECTRICAL CHARACTERISTICS V|L(V) LOW , 2.4 2.4 -2 -2 -2 -2 J1,J2,J3,K1,K2, K3, CLOCK -2 PRESET, CUR -4 54/74H73 54/74H74 0.8 0.8 2 2 -1.5
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OCR Scan
54/74H101 IC 7402, 7404, 7408, 7432, 7400 CI 74122 7408, 7404, 7486, 7432 ci 7445 CI 7442a lm 7486 54/74H106 54/74H108 54/74H102

74HC4052E

Abstract: 74HC194E CT253E, M CD74HC T257E,M CD74HCT258E.M CD74HC T259E.M C D 74HC T273E.M CERDIP CD 54H C 00F CD 54H C 02F CD 54H C 03F ·C D 5 4 H C 0 4 F CD 54H C 08F CD 54H C 10F CD 54H C 11F CD 54H C 14F CD 54H C 20F CD 54H C 21F CD 54H C 27F CD 54H C 30F CD 54H C 32F CD 54H C 42F CD 54H C 73F C D 54H C 74F C D 64H C 75F C D 54H C 85F C D 54H C 86F C D 54H C 93F CD 54H C 107F C 0 54H C 109F CD 54H C 112F CD 54H C 123F CD 54H C 125F CD54H C 126F C D 54H C 132F C D 54H C 137F C D 54H C 138F CD54H C 139F C D 54H C 147F C
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OCR Scan
74HC4052E 74HC194E 74HC4046AE 74HC4067E 74HCT4511E 74HC4538E CD74HC221 CT00E CT02E CD74HCT03E 74HCT04E CT10E

7450 ttl

Abstract: 74LS series logic gates 3 input or gate GND D26 54H/74H52 ra ra ra in Fa m rn rÌ W i rrf1 Lil làl Iii Lil Iii Iii IzJ GND D27 9005, 54/7450, 54H/74H50 Vcc na nana m ra rn m Iii (AI lil Iii lil lil Lü GND D28 54/7451*, 54H/74H51*, 54S/74S51*, 54LS/74LS51 Vcc ra ra na m ra fi ra j liJ Ul Iii Iii Iii Iii Iii GND #Make no external connection to pins 11 & 12 D29 9008, 54/7453, 54H/74H53 Vcc ra ra ra na na min Iii Iii lil Lil liJ Iii 111 GND 9008, 54/7453, 54H/74H53 D30 54/7454, 54H/74H54 ra ra ra na ra fi
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OCR Scan
74S64 74S65 7450 ttl 74LS series logic gates 3 input or gate 74LS series logic gates 74LS51 74LS125 74LS126 54H/74H52 54H/74H50 54H/74H51 54H/74H53 54H/74H54 54LS/75LS54

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gate symbols FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 D34 54LS/74LS55 Vcc Vcc 0 1 D35 S4H/74H61 D36 9006, 54/7460, 54H/74H60 ra ra ra m y m Vcc ST Iii Iii Iii LiJ Iii lil Id QND -'I r i D37 54H/74H62 D39 96106 ra näi na nri pa rri ITI Vcc Lil , High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , '" 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H
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OCR Scan
74LS266 74LS series logic gate symbols 74ls gate symbols 74125 ic 74H62 TTL 74125 buffer 74ls series logic gates 54H/74H55 54H/74H60 54H/74H62 54H/74H 54LS/74LS54

IC 7404 7406

Abstract: 74LS00 7400 74S00 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
74LS132 IC 7404 7406 74LS00 7400 74S00 IC TTL 74LS00 ic 7404 74LS04 Hex Inverter Gates ic 74132 54H/74H04 54H/74H05 54H/74H00 54H/74H01 54LS/74LS03 54LS/74LS26
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