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54H/74H72

Catalog Datasheet MFG & Type PDF Document Tags

7472 PIN DIAGRAM

Abstract: 74574 a. H o D52a 54H/74H71 D52b 54H/74H101 1 2 3 â'¢ 4 13 9-10 11 -12- SD J O CP K Q So J O â'" 6 CP K O 0-8 Vcc = Pin 14 GND = Pin 7 D53a 54/7472 54H/74H72 13 Vcc = Pin 14 GND = Pin 7 D53b 54H/74H102 1ÌE0 J S° o â'" 8 CP KC0 0 0-6 T 2 Vcc = Pin 14 GND = Pin 7 ÌED , JK 54/7472 3J, 3K X X 20 25 50 D53a 3I, 6A, 9A 6 Single JK 54H/74H72 3J, 3K X X 30 22 80 D53a 3I , , J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H/74H71 (AOI) (2+2) J, (2+2) K X _ 30 22 95
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OCR Scan
7472 PIN DIAGRAM 74574 74LS112 74LS74 TTL 7472 7473 dual JK 54H/74H71 54H/74H101 54H/74H72 54H/74H102 74H71 54H/74H74

7472 ci

Abstract: 7472 Flip-Flop 54/7472 54H/74H72 LOGIC SYMBOL DESCRIPTION The "72" is a positive pulse triggered master , Fig B S5472W â'¢ S54H72W INPUT AND OUTPUT LOADING AND FAN-OUT TABLE , TEST CONDITIONS 54/74 54H/74H 54S/74S 54LS/74LS UNIT Min Max Min Max Min Max Min Max Ice , , see inside front cover for 54/74 and 54H/74H and see inside back cover for 54S/74S and 54LS/74LS , . AC CHARACTERISTICS TA = 25°C (See Section 4 for Waveforms and Conditions) 54/74 54H/74H 54S
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OCR Scan
N7472N N74H72N N7472F N74H72F S5472F S54H72F 7472 ci 7472 Flip-Flop 7472 truth table j-k master slave flip flop 7472

TTL 74ls74

Abstract: 74ls74 , 3K X X 20 25 50 D53a 3I, 6A, 9A 6 Single JK 54H/74H72 3J, 3K X X 30 22 80 D53a 3I, 6A, 9A 7 , "O 11 J_ 15 Vcc = Pin 16 GND = Pin 8 D61 54/7474, 54H/74H74, 54S/74S74, 54LS/74LS74 4 10 J , o 3 a i-3 o D57a 54/7473, 54H/74H73, 54LS/74LS73 â'¢54/74107, *54LS/74LS107 14 â'" J 0 -12 I- J 0 1 -0 CP 5-0 CP 3 â'" Kc, 0 0-13 12 KC0 0 Vcc = Pin 4 GND = Pin 11 D57b 54H/74H103 D58 54/7476, 54H/74H76, 54LS/74LS76 2 7 14 â'" J 0 "Vcc = Pin 14 1-0 CP GND = Pin 7 3 â'" K Q Pins are
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OCR Scan
TTL 74ls74 CI 7473 7476 JK TTL 7474 ttl 7474 14 PIN Jk 7476 54S/74S109 54LS/74LS109 54H/74H73 54H/74H103 54H/74H76 54S/74S113

7472 PIN DIAGRAM

Abstract: 74ls112 pin diagram JK 54H/74H72 3J, 3K X X 30 22 80 D53a 3I, 6A, 9A 7 Single JK 54H/74H102 3J, 3K T X X 50 16 100 D53b , FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 ¿ 10 i , < O Ul z o (A Ul (9 z < X o I-3 a H 3 O Vcc = Pin 14 GND = Pin 7 EDGE-TRIGGERED D58 54H , Pin 13 oâ'"10 Vcc = Pin 16 GND = Pin 8 D59b 54H/74H108 10 0 â'" 2 11 J So 0 CP CP K Co Q , 16 100 D50 3I, 6A 2 Single JK 9001 2J, 2K, J, K, JK "t_r X X 50 16 115 D51 3I, 6A 3 Single JK 54H
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OCR Scan
74ls112 pin diagram TTL 74107 7473 pin diagram 7476 74h106 74LS113 54H/74H78 54H/74H106 54S/74S112 54LS/74LS112 54H/74H108 54LS/74LS113

7472 Flip-Flop

Abstract: pin diagram of 7472 72 54/7472 b/z^ol ^54H/74H72 Oi/T/O JK MASTER/SLAVE FLIP-FLOP (With AND Inputs) DESCRIPTION â'"The '72 is a high speed JK master/slave flip-flop with AND gate inputs. The AND gate inputs for entry into the master section are controlied by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from AND gate inputs to master; 3) disable AND gate inputs; 4
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OCR Scan
7472PC 74H72PC 7472DC 74H72DC 7472FC 74H72FC pin diagram of 7472 5472DM 5472FM 54H72DM 54H72FM

ic 7472 pin diagram

Abstract: 7472 Flip-Flop NA TIO NAL SEDICOND -CLOGIO OSE D | bSD1152 DGti371G 3 | j 2 T~V^07~0r CO NN ECTIO N DIAGRAMS PINO UT A 54/7472 54H/74H72 JK M A S T E R /S L A V E FLIP-FLOP (W ith A N D Inputs) DESCRIPTION - The '72 is a high speed JK master/slave flip -flo p with AND gate inputs. The AND gate inputs fo r entry in to the master section are con tro lled by the clo ck pulse. The clock pulse also regulates the circ u itry w h ich connects the master and slave sections. The sequence of operation is as
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OCR Scan
ic 7472 pin diagram SD1152 54/74H

7472PC

Abstract: 47-25l 72 C O N N E C T IO N D IA G R A M S PINOUT A 54/7472 £>//
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OCR Scan
47-25l

74H74

Abstract: MCC3052 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , Pin 7 MCC3054/74H 71 /MCC3154/54H 71 OR Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS (3) SET 5
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OCR Scan
74H74 MCC3052 transistor k49 54H00 74H00 MC1741C MIL-STD-883 MCC74H11 MCC54H11 MCC74H20 MCC54H20 MCC74H20F

54H00

Abstract: 74H00 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , Pin 7 MCC3054/74H 71 /MCC3154/54H 71 OR Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS (3) SET 5
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OCR Scan
MC1741CP1 MCC1741C MCC3000 6384d MCC3031 MCC3131/54H52 MCC3032/74H53 MCC3132/54H53 MCC3033/74H54

MCC3063

Abstract: MCC3052 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , /74H 20/MCC3110/54H 20 Dual 4-lnput NAND Gate 39 x 42 (1GH) PIN CONNECTIONS 1 -2- 4- 5-9
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OCR Scan
MCC3063 MCC3011 MCC3010 74HOO MCC3029 MCC3129 MCC3030 MCC3130 MCC3133/54H54

MCC3155

Abstract: 54H00 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , /74H 72/MCC3155/54H 72 ANO Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS tpd = 10 ns typ f = 30
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OCR Scan
MCC3155 MCC3023 master slave jk flip flop MCC3028 MCC3128 MCC3034/74H55 MCC3134/54H55 MCC3050

MCC3155

Abstract: 54h00 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , /74H 72/MCC3155/54H 72 ANO Input J-K Flip Flop 63x63 (43H) PIN CONNECTIONS tpd = 10 ns typ f = 30
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OCR Scan
AOI gate d flip flop MCC3152 MCC3055 MCC54H20F MCC74H21 MCC54H21 MCC74H22 MCC54H22 MCC74H22F

74H00

Abstract: 54H00 MCC3055/74H72 MCC3155/54H72 AND Input J-K Flip-Flop 43 H 63x63 MCC3060 MCC3160 Dual Type D Flip-Flop 80V , /74H 20/MCC3110/54H 20 Dual 4-lnput NAND Gate 39 x 42 (1GH) PIN CONNECTIONS 1 -2- 4- 5-9
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OCR Scan
74H55 MCC54H22F MCC74H30 MCC54H30 MCC74H40 MCC54H40 MCC74H40F

IC 7402, 7404, 7408, 7432, 7400

Abstract: CI 74122 54H ELECTRICAL CHARACTERISTICS V|L(V) LOW LEVEL (See Notes - Page 50) OUTPUT VOLTAGE V|C (V) CLAMP , o X o X o X o h- < 0 X 5 o 54H ELECTRICAL CHARACTERISTICS V|L(V) LOW , 54/74H61 54/74H62 54/74H71 54/74H72 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 -1.5 -1.5 -1.5 -1.5 -1.5 0.4 0.4
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OCR Scan
54/74H101 IC 7402, 7404, 7408, 7432, 7400 CI 74122 7408, 7404, 7486, 7432 ci 7445 CI 7442a lm 7486 54/74H106 54/74H108 54/74H102

74HC4052E

Abstract: 74HC194E CT253E, M CD74HC T257E,M CD74HCT258E.M CD74HC T259E.M C D 74HC T273E.M CERDIP CD 54H C 00F CD 54H C 02F CD 54H C 03F ·C D 5 4 H C 0 4 F CD 54H C 08F CD 54H C 10F CD 54H C 11F CD 54H C 14F CD 54H C 20F CD 54H C 21F CD 54H C 27F CD 54H C 30F CD 54H C 32F CD 54H C 42F CD 54H C 73F C D 54H C 74F C D 64H C 75F C D 54H C 85F C D 54H C 86F C D 54H C 93F CD 54H C 107F C 0 54H C 109F CD 54H C 112F CD 54H C 123F CD 54H C 125F CD54H C 126F C D 54H C 132F C D 54H C 137F C D 54H C 138F CD54H C 139F C D 54H C 147F C
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OCR Scan
74HC4052E 74HC194E 74HC4046AE 74HC4067E 74HCT4511E 74HC4538E CD74HC221 CT00E CT02E CD74HCT03E 74HCT04E CT10E

7450 ttl

Abstract: 74LS series logic gates 3 input or gate GND D26 54H/74H52 ra ra ra in Fa m rn rÌ W i rrf1 Lil làl Iii Lil Iii Iii IzJ GND D27 9005, 54/7450, 54H/74H50 Vcc na nana m ra rn m Iii (AI lil Iii lil lil Lü GND D28 54/7451*, 54H/74H51*, 54S/74S51*, 54LS/74LS51 Vcc ra ra na m ra fi ra j liJ Ul Iii Iii Iii Iii Iii GND #Make no external connection to pins 11 & 12 D29 9008, 54/7453, 54H/74H53 Vcc ra ra ra na na min Iii Iii lil Lil liJ Iii 111 GND 9008, 54/7453, 54H/74H53 D30 54/7454, 54H/74H54 ra ra ra na ra fi
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OCR Scan
74S64 74S65 7450 ttl 74LS series logic gates 3 input or gate 74LS series logic gates 74LS51 74LS125 74LS126 54H/74H52 54H/74H50 54H/74H51 54H/74H53 54H/74H54 54LS/75LS54

74LS series logic gates 3 input or gate

Abstract: 74LS series logic gate symbols FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D33 54H/74H55 D34 54LS/74LS55 Vcc Vcc 0 1 D35 S4H/74H61 D36 9006, 54/7460, 54H/74H60 ra ra ra m y m Vcc ST Iii Iii Iii LiJ Iii lil Id QND -'I r i D37 54H/74H62 D39 96106 ra näi na nri pa rri ITI Vcc Lil , High Speed 54H/74H 6 ns/22 mW High Speed Schottky 54S/74S 3 ns/19 mW Logic/Connection Diagram(2) 5 , '" 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H
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OCR Scan
74LS266 74LS series logic gate symbols 74ls gate symbols 74125 ic 74H62 TTL 74125 buffer 74ls series logic gates 54H/74H55 54H/74H60 54H/74H62 54H/74H 54LS/74LS54

IC 7404 7406

Abstract: 74LS00 7400 74S00 FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012, 54H/74H01, 54/7403, 54S/74S03, 54LS , iii Là QND LJ Id Lil W à LJ GND U HI [21 LU liJ lil LJ QND D4 9003, 54/7410, 54H/74H10, 54S/74S10, 54LS/74LS10, 54/7412 Vcc L_l Lil lil LiJ LiJ LiJ Lü QND D5 9004, 54/7420, 54H/74H20, 54S
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OCR Scan
74LS132 IC 7404 7406 74LS00 7400 74S00 IC TTL 74LS00 ic 7404 74LS04 Hex Inverter Gates ic 74132 54H/74H04 54H/74H05 54H/74H00 54H/74H01 54LS/74LS03 54LS/74LS26

ITT 7400

Abstract: 74h01 - 9004 - - 9009 - 9007 - - - 54LS/74LS04 54/7404 54LS/74LS05 54/7405 - - 54/7416 54/7406 54H/74H04 54H/74H05 - - - 54H/74H00 54H/74H01 - - - - - - 54H/74H10 - 54H/74H20 - 54H/74H22 54H/74H40 - - 54H/74H30 - - 54S/74S04 9S04A 54S/74S05 9S05A - - - 54S/74S00 54S/74S03 - - - - - , /CONNECTION DIAGRAMS D IG IT A L -T T L D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S0SA, 54/7405, 54H/74H05, 54S/74S05, 54LS/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54
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OCR Scan
74LS38 ITT 7400 74h01 74H04 TTL 7414 fairchild 7404 74LS40 OC/48 54H/74H10 54H/74H20 54H/74H22 54H/74H40 54H/74H30

TTL 74126

Abstract: 74ls gate symbols Low Power Schottky 54LS/74LS 5 ns/2 mW Std. TTL 9N 54/74 10 ns/10 mW High Speed 54H/74H 6 ns/22 mW , 4-2 Input â'" â'" â'" â'" 9S42 D25 4L,6B,9B 3 2-2-2-3 Input (Exp) â'" â'" - 54H/74H52 â'" D26 3I,6A,9A AND-OR-INVERT Gates 4 Dual 2-2 Input (Exp) 9005 â'" 54/7450 54H/74H50 â'" D27 3I,6A,9A 5 Dual 2-2 Input â'" 54LS/74LS51 54/7451 54H/74H51 54S/74S51 D28 3I,6A,9A 6 2-2-2-3 Input (Exp) 9008 â'" 54/7453 54H/74H53 â'" D29 3I,6A,9A 7 2-2-2-3 Input â'" â'" 54/7454 54H/74H54 â'" D30 3I,6A,9A
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OCR Scan
TTL 74126 Fairchild logic/connection diagrams ttl 74LS55 74LS367 74126 high speed 9006 54H/74H61 54LS/74LS125 54LS/74LS126 54LS/74LS365 54LS/74LS366 54LS/74LS367
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