ACT373 AC373 74AC373PC 74AC373SC 74AC373SJ 74ACT373PC 74ACT373SC 74ACT373SJ - Datasheet Archive

 

Features The 'AC/'ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops

 

General Description Features The 'AC/'ACT373 ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. n n n n n n Ordering Code: ICC and IOZ reduced by 50% Eight latches in a single package TRI-STATE outputs for bus interfacing Outputs source/sink 24 mA 'ACT373 ACT373 has TTL-compatible inputs Standard Military Drawing (SMD) - 'AC373 AC373: 5962-87555 - 'ACT373 ACT373: 5962-87556 See Section 0 Commercial Military Package Package Description Number 74AC373PC 74AC373PC N20A 74AC373SC 74AC373SC (Note 1) M20B 20-Lead Molded Dual-In-Line (0.300" Wide) 20-Lead Molded Small Outline (0.300" Wide), JEDEC 74AC373SJ 74AC373SJ (Note 1) M20D 20-Lead Molded Small Outline, EIAJ 74ACT373PC 74ACT373PC N20A 20-Lead Molded Dual-In-Line (0.300" Wide) 74ACT373SC 74ACT373SC (Note 1) M20B 20-Lead Molded Small Outline (0.300" Wide), JEDEC 74ACT373SJ 74ACT373SJ (Note 1) M20D 20-Lead Molded Small Outline, EIAJ 74ACT373MTC 74ACT373MTC (Note 1) MTC20 MTC20 20-Lead Molded Thin Shrink Small Outline Package, JEDEC 74ACT373MSA 74ACT373MSA (Note 1) MSA20 MSA20 20-Lead Molded Small Shrink Outline Package, (EIAJ SSOP) 54AC373DM 54AC373DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line 54AC373FM 54AC373FM (Note 2) W20A 20-Lead Cerpak 54AC373LM 54AC373LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 54ACT373DM 54ACT373DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line 54ACT373FM 54ACT373FM (Note 2) W20A 20-Lead Cerpak 54ACT373LM 54ACT373LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13" Tape and Reel. Use suffix SCX, SJX, and MTCX. Note 2: Military grade device with environmental and burn-in processing, use suffix DMQB, FMQB and LMQB. 54AC/74AC373 54AC/74AC373 · 54ACT/74ACT373 54ACT/74ACT373 54AC/74AC373 54AC/74AC373 · 54ACT/74ACT373 54ACT/74ACT373 Octal Transparent Latch with TRI-STATE ® Outputs 54AC/74AC373 54AC/74AC373 · 54ACT/74ACT373 54ACT/74ACT373 Octal Transparent Latch with TRI-STATE Outputs April 1997 DSXXX TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACTTM is a trademark of National Semiconductor Corporation. © 1997 National Semiconductor Corporation www.national.com DS009958 DS009958 PrintDate=1997/04/24 PrintTime=10:20:09 5738 ds009958 Rev. No. 1 Proof 1 1 Logic Symbols IEEE/IEC DS009958-1 DS009958-1 DS009958-2 DS009958-2 Pin Names Description D0­D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0­O7 TRI-STATE Latch Outputs Connection Diagrams Pin Assignment for DIP, Flatpak, SSOP, SOIC and TSSOP Pin Assignment for LCC DS009958-4 DS009958-4 DS009958-3 DS009958-3 Functional Description Truth Table The 'AC/'ACT373 ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. www.national.com PrintDate=1997/04/24 PrintTime=10:20:10 5738 ds009958 Rev. No. 1 Inputs Outputs LE OE Dn On X H X Z H L L L H L H H L L X O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable 2 Proof 2 Logic Diagram DS009958-5 DS009958-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 PrintDate=1997/04/24 PrintTime=10:20:10 5738 ds009958 Rev. No. 1 www.national.com Proof 3 Absolute Maximum Ratings Recommended Operating Conditions (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP PDIP Supply Voltage (VCC) 'AC 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 74AC/ACT 74AC/ACT 54AC/ACT 54AC/ACT Minimum Input Edge Rate (V/t) 'AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) 'ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V ± 50 mA ± 50 mA -65°C to +150°C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40°C to +85°C -55°C to +125°C 125 mV/ns 125 mV/ns Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACTTM circuits outside databook specifications. 175°C 140°C DC Characteristics for 'AC Family Devices Symbol Parameter VCC 74AC TA = +25°C 74AC TA = -55°C to +125°C (V) 54AC TA = -40°C to +85°C Typ VIH 3.0 1.5 2.1 2.1 2.25 3.15 3.15 3.15 5.5 2.75 3.85 3.85 3.85 Maximum Low 3.0 1.5 0.9 0.9 0.9 Level Input 4.5 2.25 1.35 1.35 1.35 Voltage 5.5 2.75 1.65 1.65 1.65 Minimum High 3.0 2.99 2.9 2.9 2.9 Level Output 4.5 4.49 4.4 4.4 4.4 Voltage 5.5 5.49 5.4 5.4 VOUT = 0.1V 2.1 4.5 Voltage VOH Conditions Guaranteed Limits Minimum High Level Input VIL Units 5.4 V or VCC - 0.1V V or VCC - 0.1V VOUT = 0.1V IOUT = -50 µA V (Note 4) VIN = VIL or VIH 3.0 2.56 2.4 2.46 4.5 3.86 3.7 3.76 5.5 4.86 4.7 4.76 Maximum Low 3.0 0.002 0.1 0.1 0.1 Level Output 4.5 0.001 0.1 0.1 0.1 Voltage VOL 5.5 0.001 0.1 0.1 -12 mA V IOH -24 mA -24 mA IOUT = 50 µA 0.1 V (Note 4) VIN = VIL or VIH 3.0 0.36 0.50 0.44 4.5 0.36 0.50 0.44 5.5 IIN Maximum Input 0.36 0.50 0.44 5.5 ± 0.1 ± 1.0 ± 1.0 12 mA V µA IOL 24 mA 24 mA VI = VCC, GND Leakage Current www.national.com PrintDate=1997/04/24 PrintTime=10:20:13 5738 ds009958 Rev. No. 1 4 Proof 4 DC Characteristics for 'AC Family Devices Symbol Parameter VCC 74AC TA = +25°C 54AC TA = 74AC TA = -55°C to +125°C (V) -40°C to +85°C Typ IOZ (Continued) Units Conditions Guaranteed Limits ± 5.0 ± 2.5 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 50 75 mA VOLD = 1.65V Max 5.5 -50 -75 mA VOHD = 3.85V Min 80.0 40.0 µA Maximum TRI-STATE ± 0.25 5.5 Current IOLD IOHD (Note 5) Minimum Dynamic Output Current ICC Maximum Quiescent 5.5 4.0 Supply Current VIN = VCC or GND Note 4: All outputs loaded, thresholds on input associated with output under test. Note 5: Maximum test duration 2.0 ms, one output loaded at a time. Note 6: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25°C is identical to 74AC @ 25°C. DC Characteristics for 'ACT Family Devices Symbol Parameter 74ACT 74ACT TA = +25°C VCC (V) 54ACT 54ACT TA = -55°C to +125°C Typ VIH 74ACT 74ACT TA = 4.5 1.5 2.0 2.0 2.0 5.5 1.5 2.0 2.0 V VOUT = 0.1V V or VCC - 0.1V VOUT = 0.1V V or VCC - 0.1V IOUT = -50 µA 2.0 Maximum Low Level 4.5 1.5 0.8 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 0.8 Minimum High Level 4.5 4.49 4.4 4.4 4.4 Output Voltage VOH Conditions Guaranteed Limits Minimum High Level Input Voltage VIL Units -40°C to +85°C 5.5 5.49 5.4 5.4 5.4 (Note 7) VIN = VIL or VIH 4.5 VOL 3.86 3.70 3.76 5.5 4.86 4.70 4.76 Maximum Low Level 4.5 0.001 0.1 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 V V IOH -24 mA -24 mA IOUT = 50 µA 0.1 (Note 7) VIN = VIL or VIH 4.5 0.36 0.50 0.44 5.5 0.36 0.50 0.44 V IOL 24 mA 24 mA VI = VCC, GND IIN Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 ± 1.0 µA IOZ Maximum TRI-STATE 5.5 ± 0.25 ± 5.0 ± 2.5 µA VI = VIL, VIH VO = VCC, GND 1.6 1.5 mA 50 75 mA VI = VCC - 2.1V VOLD = 1.65V Max -50 -75 mA 80.0 40.0 µA Current ICCT Maximum ICC/Input 5.5 IOLD (Note 8) Minimum Dynamic 5.5 IOHD Output Current 5.5 ICC Maximum Quiescent 5.5 0.6 4.0 Supply Current VOHD = 3.85V Min VIN = VCC or GND Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. Note 9: ICC for 54ACT 54ACT @ 25°C is identical to 74ACT 74ACT @ 25°C. 5 PrintDate=1997/04/24 PrintTime=10:20:14 5738 ds009958 Rev. No. 1 www.national.com Proof 5 AC Electrical Characteristics See Section 0 for Waveforms DSXXX VCC Symbol Parameter 74AC TA = +25°C 54AC TA = -55°C 74AC TA = -40°C (Note 10) CL = 50 pF to +125°C CL = 50 pF to +85°C CL = 50 pF (V) Min tPHL Typ Max Min Max Min Propagation Delay 3.3 1.5 10.0 13.5 1.0 16.5 1.5 15.0 Dn to On tPLH 5.0 1.5 7.0 9.5 1.5 11.5 1.5 Propagation Delay 3.3 1.5 9.5 13.0 1.0 16.0 1.5 14.5 5.0 1.5 7.0 9.5 1.5 11.5 1.5 Propagation Delay 3.3 1.5 10.0 13.5 1.0 16.5 1.5 15.0 5.0 1.5 7.5 9.5 1.5 12.0 1.5 Propagation Delay 3.3 1.5 9.5 12.5 1.0 15.0 1.5 14.0 5.0 1.5 7.0 9.5 1.5 11.0 1.5 Output Enable Time Output Enable Time 3.3 1.5 9.0 11.5 1.0 14.0 1.0 13.0 1.5 7.0 8.5 1.5 10.5 1.0 kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX 9.5 Output Disable Time Output Disable Time 3.3 1.5 8.5 11.5 1.0 13.5 1.0 13.0 1.5 6.5 8.5 1.5 10.0 1.0 9.5 3.3 1.5 10.0 12.5 1.0 16.0 1.0 14.5 5.0 tPLZ ns 10.5 5.0 tPHZ DSXXX 10.5 5.0 tPZL kk-kk 10.5 LE to On tPZH ns 10.5 LE to On tPHL No. Max Dn to On tPLH Fig. Units 1.5 8.0 11.0 1.5 13.5 1.0 12.5 3.3 1.5 8.0 11.5 1.0 13.0 1.0 12.5 5.0 1.5 6.5 8.5 1.5 10.5 1.0 10.0 Note 10: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements See Section 0 for Waveforms DSXXX VCC Symbol Parameter 74AC TA = +25°C 54AC TA = -55°C 74AC TA = -40°C (Note 11) CL = 50 pF to +125°C CL = 50 pF to +85°C CL = 50 pF (V) Typ ts 3.3 3.5 5.5 6.5 6.0 5.0 2.0 4.0 5.0 ns kk-kk DSXXX ns kk-kk DSXXX ns kk-kk DSXXX 4.5 Hold Time, HIGH or LOW 3.3 -3.0 1.0 1.0 1.0 Dn to LE 5.0 -1.5 1.0 1.0 1.0 LE Pulse Width, 3.3 4.0 5.5 6.5 6.0 HIGH tw No. Guaranteed Minimum Setup Time, HIGH or LOW Dn to LE th Fig. Units 5.0 2.0 4.0 5.0 4.5 Note 11: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.national.com PrintDate=1997/04/24 PrintTime=10:20:16 5738 ds009958 Rev. No. 1 6 Proof 6 AC Electrical Characteristics See Section 0 for Waveforms DSXXX VCC Symbol 54ACT 54ACT TA = -55°C 74ACT 74ACT TA = -40°C (Note 12) Parameter 74ACT 74ACT TA = +25°C CL = 50 pF to +125°C CL = 50 pF to +85°C CL = 50 pF (V) Fig. Units No. Min tPLH Propagation Delay Typ Max Min Max Min Max 5.0 2.5 8.5 10.0 1.5 12.5 1.5 11.5 ns kk-kk DSXXX 5.0 2.0 8.0 10.0 1.5 12.5 1.5 11.5 ns kk-kk DSXXX 5.0 2.5 8.5 11.0 1.5 12.5 2.0 11.5 ns kk-kk DSXXX 5.0 2.0 8.0 10.0 1.5 11.5 1.5 11.5 ns kk-kk DSXXX Dn to On tPHL Propagation Delay Dn to On tPLH Propagation Delay LE to On tPHL Propagation Delay LE to On tPZH Output Enable Time 5.0 2.0 8.0 9.5 1.5 11.5 1.5 10.5 ns kk-kk DSXXX tPZL Output Enable Time 5.0 2.0 7.5 9.0 1.5 11.0 1.5 10.5 ns kk-kk DSXXX tPHZ Output Disable Time 5.0 2.5 9.0 11.0 1.5 14.0 2.5 12.5 ns kk-kk DSXXX tPLZ Output Disable Time 5.0 1.5 7.5 8.5 1.5 11.0 1.0 10.0 ns kk-kk DSXXX Note 12: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements See Section 0 for Waveforms DSXXX VCC Symbol Parameter (Note 13) 74ACT 74ACT TA = +25°C CL = 50 pF 54ACT 54ACT TA = -55°C to +125°C CL = 50 pF (V) Typ ts Setup Time, HIGH or LOW 74ACT 74ACT TA = -40°C to +85°C CL = 50 pF Fig. Units No. Guaranteed Minimum 5.0 0.8 2.5 8.5 3.5 ns kk-kk DSXXX 5.0 0 0 1.0 1.0 ns kk-kk DSXXX 5.0 2.0 7.0 8.5 8.0 ns kk-kk DSXXX Dn to LE th Hold Time, HIGH or LOW Dn to LE tw LE Pulse Width, HIGH Note 13: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF CPD Power Dissipation Capacitance 40.0 pF Conditions VCC = OPEN VCC = 5.0V 7 PrintDate=1997/04/24 PrintTime=10:20:18 5738 ds009958 Rev. No. 1 www.national.com Proof 7 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: Book Extract End DS009958-7 DS009958-7 www.national.com PrintDate=1997/04/24 PrintTime=10:20:18 5738 ds009958 Rev. No. 1 8 Proof 8 THIS PAGE IS IGNORED IN THE DATABOOK 9 PrintDate=1997/04/24 PrintTime=10:20:18 5738 ds009958 Rev. No. 1 Proof 9 Physical Dimensions inches (millimeters) 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A www.national.com PrintDate=1997/04/24 PrintTime=10:20:19 5738 ds009958 Rev. No. 1 10 Proof 10 Physical Dimensions inches (millimeters) (Continued) 20 Lead Small Outline Integrated Circuit (S) NS Package Number M20B 20 Lead Plastic EIAJ SSOP (MSA) NS Package Number MSA20 MSA20 11 PrintDate=1997/04/24 PrintTime=10:20:19 5738 ds009958 Rev. No. 1 www.national.com Proof 11 Physical Dimensions inches (millimeters) (Continued) 20-Lead Molded Thin Shrink Small Outline Package, JEDEC NS Package Number MTC20 MTC20 www.national.com PrintDate=1997/04/24 PrintTime=10:20:20 5738 ds009958 Rev. No. 1 12 Proof 12 Physical Dimensions inches (millimeters) (Continued) 20-Lead Plastic Dual-In-Line Package (P) NS Package Number N20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 13 PrintDate=1997/04/24 PrintTime=10:20:20 5738 ds009958 Rev. No. 1 www.national.com Proof 13 13 54AC/74AC373 54AC/74AC373 · 54ACT/74ACT373 54ACT/74ACT373 Octal Transparent Latch with TRI-STATE Outputs LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 www.national.com National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: cnjwge@tevm2.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Français Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. PrintDate=1997/04/24 PrintTime=10:20:20 5738 ds009958 Rev. No. 1 Proof 14