NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: i2 39-52- 1104 5320-I0AT2 39-51-0105 5320-I0AG3 15-29-3102 5320- I0AG2 15-29-3101 5320-I0AG io edp no. eng. no. edp no. eng. no. edp no. eng. no. edp no. eng. no. no. of , i4 i2 39-5 I-7107 I-7107 5320-I0AGS3-GY 39-51-7106 532G-I0AGS2-GY 532G-I0AGS2-GY 39-5 , í64 Î04 64 44 EDP NO. 5320-50AT2 5320-50AT2 -40AT2 -40AT2 -34AT2 -34AT2 -30AT2 -30AT2 ?6AT2 -20AT2 -20AT2 - I6AT2 - I4AT2 5320-I0AT2 ENG. NO. , 5320-60AGS3 5320-60AGS3 -50AGS3 -50AGS3 -40AGS3 -40AGS3 -34AGS3 -34AGS3 -30AGS3 -30AGS3 ?6AGS3 ?0AGS3 - I6AGS3 - I4AGS3 5320-IOAGS3 ENG. NO. 5320-NAGS3 5320-NAGS3 ... | OCR Scan |
6 pages, |
SI 4606 -20AGS17F mx 2262 MOLEX 3953 -20AT2 -26AG3 26ag 5320-10AGS17F 39512100 -20AG3 ck 66 ul94v-0 I-7107 CI 7407 sd 7406 datasheet abstract |
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| Abstract: I2 39-5I-7I04 39-5I-7I04 5320-I0BGS3-GY 39-5I-7I03 39-5I-7I03 5320-I0BGS2-GY 39-5I-7I02 39-5I-7I02 5320- 0BGS l-GY 39-5I-2I05 39-5I-2I05 5320-I0BGS3 39-5I-2 39-5I-2 04 5320-I0BGS2 39-5I-2 39-5I-2 03 5320-I0BGS IO EDP NO. ENG. NO. EDP NO. ENG. ... | OCR Scan |
2 pages, |
sd 7404 sd 7402 molex 5578 series connector EN 4165 20bt2 GS47F 5320-60BG3 MOLEX 3953 datasheet abstract |
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| Abstract: JT MIL-DTL-38999 MIL-DTL-38999 Series II Cylindrical Connectors Contact Layouts JT MIL-DTL-38999 MIL-DTL-38999 Series - Contact Layouts Series II Contact Layouts - Continued Shell Size/Arr. 18-35 18-53 18-66 18-68 2 TEST & MEASUREMENT Contact #22D Contact #22M 18-96 Contact #22 Contact #20 20-1 Contact #16 Contact #12 20-2 Contact #10 Contact #8 20-11 1 1 31 21 41 4 1 2 3 9 10 17 25 34 43 1 51 21 17 4 41 1 2 3 10 25 34 43 51 58 64 A L M K J 66 58 64 51 53 52 B T S U N P R G F E F E C D G H A 51 J H ... | Original |
1 pages, |
rg180 coax contacts MIL-DTL-38999 MIL-DTL-38999 abstract |
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| Abstract: 2 TEST & MEASUREMENT MIL-DTL-38999 MIL-DTL-38999 Series II Cylindrical Connectors and Contact Layouts 8T MIL-DTL-38999 MIL-DTL-38999 Series II - Cylindrical High Density Bayonet Connectors, Crimp Rear Release Part No. Break Down: MS27497 MS27497 T 16 B 35 P E Basic Series Ordering Information Prefix/Shell Type/Class MS27472T MS27472T MS27508E MS27508E MS27497T MS27497T MS27499E MS27499E MS27484T MS27484T MS27473T MS27473T MS27474T MS27474T MS27472E MS27472E MS27484E MS27484E MS27473E MS27473E Class E T Description Square Flange Receptacle (Front Mount with Accessories Threads) Square Flange Receptacle ... | Original |
1 pages, |
ms27497 MS27484T circular CONNECTORS 28 pin layout MS27499E MS27472T MIL-DTL-38999 series II MS27473T MS27473E MS27484E MIL-DTL-38999 MIL-DTL-38999 abstract |
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| Abstract: MIL-DTL-38999 MIL-DTL-38999 Series I and III Cylindrical Connectors Contact Layouts LJT and TV MIL-DTL-38999 MIL-DTL-38999 Series - Contact Layouts Series I and III Contact Layouts Shell Size/Arr. 9-5 9-6 9-35 9-44 9-98 11-2 11-5 11-35 11-54 2 TEST & MEASUREMENT Contact #22D Contact #22M Contact #22 11-98 11-99 Contact #20 Contact #16 Contact #12 13-3 13-4 13-8 Contact #10 Contact #8 13-35 1 13-98 5 4 6 3 1 2 5 1 4 6 2 3 4 1 3 2 A C B B A E D C A B 1 2 10 3 9 11 13 12 8 4 7 6 5 D C A B E D A F B C F E ... | Original |
1 pages, |
MIL-DTL-38999 MIL-DTL-38999 abstract |
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| Abstract: RNJ - E115/G E115/G 26/11/03 10:53 Page 2 RNJ DESCRIPTION · EMI shielding · Shells are grounded before contact mating · Lightweight space saving design · Durability: 500 cycles · Moisture resistance: in addition to interfacial seal, main joint souffler and rear gasket on the plug are set up for moisture sealing between connector halves · Corrosion resistance: · Olive drab cadmium over nickel plating on aluminium shell (withstands 500 hours of salt spray exposure) or ele ... | Original |
8 pages, |
MIL-L-7808 socapex RNJ8982G23 893 906 266 HE308 MIL-H-5606 MIL-L-23699 TT-I-735 85049 torque rnj socapex rnj amphenol m2-v hydraulic fluid he308 socapex RNJ27 datasheet abstract |
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| Abstract: MIL-DTL-38999 MIL-DTL-38999 Series I and III Cylindrical Connectors Contact Layouts 8LT and 8D MIL-DTL-38999 MIL-DTL-38999 Series - Contact Layouts Series I and III Contact Layouts Shell Size/Arr. 09-01* 09-05 09-35 09-98 11-01 2 TEST & MEASUREMENT Contact #22D Contact #20 Contact #16 11-01 A Contact #12 Contact #10 Contact #8 Triax 11-02 11-02* 1 Contact #8 Power Contact #8 Quadrax 11-05 E A Contact #Elio® (optical fiber) Contact #4 Power 11-35 10 1 11 2 3 4 5 11-04 11-12 11-22 11-80 A 11-81 D A A A D A 5 ... | Original |
1 pages, |
MIL-DTL-38999 MIL-DTL-38999 abstract |
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| Abstract: RNJ Rack and panel cylindrical connectors MAIN CHARACTERISTICS · EMI shielding · Shells are grounded before contact mating · Lightweight space saving design · Durability: 500 cycles DESCRIPTION APPLICATIONS The RNJ series rack and panel connectors are qualified for the requirements of the standard DAT C 5935 x 0005 HE308 HE308 21, 25, 26 & 27T models. They are used to connect electrical and optical devices between a moving unit (rack) and a fixed unit (panel) without any coupling / uncoupl ... | Original |
8 pages, |
P-D-680 mil-c-39029 socket MIL H 5606 MIL-C-47220 rnj socapex he308 socapex TT-I-735 RNJ27 m2-v hydraulic fluid datasheet abstract |
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| Abstract: SC16C554B/554DB SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 4 - 8 June 2010 Product data sheet 1. General description The SC16C554B/554DB SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel (16 mode) or Motorola (68 mode) interface. The SC1 ... | Original |
58 pages, |
16C454 HVQFN48 LQFP64 LQFP80 PLCC68 SC16C554B ST16C554 ST16C554D TL16C554 transistor smd t1W SmD TRANSISTOR t1w SC16C554B/554DB SC16C554B/554DB abstract |
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| Abstract: SC16C554B/554DB SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 03 - 1 September 2005 Product data sheet 1. General description The SC16C554B/554DB SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel or Motorola interface. The SC16C554B/554DB SC16C554B/554DB i ... | Original |
56 pages, |
PLCC68 ST16C554 smd transistor txa SC16C554B plcc68 socket HVQFN48 LQFP80 LQFP64 TL16C554 16C454 logic control of conveyor SC16C554B/554DB SC16C554B/554DB abstract |
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| Abstract: RTL8139C RTL8139C RTL8139C-LF RTL8139C-LF RTL8139CL RTL8139CL RTL8139CL-LF RTL8139CL-LF 3.3V SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT DATASHEET Rev. 1.6 29 December 2005 Track ID: JATR-1076-21 JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw RTL8139C RTL8139C(L) Datasheet COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, ... | Original |
67 pages, |
TXC10 93C46 93C56 93C56 14 pin JATR-1076-21 PC99 Realtek Semiconductor REALTEK SEMICONDUCTOR 8129 RTL8139C FLY mobile MOTHERBOARD CIRCUIT diagram RTL8139A 003EH-003FH realtek rtl8139 programming RTL8139CL-LF RTL8139C abstract |
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| Abstract: APEX 20K Programmable Logic Device Family ® November 1999, ver. 2.05 Features. Data Sheet s Preliminary Information s Industry's first programmable logic device (PLD) incorporating System-on-a-Programmable-ChipTM integration MultiCoreTM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory Embedded system block (ESB) implementation of product-term logic used for combinatorial-intensive functions LUT logic used for regis ... | Original |
204 pages, |
G31* Diode 0 811 404 614 diode t25 4 L9 diode device data on semiconductor ba23 expander v16 248 B 503 f30 ar8 connect AMPP biasing circuit AM3 938 pinout resistor PC 817 data sheet BGA and QFP Package EPF20K100 datasheet abstract |
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| A V CE = 4 V for 2N5320 2N5320 2N5320 2N5320 for 2N5321 2N5321 2N5321 2N5321 1.1 1.4 V V h FE * DC Current Gain for 2N5320 I C = 500 mA V www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/3275-v1.htm |
STMicroelectronics | 02/04/1999 | 4.79 Kb | HTM | 3275-v1.htm |
| V for 2N5320 2N5320 2N5320 2N5320 for 2N5321 2N5321 2N5321 2N5321 1.1 1.4 V V h FE * DC Current Gain for 2N5320 I C = 500 m www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/3275.htm |
STMicroelectronics | 20/10/2000 | 6.93 Kb | HTM | 3275.htm |
| .1 1.4 V V h FE * DC Current Gain for 2N5320 I C = 500 mA V CE = 4 V I C www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/3275-v3.htm |
STMicroelectronics | 25/05/2000 | 6.57 Kb | HTM | 3275-v3.htm |
| A V CE = 4 V for 2N5320 2N5320 2N5320 2N5320 for 2N5321 2N5321 2N5321 2N5321 1.1 1.4 V V h FE * DC Current Gain for 2N5320 I C = 500 mA V www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/3275-v2.htm |
STMicroelectronics | 14/06/1999 | 4.75 Kb | HTM | 3275-v2.htm |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/52728641-985501ZC/wcd00ea6.zip (time_sim.vhd) |
Xilinx | 12/02/1999 | 7683.96 Kb | ZIP | wcd00ea6.zip |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/8430237-985500ZC/wcd00ea5.zip (time_sim.vhd) |
Xilinx | 12/02/1999 | 4169.69 Kb | ZIP | wcd00ea5.zip |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/95835256-987151ZC/wcd02ea3.z |
Xilinx | 13/07/1998 | 11223.63 Kb | Z | wcd02ea3.z |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/55088592-987155ZC/wcd02ea7.z |
Xilinx | 13/07/1998 | 6181.24 Kb | Z | wcd02ea7.z |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/10929841-987152ZC/wcd02ea4.zip (time_sim.vhd) |
Xilinx | 13/07/1998 | 7683.96 Kb | ZIP | wcd02ea4.zip |
| - Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12 - Date: Tue Jan 6 16:00:43 1998 - Design file: time_sim.nga - Device: 4005epc84-2 - CELL ROC - - Model for Reset-On-Configuration Cell library IEEE; use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is generic ( InstancePath: STRING := "*"; WIDTH : Time := 0 ns) ; port( O : out std_ulogic := '1' ) ; attribute VITAL_LEVEL0 of ROC : entity is TRUE ; end ROC ; architecture ROC_V o www.datasheetarchive.com/download/23395372-985947ZC/wcd010c8.zip (time_sim.vhd) |
Xilinx | 13/07/1998 | 4169.69 Kb | ZIP | wcd010c8.zip |