NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: First 33MHzÂ500MHz Programmable Synthesizer with 3 Independently Controlled Output Banks Replace 8 ICs with a Single Chip! The Good Stuff x x x x x x x Low jitter: , /HSTL Skew (Within Bank) , (Cycle-to-Cycle) ... | Original |
1 pages, |
SY89536L SY89535L SY89534L SY89533L SY89532L SY89531L PROGRAMMABLE SYNTHESIZER crystal 14MHZ SY89531/2/3/4/5/6 SY89531/2/3/4/5/6 abstract |
|
|||
| Abstract: varying increments of 50ps, 100ps, and 500ps. See the following pages for detailed specifications. , 650MHz 650MHz 650MHz 600MHz 600MHz 600MHz 550MHz Temperature Coefficient 50ps ±25ps 100ps , ±25ps 550ps ±25ps 600ps ±50ps 700ps ±50ps 800ps ±50ps 900ps ±50ps 1.0ns ±50ps 1.1ns ±50ps 1.2ns ±50ps 1.3ns ±50ps ±100ppm/°C 1.4ns ±50ps 50 ±10% 1.5ns ±50ps 1.6ns ±50ps 1.7ns ±50ps 1.8ns ±50ps 1.9ns ±50ps 2.0ns ±50ps 2.1ns ±50ps 2.2ns ±50ps 2.3ns ±50ps 2.4ns ±50ps 2.5ns ±50ps 2.6ns ±50ps ... | Original |
15 pages, |
FDC04505 FDC0405 FDC03505 FDC0305 FDC02505 FDC0205 FDC0105 FDC00505 FDC2405 FDD7005 FDD15005 FDD11005 FDC50 FDC3010 FDC2905 100KH 100KH abstract |
|
|||
| Abstract: for F 40MHz, ±50ps typ. RMS One sigma ± 50ps max. for F , 100ps max. for F> 40MHz, ±50ps typ. ± 50ps max. for F40MHz ... | Original |
1 pages, |
datasheet abstract |
|
|||
| Abstract: maximum of +/- 50ps. Clock skew is counted as an error factor in both front-end and back-end timing , , drvr = the driver, rcvr = the receiver, Tskew = clock skew (assumed to be unfavorable), +/-50ps , + 1.8v 2.5v 3.3v 2.5.3 Tf(GX-GX) 600ps 600ps 600ps  - Tskew 50ps = 50ps = 50ps = . . . .>= 1550ps >= 1150ps >= 1150ps >= Tih(GX) 450ps 300ps 300ps ok ok ok , Tskew 50ps = 50ps = 50ps = . . . .>= Tih(BR) 850ps >= 0 850ps >= 0 850ps >= 0 ok ok ok ... | Original |
6 pages, |
750gX 750GX 750GX abstract |
|
|||
| Abstract: * 0.43 = 7.8ns RxCLKOUT 4:3 0.43 1 4 7.8ns #1= 50ps #2TCCD = 2.5nsNote 1 #3 = 50ps #4RCCD = 4nsNote 1 Note 1: 3.3V FPD TCCD RCCD Note 2: ASIC 1. FPD ... | Original |
3 pages, |
sxGA FIFO AN-1084 1084 3.3V AN-1084 abstract |
|
|||
| Abstract: Differential Clocks · Low skew < 50ps · Low jitter < 50ps cycle-to-cycle · < 1 ps additive RMS phase jitter ... | Original |
1 pages, |
PI6C20400B 400B PI6C20400B abstract |
|
|||
| Abstract: COAX CABLE 3.2Gbps MAX3800 MAX3800 OUTPUT Equalizer Output ACTUAL SCOPE DATA 50ps/div 50ps/div ... | Original |
1 pages, |
MAX3800 equalizer ic MAX3800 abstract |
|
|||
| Abstract: * 0.43 = 7.8ns RxCLKOUT 4:3 0.43 1 4 7.8ns #1= 50ps #2TCCD = 2.5nsNote 1 #3 = 50ps #4RCCD = 4nsNote 1 Note 1: 3.3V FPD TCCD RCCD Note 2: ASIC 1. FPD ... | Original |
3 pages, |
AN-1084 AN-1084 abstract |
|
|||
| Abstract: max. Jitter 20uA max. ± 250ps max. for F33MHz, ±50ps , ± 50ps max. for F33MHz, ±20ps typ. ± 50ps max. for F , max. for F 40MHz, ±50ps typ. RMS One sigma ± 50ps max. , typ. ± 100ps max. for F> 40MHz, ±50ps typ. ± 50ps max. for F ... | Original |
2 pages, |
TTL 7475 datasheet abstract |
|
|||
| Abstract: max. Jitter 20uA max. ± 250ps max. for F33MHz, ±50ps , ± 50ps max. for F33MHz, ±20ps typ. ± 50ps max. for F ... | Original |
1 pages, |
datasheet abstract |
|
|||
| Abstract: Data eye from pattern generator Data eye after 25-inch FR4 trace Data eye after DS40MB200 DS40MB200 50 ps/DIV Pattern Generator, 4 Gb/s D+ D- 27-1 pattern Lr-OZZh 95-inr.h FR4 L 50 ps/DIV DS40MB200 DS40MB200 50 ps/DIV 25-inch FR4 board trace r i^-uv it^^THd 50 ps/DIV ... | OCR Scan |
1 pages, |
pattern generator DS40MB200 DS40MB200 abstract |
|
|||
| Abstract: Data eye from pattern generator Data eye after 25-inch FR4 trace Data eye after DS42MB200 DS42MB200 50 ps/DIV Pattern Generator, 4 Gb/s 2 -1 pattern 50 ps/DIV DS42MB200 DS42MB200 50 ps/DIV > PE EQ U X OUT+ [c-^ 40-inch FR4 trace tzh* 50 ps/DIV ... | OCR Scan |
1 pages, |
DS42MB200 DS42MB200 abstract |
|
|||
| Abstract: â-¡atei: Ausgabe 1. Änderung Erstellt_10,03,2000 Sz 2, Änderung 38,0 32,0 © 03,4(4x) Frequency Isolation Insertion loss VSWR Power Delay variation Phase flatness Intermodulation Tempenatune nange Connectons Dimensions ©- 4,0 un rn « 1930,„1990MHz min 20dB max 0,25dB max 1,25 40W cw 50ps max, , unit to unit max 0,2 degnees 2th onder better -72dBc, direct 2 tones 40W -10 „+90T solder pins (2x) 28x28x12,6 mm M 1 : 1 Art Isolator Artikel-Nr. 2722 162 1026 1 Typ VET 1036 Blatt-Nr. ... | OCR Scan |
1 pages, |
datasheet abstract |
|
|||
| Abstract: bel/ defining a degree of excellence LUMPED CONSTANT DELAY LINE 0432 PICOLINE AND 0402 SERIES TECHNICAL INFORMATION TEST CONDITIONS Pulse Width Pulse Period Rise Time Pulse Voltage Ambient Temperature 25°C 3.0 x Total Delay, 5.0 Nsec min. 4 x Pulse Width 1.0 NSec (10%-90%) 1 Volt PERFORMANCE CHARACTERISTICS Distortion 10% max. Performance Characteristics apply at above listed Test Conditions. ELECTRICAL CHARACTERISTICS Operating Temperature Range -55°CTo 125°C Temperature Coefficie ... | OCR Scan |
1 pages, |
25NS 043209 datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| two channels, such as clock and data, in 50ps increments. Both inputs may be adjusted in either direction in 7 increments of 50ps, for a total adjustment range of ±350ps. In addition, the clock input < 120ps Tr/Tf Delay either clock or data 50ps increments ± 350ps www.datasheetarchive.com/files/micrel/products/products/sy55856u.shtml |
Micrel | 26/06/2002 | 6.37 Kb | SHTML | sy55856u.shtml |
| * SAMTEC MODEL TEST FILE * 2 rows 10 pins each row x 8 section * for 50 ps edge rate or =MONITORED" * * * * QTS-RA QSS-01 QSS-01 QSS-01 QSS-01 * 1.0V/50PS TR * 50 OHM TERMINATIONS * * * input .TRAN 5PS 1NS * excitation * XDR1 1104 0 SRC50PS XDR2 1304 0 SRC50PS * * analysis & control * * .SUBCKT SRC50PS 3 2 *1.0v; 50ps; 20-80% * VS1 1 2 PWL( +0 0 +.02NS 0.06 +.03 www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/vendor list/samtec/spice/m_qtsra_qss01_sample.cir |
Spice Models | 29/07/2012 | 5.48 Kb | CIR | m_qtsra_qss01_sample.cir |
| ps for the CLKDLL input. The application note indicates that the maximum jitter is 50ps. This is a misprint. 50ps is from a testcase, but not the actual maximum spec. End of Record #4935 www.datasheetarchive.com/files/xilinx/docs/rp00017/rp017f7.htm |
Xilinx | 29/02/2000 | 4.64 Kb | HTM | rp017f7.htm |
| 89809L 89809L 89809L 89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available www.datasheetarchive.com/files/micrel/products/products/sy89809l.shtml |
Micrel | 26/06/2002 | 5.33 Kb | SHTML | sy89809l.shtml |
| . The SY89824L SY89824L SY89824L SY89824L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max max.) Low pin-to-pin skew (50ps max.) Available in a 10x10mm 64-pin www.datasheetarchive.com/files/micrel/products/products/sy89824-l.html |
Micrel | 26/06/2002 | 6.41 Kb | HTML | sy89824-l.html |
| Ultrahigh-Speed Hybrid Track-and-Hold Amplifiers Features Aperture Jitter of 50ps Input Range ±10V Output Current ±50mA Max Droop Rate uV/us Max 200ns Acquisition Time (0.01%; 10V Step) Applications Data Acquisition Systems Peak Measurement Systems Simultaneous Sample & Hold Analog Delay General Description The HTC-0300A HTC-0300A HTC-0300A HTC-0300A is a hybrid microcircuit track-and-hold amplifier useful in a wide range of signal processing applications, including waveform measurements, analog signal delay, and www.datasheetarchive.com/files/analog-devices/doc/productdescriptions/1708.html |
Analog Devices | 0.64 Kb | HTML | 1708.html | |
| /disabled as can happen with an asynchronous control. The SY89829U SY89829U SY89829U SY89829U features low pin-to-pin skew (50ps MAX (toggle) < 50ps ch-ch skew LVDS input includes 100W internal termination www.datasheetarchive.com/files/micrel/products/products/sy89829u.shtml |
Micrel | 26/06/2002 | 6.29 Kb | SHTML | sy89829u.shtml |
| ) ±20ppm/°C Temperature Stability Rise Time: 0.5ns, C L = 5pF Timing Jitter: 50ps at 170MHz www.datasheetarchive.com/files/linear/c1010/c1096/p7888/p7888.html |
Linear | 21/11/2005 | 7.99 Kb | HTML | p7888.html |
| ) ±20ppm/°C Temperature Stability Rise Time: 0.5ns, C L = 5pF Timing Jitter: 50ps at 170MHz www.datasheetarchive.com/files/linear/c1010/c1096/p7888/p7888-v1.html |
Linear | 09/02/2007 | 9 Kb | HTML | p7888-v1.html |
| / tf < 200ps Within-device skew < 50ps Propagation delay < 400ps www.datasheetarchive.com/files/micrel/products/products/sy55857l.shtml |
Micrel | 26/06/2002 | 6.56 Kb | SHTML | sy55857l.shtml |