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5 to 32 decoder circuit

Catalog Datasheet MFG & Type PDF Document Tags

QFP120

Abstract: SAA7186 circuit (DESCPro) Fig.1 Block diagram of decoder part (continued in Fig.2). 5 CONTROL I2C-BUS , Digital video decoder, Scaler and Clock generator circuit (DESCPro) · Mode 3: YUV15 to YUV0 and HREF/VS , Semiconductors Product specification Digital video decoder, Scaler and Clock generator circuit (DESCPro , Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1 SAA7196 · I2C-bus control , 2 The CMOS circuit SAA7196, digital video decoder, scaler and clock generator (DESCPro), is a
Philips Semiconductors
Original
QFP120 SAA7186 SAA7191B SAA7194 SAA7196H SAA7197

SAA7194

Abstract: specification Digital video decoder, scaler, and clock generator circuit (DESCPro) SAA7196 5. BLOCK , , digital video decoder, scaler and clock generator (DESCPro), is a highly integrated circuit for DeskTop , ) of the input interface are used in Y/C mode (Fig. 1(a) on page 5) to decode digitized luminace and , , and only one ADC is neccessary (Fig.3 on page 12). The 32-bit VRAM output port is interface to the , Expansion port is configurable to send data from the decoder unit or to accept external data for input
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VR017 VR019 VRO20 VR016 VR018 VR022

S-29131A

Abstract: S-7040D . PAGING DECODER IC (POCSAG) S-7040D Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment , SIG-IN BS2 BS1 8 7 6 5 4 3 2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 32 31 30 , pin has noise reduction circuit. Duty cycle of 25 to 75% is required. 14 SIG-IN In 15 BS2 Out Output pin for quick charge signal to RF circuit reference voltage. BS1 Out , oscillation and resets the internal circuit. IDROM data is fetched after recovery. Connect to VDD when the
Seiko Instruments
Original
S-7040DQP S-29131A S-7040XQP 92F-11 POCSAG S-18XX S-4520B

"Decoder IC"

Abstract: POCSAG DECODER IC (POCSAG) S-7040D n Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment The S , elements: Crystal oscillator (32 KHz/76 KHz), CG, RF · Direct interface to IDROM (S-29131A / S-2913) · 3 , correction up to 2 bits Battery saving Battery low alert Extended function 1 PAGING DECODER IC , Hard-clear circuit RST XRS CLK-OUT VDD VSS Figure 2 n Pin Configuration 32-pin QFP Top , synchronous to falling edge of the clock. H 5 RX-DATA Out Output pin for received data. L
Seiko Instruments
Original
QP032-A

hlx crystal

Abstract: HP611 specification Digital video decoder, Scaler and Clock SAA7196 generator circuit (DESCPro) 5 BLOCK DIAGRAM , ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Decoder part 7.1.1 , Digital video decoder, Scaler and Clock generator circuit (DESCPro) SAA7196 1 FEATURES Digital 8 , GENERAL DESCRIPTION The CMOS circuit SAA7196, digital video decoder, scaler and clock generator (DESCPro , ) â'¢ 32-bit VRAM output port; interface to the video memory. It outputs the down-scaled video data
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hlx crystal HP611 12 mhz hlx Block diagram on monochrome tv receiver circuit VR029 QFP52 QFP100 QFP160

POCSAG

Abstract: "Decoder IC" internal circuit and the POCSAG signal. Acceptable duty ratio of preamble ranges from 25% to 75%. 32 , .16 Circuit Design .21 PAGING DECODER IC (POCSAG) S , per an address External elements: Crystal oscillator (32 KHz/76 KHz), CG, Rf Direct interface to , output. Serial output of received data is enabled in synchronous to falling edge of the clock. H 5 , enabled by register). Thispinhas noise reduction circuit. Dutycydeof 25 to 75% is required. 15 BS2 Out
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DS-VTC-200 M19-M0 S-4S20B

5 to 32 decoder circuit

Abstract: VR015 Products Objective specification Digital video decoder, scaler and clock generator circuit (DESCPro , Digital video decoder, scaler and clock generator circuit (DESCPro) SAA7196 GENERAL DESCRIPTION The CMOS circuit SAA7196, digital video decoder and scaler (DESC), is a highly integrated circuit for , ADC is necessary (Fig.3). The 32-bit VRAM output port is interface to the video memory; it outputs the , identical to that of SAA7194. It is divided into two sections: - subaddress OOh to 1F for the decoder part
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VR015 VR024 YR025 5 to 32 decoder circuit YUV10 hs 117 line-locked mPC 514 S3T24 CYB56 VR010 VR011 YR012 VR013

"Preamble signal"

Abstract: . 16 Circuit Design. 21 PAGING DECODER , This pin has noise reduction circuit. Duty cycle of 25 to 75% is required. Output pin for quick charge signal to RF circuit reference voltage. Output pin for control signal of RF circuit power supply , 2.7 KHz /3.2 KHz. Input pin for oscillation control. "H" to this pin enables oscillation. "L" disables oscillation and resets the internal circuit. IDROM data is fetched after recovery. Connect to Vdo when the pin
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saa5000

Abstract: TBA2800 , 32 kBytes ROM, and 1024 Bytes RAM. An IM/I2C master interface, a 5-input ADC, ports and 6 PWM , circuit. Features: - CPU with 6 MHz clock (3 MIPS) Closed-Caption Decoder 3-line caption mode , Bytes RAM up to 29 port lines six PWM converters, 6-bit 5-input ADC (8-bit resolution/6-bit accuracy , to 512 kBytes external ROM up to 26 port lines six PWM converters, 6-bit 5-input ADC (8 , Caption Slicer 1>' 61 . â'¢ ' . ' - P W M O to H S y n C2 â  PW M 5 T' 61/ 1,-
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saa5000 TBA2800 CCU3000 CCU3001 3000-I 3001-I PLCC68 65C02

MCT 2E C4

Abstract: Block diagram on monochrome tv receiver circuit circuit (DESCPro) Fig.1 Block diagram of decoder part (continued in Fig.2). 5 CONTROL I2C-BUS , Digital video decoder, Scaler and Clock generator circuit (DESCPro) · Mode 3: YUV15 to YUV0 and HREF/VS , Semiconductors Product specification Digital video decoder, Scaler and Clock generator circuit (DESCPro , Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1 SAA7196 · I2C-bus control , 2 The CMOS circuit SAA7196, digital video decoder, scaler and clock generator (DESCPro), is a
Philips Semiconductors
Original
MCT 2E C4 Block diagram on monochrome tv transmitter VMUX Block diagram on monochrome tv receiver BUS CONTROLLED VERTICAL DEFLECTION SYSTEM digital cvbs encoder 1024 768 SCA52

scrambler satellite v.35

Abstract: BUS13r Quality Monitor Error Threshold Selection Ratio of channel errors to window size 1/8 5/32 3/16 7/32 1/4 9 , decoder with up to 3 bit soft decision inputs and an 80 stage trellis · Two versions for operation at the , Excellent performance for code rates up to 7/8 · Encoder and decoder valid data synchronization inputs and , forward error correction circuit that can provide more than 5 dB of coding gain for information rates up , rate 3/4. The decoder offers optional differential decoder and CCITT V.35 descrambling to be applied
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scrambler satellite v.35 BUS13r IESS-308 sCRAMBLER iess-309 standard IESS309 intelsat scrambler PM7018-256 PM7018-2500 IESS-308 IESS-309 PM7018 PM7018-256QC
Abstract: and decoder output filters are incorporated on-chip. Sam pling clock rates can be programm ed to 16,32 or 64K bits/second from an internal clock generator or externally injected in the 8 to 64K bits , Force Idle: A logical â'0â' at this pin gates a 0101. pattern internally to the decoder so that the decoder output goes to VD /2. W hen this pin is at a logical â' 1â' , the decoder operates as normal. D , Internal, 32kb/s = f/32 1 1 Internal, 16kb/s = f/64 External Clocks Clock rates refer to f = -
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MX629 MX629J 024MH BS9450 100C3
Abstract: rates can be programmed to 16, 32 or 64K bits/second from an internal clock generator The MX609 is a , circuit) vss Encoder Force Idle: When this pin is at a logical â'0â' the encoder is forced to an , â'Oâ'™â'™ at this pin gates a 0101. pattern internally to the decoder so that the Decoder Output goes to VD /2. When this pin is a logical â'1â' the decoder operates as D normal. Internal 1M12 , available at the ports for external circuit synchronization. Independent or com­ mon data rate inputs to -
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MX609J MX609P MX609LH MX609DW 1000H

circuit diagram of scrolling LED message display

Abstract: POCSAG Circuit Design configuration of ID-ROM). Table 5 Setup of number of retries 1. Interface to ID-ROM" for , DECODER IC (POCSAG) S-7038AF â  Circuit Design 1. Interface to ID-ROM 1.1 ID-ROM assignment Using S , circuit example: Tone-only pager 3.2 Display pager A CPU and a display unit are added to a tone-only , DECODER IC (POCSAG) S-7038AF Features Operating voltage : 1.7 to 5.5 V (3.0 V typ.) Current consumption , External elements: Crystal oscillators (32 kHz/76 kHz), Cq, Rf Direct interface to IDROM (S
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circuit diagram of scrolling LED message display 7038A 29131 TSI S 14001 s7038af S-14001 SEGO-31

LHi 874

Abstract: LHi 888 the decoder part (Tables 9 and 10 on page 32 and page 33) - subaddress 20h to 3F for the scaler part , Product specification Digital video decoder and scaler circuit (DESC) SAA7194 Table 5 VRAM port output , INTEGRATED CIRCUITS DATA SHEET SAA7194 Digital video decoder and scaler circuit (DESC , Product specification Digital video decoder and scaler circuit (DESC)SAA7194 Ï CONTENTS I VJBB 1 , SAA7194, digital video decoder and scaler (DESC), is a highly integrated circuit for DeskTop Video
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LHi 874 LHi 888 sp1191 APER XD7 sot349 ay 103 adhesive

7040D

Abstract: "Decoder IC" is enabled by register). This pin has noise reduction circuit. Duty cycle of 25 to 75% is required , internal circuit. IDROM data is fetched after recovery. Connect to VDD when the pin is not used. No , column means that the pin is pulled up to VDD. Seiko Instruments Inc. 3 PAGING DECODER IC , , XRST to VDD, other pins are open and the oscillation circuit operates. 4. Current flowing into the IC is defined to be positive. 5. f (VDD=3.0 V) - f0 f/ IC= ×106 (ppm) f0: Average frequency when
Seiko Instruments
Original
7040D diodes SY 200 POCSAG out of range BCH codes diode sy

SAA7194

Abstract: decoder part (Tables 9 and 10 on page 32 and page 33) - subaddress 20h to 3F for the scaler part (Tables , Product specification Digital video decoder and scaler circuit (DESC)SAA7194 n CO NTENTS 1. 2 , Digital video decoder and scaler circuit (DESC) SAA7194 1. FEATURES 2. GENERAL DESCRIPTION â , circuit SAA7194, digital video decoder and scaler (DESC), is a highly integrated circuit for DeskTop , are used in Y/C mode (Fig. 1(a) on page 5) to decode digitized luminace and chrominance signals
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motorcycle regulator

Abstract: transponder key application circuit is 25 millimeters (one inch). PIN FUNCTIONS Stand-alone transponder decoder , microcontroller interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from , clock to transistor Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce , components used in the decoder circuit as shown in the schematics, in Figure 2 and Figure 3. Table 9 lists , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5-bit IFF commands or opcodes
Microchip Technology
Original
motorcycle regulator transponder key 74HC4060 transponder digi-key e bike motor controller motorcycle ignition AN675 PIC16C56 QS-9000

motorcycle ignition circuit diagram

Abstract: LM358n pin application circuit is 25 millimeters (one inch). PIN FUNCTIONS Stand-alone transponder decoder , microcontroller interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from , clock to transistor Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce , components used in the decoder circuit as shown in the schematics, in Figure 2 and Figure 3. Table 9 lists , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5-bit IFF commands or opcodes
Microchip Technology
Original
motorcycle ignition circuit diagram LM358n pin circuit diagram voltage regulator for motorcycle 1N4148 2N3904 74HC4060 DS00675D-

DN7437

Abstract: P3499 stored in EEPROM. The decoder reads the transponder's 32-bit serial number, forces the upper 4 bits to 6h , Q1. This transistor drives the resonant circuit formed by R1, C1 and L1 to produce a magnetic field , output DATA_T2B is fed directly to the microcontroller. Table 8 lists the components used in the decoder , interfaces to the base station circuit by means of two wires: DATA_T2B used to read data from the transponder , functions of the HCS410. IFF Commands The HCS410 transponder responds to 5-bit IFF commands or opcodes
Microchip Technology
Original
DN7437 P3499 DS40149 LM78L05ACH dual diode ser. 2A 100V SOT23 P4773 DS00675C- 00662B-
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