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TMX320DM8168ACYG Texas Instruments 16-BIT, 48MHz, OTHER DSP, PBGA1031, PLASTIC, BGA-1031 visit Texas Instruments
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TMS470R1VC338PZA Texas Instruments 32-BIT, MROM, 48MHz, RISC MICROCONTROLLER, PQFP100, PLASTIC, LQFP-100 visit Texas Instruments
TMS470R1A128PZ-TR Texas Instruments 32-BIT, FLASH, 48MHz, RISC MICROCONTROLLER, PQFP100, PLASTIC, LQFP-100 visit Texas Instruments

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48MHZ

Catalog Datasheet MFG & Type PDF Document Tags

24MHZ

Abstract: 48MHZ 48Mhz. Af ter in put sam pling, this pin will gen er ate 14.318Mhz clock. IOAPIC 24 O 2.5V , fixed 48Mhz USB clock and one selectable 24 or 48Mhz output clock n Supports 2-wire I2C serial bus , tached. Power Con nec tions: VDD1 : REF, XIN, XOUT VDD2 : 48MHZ,24/48MHZ,SDATA,SCLK VDD3 : PCIF , * 48MHZ/F1* 4,13 B At power- up, these pins are in put and will de ter mine the CPU clock fre , by Fre quency Ta ble. CPU(0:1) SDATA,SCLK 48MHZ 4,5,6,7,8, 10,11 22,21 18,17 13 O I
PhaseLink
Original
PLL52C68-02 24MHZ PIN14 PLL52C68- 24/48MHZ

BU20360

Abstract: Biforst Technology 12MHz Phase Locked Loop; PLL 48MHz USB USB 2 2 I S I S USB I2S I2S USB to I2S , ) (3.3V) PLL External Filter Circuit Connect Path 3.3V 0 : 1 : 12MHz 48MHz XIN Input Clock Source Frequency Select 0 : 12MHz 1 : 48MHz High Level Trigger Active High Level , Level Trigger Active EXT_CLK_EN = 0, CLK_SEL = 0 : 12MHz EXT_CLK_EN = 0, CLK_SEL = 1 : 48MHz EXT_CLK_EN = 1, CLK_SEL = 0 : 12MHz (3.3V) EXT_CLK_EN = 1, CLK_SEL = 1 : 48MHz 46 XOUT
Biforst Technology
Original
BU20360 1N4004 LQFP48 Biforst Technology digital amplifier dvd with usb circuit diagram 2000/W

CY28158

Abstract: 48MHZ CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ , # CY28158 STOP Clock Logic SPREAD# SEL0 SEL1 (CPU leads) 48MHz · 3901 North First , clock outputs, running at 16.67 MHz REF [0­1] 2, 3 Reference clock outputs, 14.318 MHz 48MHZ 30 48-MHz USB clock output CPU_STOP# 36 Active LOW input, disables CPU and 3V66 clocks , PCI ground GND_3V66 20, 21, 24 3.3V 66-MHz (AGP) ground GND_48MHZ 29 3.3V 48-MHz
Cypress Semiconductor
Original
CK133 VDD33 VDD25 SEL133/100 CY28158PVC 51-85062-C

PLL52C68-04

Abstract: 24MHZ . n 4 CPU, 8 PCI and 2 IOAPIC clocks n Three 14.318Mhz, one fixed 48Mhz USB clock and one selectable 24 or 48Mhz output clock n Supports 2-wire I2C serial bus interface with readback. n Spread , : VDD1 : REF(0:2),XIN, XOUT VDD : 48MHZ,24/48MHZ PCIF, PCI(0:6),SDATA,SCLK VDDL1 : IOAPIC(0:1 , Power sup ply for REF(0:2), XIN and XOUT 3.3V Power sup ply for 24/48MHZ, 48MHZ, SDATA, SCLK,PCIF,PCI(0 , se rial in ter face port 48MHZ 22 O 48MHZ out put for USB ap pli ca tions.At power- up
PhaseLink
Original
PLL52C68-04 PIN23
Abstract: CPU1 CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ CY28158 PLL2 1 48MHz Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel , Name X1[1] X2[1] CPU [0­5] PCI [1­5] PCI_F 3V66 [0­1] IOAPIC [0­2] REF [0­1] 48MHZ CPU_STOP# PCI_STOP# PWR_DWN# SPREAD# SEL1 SEL0 SEL133/100# GND_REF GND_PCI GND_3V66 GND_48MHZ GND_IOAPIC GND_CPU GNDA VDD_REF VDD_PCI VDD_3V66 VDD_48MHZ VDD_IOAPIC VDD_CPU VDDA Pins 5 6 41, 42, 45, 46, 49, 50 11, 12, 14, 15, 18 9 25 Spectra Linear
Original
CY28158PVCT CY28158OXC CY28158OXCT
Abstract: GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ CY28158 PLL2 1 48MHz Cypress Semiconductor Corporation Document #: 38-07039 Rev. *A · 3901 North , Summary Name X1[1] X2[1] CPU [0­5] PCI [1­5] PCI_F 3V66 [0­1] IOAPIC [0­2] REF [0­1] 48MHZ CPU_STOP# PCI_STOP# PWR_DWN# SPREAD# SEL1 SEL0 SEL133/100# GND_REF GND_PCI GND_3V66 GND_48MHZ GND_IOAPIC GND_CPU GNDA VDD_REF VDD_PCI VDD_3V66 VDD_48MHZ VDD_IOAPIC VDD_CPU VDDA Pins 5 6 41, 42, 45, 46, 49, 50 11, 12, 14, 15 Cypress Semiconductor
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Dp 104

Abstract: DSO20 FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz , Information Description 10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes , CTLTM Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone , µSerDesTM FIN210AC - 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz , up to 48MHz FIN210AC (Serializer DIRI=1) Pin Descriptions Pin Name Description DIRI
Fairchild Semiconductor
Original
FIN210ACMLX FIN210ACGFX Dp 104 DSO20 FIN210 JESD22-A114 MO-195

48MHZ

Abstract: PCK2010 3.3V 48MHz USB clock â'¢ Two 3.3V reference clocks @ 14.318 MHz â'¢ Reference 14.31818 MHz Xtal , CPUCLK0 Vss VDD3V Vss PCISTOP CPUSTOP PWRDWN SPREAD SEL1 SEL0 VDD3V 30] 48MHz Vss SW00352 m 4Ãj 13 , /100 Select input pin for enabling 133MHz or 100MHz CPU outputs. H = 133MHz, L = 100MHz 30 48MHz 3.3V fixed 48MHZ clock output 32, 33 SEL [0-1] Logic select pins. TTL levels. 34 SPREAD 3.3V LVTTL input , 0 NOTES 0 0 0 3-State Don't care 0 0 1 Reserved Reserved 1 0 1 0 Active 100MHz, 48MHz PLL
-
OCR Scan
PCK2010 100/133MHZ 318MH 100/133MH SSOP56 MO-118AB

48MHZ

Abstract: CY28158 CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ , # CY28158 STOP Clock Logic SPREAD# SEL0 SEL1 (CPU leads) 48MHz · 3901 North First , clock outputs, running at 16.67 MHz REF [0­1] 2, 3 Reference clock outputs, 14.318 MHz 48MHZ 30 48-MHz USB clock output CPU_STOP# 36 Active LOW input, disables CPU and 3V66 clocks , PCI ground GND_3V66 20, 21, 24 3.3V 66-MHz (AGP) ground GND_48MHZ 29 3.3V 48-MHz
Cypress Semiconductor
Original

5028b

Abstract: WF5028 48MHz, fOUT = 48MHz mA V DD = 1.2V 1.3 2.0 mA V DD = 0.9V 0.9 1.4 mA V DD , 1.4 mA fo = 48MHz, fOUT = 6MHz V DD = 0.9V 0.55 0.9 mA 5028×5 (fo/16), 1, , INHN = "OPEN", V DD = 1.5V 1.1 1.7 mA V DD = 1.2V 0.8 1.2 mA fo = 48MHz, fOUT = 3MHz V DD = 0.9V 0.5 0.8 mA 5028×6 (fo/32), 1, , INHN = "OPEN", fo = 48MHz , 0.5 0.8 mA V DD = 1.5V IDD 2.6 5028×3 (fo/4), 1, , INHN = "OPEN", fo = 48MHz
Nippon Precision Circuits
Original
WF5028 CF5028C 5028b WF5028A DUTY50 CF5028B CF5028
Abstract: (3.3 V, 66 MHz) â'" 2 REF (3.3 V, 14.318 MHz) â'" 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP , VDD2.5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz , , 3V66, PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium , (PLLs) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters , -state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be Texas Instruments
Original
CDC922 133-MH SCAS634 CDCR81 CDCR82 CDCR83
Abstract: , providing less than -130dBc at 10kHz offset at 48MHz. The very low jitter (3.5ps RMS period jitter) makes , PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) FEATURES â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ â'¢ VCXO output for the 48MHz to 100MHz range Low phase noise (-130 dBc @ 10kHz offset at 48MHz). CMOS , ) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1 PLL502-03 Low Phase Noise VCXO (48MHz , ) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 2 PLL502-03 Low Phase Noise VCXO (48MHz PhaseLink
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100MH PLL502-03SC PLL502-03HSC P502-03SC P502-03HSC

ZO 150

Abstract: ZO150 =75 [=Zin] 82pF series capacitors on Pin 4&7 48MHz 0 -1.343 -1.381 -1.5 -1.8 -2.1 -2.4 , -3 57MHz 48MHz 870MHz 82pF series capacitors on Pin 4&7 0 1080MHz 170MHz 57MHz 1.6 Return Loss 82pF series capacitors on Pin 4&7 48MHz 2 -6 1.2 -9 0.4 , 12 8 57MHz -3 82pF series capacitors on Pin 4&7 48MHz 870MHz 0 1080MHz 170MHz 57MHz 16 Common Mode Rejection 82pF series capacitors on Pin 4&7 48MHz 20 1000
Anaren
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B0011E75300A00 ZO 150 ZO150 balun transformer 75 ohm unun 1080MHz

Frequency multiplier 1mHz 100MHz

Abstract: 48MHZ for the 48 to 100MHz range, providing less than -130dBc at 10kHz offset at 48MHz. The very low jitter , ABV0203 Low Phase Noise VCXO (48MHz to 100MHz) FEATURES · · · · · · · · · · VCXO output for the 48MHz to 100MHz range Low phase noise (-130 dBc @ 10kHz offset at 48MHz). CMOS output. 12 to 25MHz , Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 1 ABV0203 Low Phase Noise VCXO (48MHz to 100MHz , : 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/11/05 Page 2 ABV0203 Low Phase Noise VCXO (48MHz to
Abracon
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Frequency multiplier 1mHz 100MHz ABV0203SC ABV0203HSC

48MHZ

Abstract: CY28158 CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ , # CY28158 STOP Clock Logic SPREAD# SEL0 SEL1 (CPU leads) 48MHz · 3901 North First , , 14.318 MHz 48MHZ 30 48-MHz USB clock output CPU_STOP# 36 Active LOW input, disables CPU , 7, 8, 13, 19 3.3V PCI ground GND_3V66 20, 21, 24 3.3V 66-MHz (AGP) ground GND_48MHZ 29 3.3V 48-MHz (USB) ground GND_IOAPIC 52 2.5V APIC ground GND_CPU 40, 44, 48
Cypress Semiconductor
Original

100mhz phase comparator

Abstract: osc 48mhz 48MHz. The very low jitter (12 ps RMS period jitter) makes this chip ideal for applications requiring , Preliminary for proposal PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) FEATURES · · · · · · · · VCXO output for the 48MHz to 100MHz range Low phase noise (-130 dBc @ 10kHz offset at 48MHz). CMOS output. 12 to 25MHz crystal input. Integrated variable capacitors. Selectable , proposal PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) PIN DESCRIPTIONS Name Number Type
PhaseLink
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100mhz phase comparator osc 48mhz 100MHz FREQUENCY DIVIDER Varicap

UT54ACTS220

Abstract: UT69151 . The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle , 48MHz VSS DESCRIPTION 1 6 9 7 8 RCS DMACK 14-Lead Flatpack Top View NC 1 , 5 10 MRST 48MHz VSS 6 9 7 8 RCS DMACK LOGIC SYMBOL MRST 48MHz RCS , user wishes to buffer. 6 48MHz 48MHz Clock. The 24MHz clock is created by dividing this signal , 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling edge of 24MHz is
UTMC Microelectronic Systems
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UT54ACTS220 UT69151 UT54ACT220

24mhz crystal 14pin dip

Abstract: by 02 be one 48MHz clock. One 14.318MHz reference clocks. 3.3V operation; 50% percent duty cycle. Available , GND 11 CP U 10 VDD 9 VDD 8 48MHz/FS 0*^ BLOCK DIAGRAM Note: ^: Pull up, v , one end of the crystal. XOUT 3 O 14.318MHz crystal output. REF/F2* 24MHz/F1* 48MHz/F0 , power-on. 48MHz 8 B 48MHz output for USB after input data latched during power-on. VDD 4 , Output Impedance DT Z0 1 REF, 48MHz, 24MHz Measured @ 0.4V ~ 2.4V, C L =10-30pf 1
PhaseLink
Original
PLL202-02 24mhz crystal 14pin dip by 02 be LL2020 phaselink pll202 LL202-02
Abstract: FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz , Ordering Information 10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes , "¢ Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone Example , µSerDesâ"¢ FIN210AC â'" 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz , Supporting Cameras and Small Displays up to 48MHz FIN210AC (Serializer DIRI=1) Pin Descriptions Pin Fairchild Semiconductor
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48008

Abstract: 48MHZ GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ 1 48MHz Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 CY28158 STOP , Reference clock outputs, 14.318 MHz 48MHZ 30 48-MHz USB clock output CPU_STOP# 36 Active , ) ground GND_48MHZ 29 3.3V 48-MHz (USB) ground GND_IOAPIC 52 2.5V APIC ground GND_CPU , 3.3V 66-MHz (AGP) voltage supply VDD_48MHZ 31 3.3V 48-MHz (USB) voltage supply VDD_IOAPIC
Spectra Linear
Original
48008

CDC921

Abstract: CDC922 , 66 MHz) ­ 2 REF (3.3 V, 14.318 MHz) ­ 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package , .5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND , , PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III , ) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and , , which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be
Texas Instruments
Original
CDC921

CY2285

Abstract: osc 24mhz = 24 MHz on pin14 USBCLK 13 3.3V 48-MHz USB clock output USB_IOCLK/TS 14 3.3V 48-MHz , 27 3.3V 14.318-MHz reference clock output USBCLK/SEL100/66 14 3.3V 48-MHz USB clock , USB 48-MHz 48 48.008 +167 Power Management Logic PCI_STOP PWR_DWN X X 0 , = 24 MHz on pin14 USBCLK 13 3.3V 48-MHz USB clock output USB_IOCLK/TS 14 3.3V 48-MHz , 27 3.3V 14.318-MHz reference clock output USBCLK/SEL100/66 14 3.3V 48-MHz USB clock
Cypress Semiconductor
Original
CY2285 osc 24mhz 100-MH CY2285-2 CY2285PVC-3 210-M 51-85079-C

48-PIN

Abstract: CDC921 (3.3 V, 14.318 MHz) ­ 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package Designed for Use with , .5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND SEL133/100 description The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz , the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback , via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be independently disabled via the
Texas Instruments
Original
48-PIN SCAS623

CDC921

Abstract: CDC922 , 66 MHz) ­ 2 REF (3.3 V, 14.318 MHz) ­ 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package , .5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND , , PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III , ) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and , , which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be
Texas Instruments
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48-PIN

Abstract: CDC924 (3.3 V, 14.318 MHz) ­ 1 48MHz (3.3 V, 48 MHz) Packaged in 56-Pin SSOP Package Designed for Use with , on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. DL PACKAGE (TOP VIEW) GND , .3V 48MHz GND All output frequencies are generated from a 14.318-MHz crystal input. A reference clock , , one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip , CPU_DIV2 3V66 PCI, PCI_F 48MHz REF APIC L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Texas Instruments
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CDC924 SCAS607A 318-MH

CDCR81

Abstract: CDCR83 MHz) ­ 3 APIC (2.5 V, 16.67 MHz) ­ 4 3V66 (3.3 V, 66 MHz) ­ 2 REF (3.3 V, 14.318 MHz) ­ 1 48MHz , system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz , CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND All output frequencies are generated from a , generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need , SEL1 L L OUTPUTS FUNCTION SEL0 CPU CPU_DIV2 3V66 PCI, PCI_F 48MHz REF
Texas Instruments
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CDC925 SCAS633
Abstract: 3V66 (3.3 V, 66 MHz) â' 2 REF (3.3 V, 14.318 MHz) â' 1 48MHz (3.3 V, 48 MHz) Packaged in 56 , Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. GND REF0 , VDD2.5V CPU1 CPU0 GND VDD3.3V GND PCI_STOP CPU_STOP PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz , generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters , SEL0 CPU CPU_DIV2 3V66 PCI, PCI_F 48MHz REF APIC L L Hi-Z Hi-Z Texas Instruments
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SCAS607B

intel 845 circuit diagram all chip

Abstract: 48MHZ PCI_F0:2 2 PCI0:6 VDD_48MHz 3V66_3/48MHz_1 VDD_48MHz 48MHz_0 PWRDWN# 24_48MHz 2 SDATA , VDD_PCI VTT_PWRGD# RESET# GND_48MHz *FS0/48MHz_0 *FS1/24_48MHz VDD_48MHz 1 2 3 4 5 6 7 8 , PCI(1:6) O PCI Clock Output 1 to 6: 3.3V PCI clock outputs. 22 48MHz_0/FS0 I/O 48MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum output. This pin also serves as a , Pin # 24_48MHz/FS1 Name I/O 24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or
Spectra Linear
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CY28378 CK-408 intel 845 circuit diagram all chip SSOP-48 XTAL OSC 40.000 mhz 3/48MH CY28378OC CY28378OCT
Abstract: MHz on pin14 USBCLK 13 3.3V 48-MHz USB clock output U SB JO C LK /TS 14 3.3V 48-MHz , 27 3.3V 14.318-MHz reference clock output USBCLK/SEL100/66 14 3.3V 48-MHz USB clock -
OCR Scan
CY2285PVC-2

ck408

Abstract: PCK2023 the current value of the external CPU_Stop pin VCH select 66 MHz/48MHz enabled not used spread , PCI_Stop USB 48MHz output enabled DOT 48 MHz output enabled TYPE RW RW RW RW POWER UP CONDITION 1 = enabled , PCIF2 7 N/A 6 7 RW RW USB 48MHz DOT 48MHz 39 38 N/A N/A 2001 Aug 20 19
Philips Semiconductors
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PCK2023 ck408 PCK2023A CK408

CK408

Abstract: PCK2023 externally selected All CPU clock pairs 44, 45, 48, 49, 51, 52 53 5 VCH select 66 MHz/48MHz , 7 N/A 6 USB 48MHz output enabled RW 1 = enabled USB 48MHz 39 N/A 7 DOT 48 MHz output enabled RW 1 = enabled DOT 48MHz 38 N/A BYTE 3 2003 Jul 31 19
Philips Semiconductors
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PCK2023DGG PCK2023DL

48-PIN

Abstract: CDC921 (3.3 V, 14.318 MHz) ­ 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package Designed for Use with , .5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND SEL133/100 description The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz , the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback , via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be independently disabled via the
Texas Instruments
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ldt0

Abstract: 10BQ015 used to generate the host frequencies and 48-MHz clock frequencies. On-chip loop filters and internal , ., random access of the registers not supported). The CPU, PCI, PCI_F, LDT, FDC (24/48-MHz), and USB (48-MHz , 48-MHz PLL: Connected to VSS through filter. Used to ground the 48-MHz PLL on the chip LDT_Stop , should only be turned off for debug and test purposes. USB 31 O 3.3-V, fixed 48-MHz non-SSC , CPU-PLL on the chip VDDF 32 P Analog VDD for 48-MHz PLL: Connected to 3.3-V power supply
Texas Instruments
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CDC960 ldt0 10BQ015 BZX84C3V3 HT66 clawhammer 200MH SCAS675

CY2285

Abstract: USBCLK 13 3.3V 48-MHz USB clock output USB_IOCLK/TS 14 3.3V 48-MHz or 24-MHz output and , 3.3V 48-MHz USB clock output or select input and frequency select strap option (use 10-k external , 100 99.77 ­2300 USB 48-MHz 48 48.008 +167 Power Management Logic PWR_DWN
Cypress Semiconductor
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CY2285PVC-1 38-00732-C 51-85079-B

ANS16

Abstract: W224 W224B 133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms Features APIC, 48-MHz, 3V66 , Running) · Seven SDRAM clock (one DCLK for Memory Hub) · Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video DOT clock · Three 3V66 Hublink/AGP outputs · One VCH clock (48-MHz , PWR_DWN# VDD_PCI PCI_F Stop Clock Control PCI1:6 PCI_STP# VDD_3V66 3V66_0:1 3V66_AGP VDD_48MHz PLL2 USB (48MHz) DOT (48MHz) SDATA SCLK SMBus Logic VCH_CLK 1 2 3 4 5 6 7 8 9
Cypress Semiconductor
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ANS16 W224 ILB1206 48-MH 67-MH
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