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48-bit

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: into the bit bucket. An ADSP-21160 ADSP-21160 2-Mbit block of memory that contains 48-bit instruction words can , single-precision IEEE floating-point data. 48-bit words contain either instructions or 40-bit extended-precision , data into the appropriate internal word width, either 64-bits, or 48-bits. Direct core accesses to , in internal memory. The 64-bit PM Data bus is used to transfer 48-bit instructions (and 64-bit, 40 , the DM data bus. This register also provides 40- and 48-bit data transfer support between the ... Analog Devices
Original
datasheet

32 pages,
288.31 Kb

00000x7 00000x4 32Kx16bit TEXT
datasheet frame
Abstract: PCM-4381 PCM-4381 PCI-104 PCI-104 48-bit LVDS1 SATA2 SATA1 ATX/ AT Power USB3, 4 USB 5, 6 48-bit LVDS2 COM2, 3, 4 & , ® Pentium® M/ Celeron® M Processor on board/ Socket type Display combination: 48-bit LVDS1 + 48-bit LVDS2, CRT + 48-bit LVDS Dual 10/100/1000 Mbps Ethernet 16-bit GPIO, 4 COM (Supports Auto flow control), 2 , DVMT 3.0 supports up to 128 MB Mobile Intel GMA 900 3D/2D engine 1 x 48-bit LVDS1, 1 x 48-bit LVDS2 , ) 48-bit LVDS connector Chrontel 7308 48-bit LVDS Connector VGA Connector SDVO BUS DDR2 400/533 ... Advantech
Original
datasheet

3 pages,
1284.79 Kb

LVDS 30 pin connector cable VGA 15 PIN CABLE CONNECTION DIAGRAM RTL8111B-GR PCM-4381 PCI-104 TEXT
datasheet frame
Abstract: 18-bit (i.e., DS90C365 DS90C365), 24-bit (i.e., DS90C385 DS90C385) and 24/48-bit (i.e., DS90C387 DS90C387) appli- cations , -bit (i.e., DS90C364A DS90C364A), 24-bit (i.e., DS90CF384A DS90CF384A) and 48-bit (i.e., DS90CF388 DS90CF388). These receivers sample the , Receiver Output Data Pin 24-bit 24-bit Tx 18-bit Tx 48-bit Tx (C385) (C365) (C387) 24-bit Rx 18-bit Rx 48-bit Rx (CF364A CF364A) (CF384A CF384A) (CF388 CF388) LSB 18-bit TFT Panel Data Signal R0 , -bit 24-bit Tx 18-bit Tx 48-bit Tx (C385) (C365) (C387) 24-bit Rx 18-bit Rx 48-bit Rx (CF364A CF364A ... National Semiconductor
Original
datasheet

5 pages,
25.87 Kb

VGA 18 BIT R0 R1 R2 R3 R4 R5 24 PIN TFT DISPLAY C365 C385 C387 DS90C364A DS90C365 DS90C385 DS90C387 DS90CF384A DS90CF388 GE-1 GE-2 "DUAL pixel" GE-4 TxIN10 TEXT
datasheet frame
Abstract: SRAM Total Size Block size (2) # of 48-bit words (per block) # of 32-bit words (per block) # of , -2106x processors. 32-bit memory words are used for single-precision IEEE floating-point data. 48-bit words , processor access the same block. Core Processor 32 x 48-Bit DAG 1 PROGRAM SEQUENCER DAG 2 , controller automatically packs external data into the appropriate word width, either 48-bit instructions or , combinations of 48-bit instruction words and 32-bit data words. Maximum efficiency (i.e. single-cycle ... Analog Devices
Original
datasheet

52 pages,
141.84 Kb

harvard architecture block diagram 0x21000 0X26000 ADSP-2100 ADSP-21000 ADSP-21060 ADSP-21060 reference manual ADSP-21061 ADSP-21062 ADSP-2106X fast page mode dram controller 0x0002 8kx16bit blocks in memory organization TEXT
datasheet frame
Abstract: are available for 18-bit (i.e., DS90C365 DS90C365), 24-bit (i.e., DS90C385 DS90C385) and 24/48-bit (i.e., DS90C387 DS90C387 , available in 18-bit (i.e., DS90C364A DS90C364A), 24-bit (i.e., DS90CF384A DS90CF384A) and 48-bit (i.e., DS90CF388 DS90CF388). These , -bit 18-bit 48-bit Rx Rx Rx (CF384A CF384A) (CF364A CF364A) (CF388 CF388) 24-bit Tx (C385) 48-bit Tx (C387 , Output Data Pin 18-bit Tx (C365) 24-bit 18-bit 48-bit Rx Rx Rx (CF384A CF384A) (CF364A CF364A) (CF388 CF388) 24-bit Tx (C385) 48-bit Tx (C387) TFT Panel Data Signal B0 Txin16 B16 Rxout16 ... National Semiconductor
Original
datasheet

5 pages,
26.07 Kb

C365 C385 C387 DS90C365 DS90C385 DS90C387 DS90CF384A DS90CF388 HSYNC, VSYNC, DE, input, output ds90C364 rgb 18 bit to lvds TEXT
datasheet frame
Abstract: . · Applications to configure memory to store 16-, 32-, 40-, or 48-bit words or combinations of these. The processor uses 32-bit memory words for single-precision IEEE floating-point data and 48-bit words , (PMD) bus, a 48-bit transmission path. Controlled by the processor's core, the PM bus provides a , for passing data between the 48-bit PM bus and the 40-bit DM bus or the 40-bit Register File , processor's core can access as one 48-bit register or as two separate registers, one 16-bit register (PX1 ... Analog Devices
Original
datasheet

68 pages,
279.01 Kb

00FF ADSP-21065L dsp 32 c processor eb3wm 40 pin EPD controller pm47-32 sec memory 32 pin addressing mode in core i7 pin diagram for core i7 processor TEXT
datasheet frame
Abstract: Data (0) 1st Data (0) 48th Data (0) SCLK Signal (Internal in 1st Device) 48-Bit Shift , ) 1st Data (0) 2nd Data (0) 3rd Data (1) 5th Data (1) 48-Bit Shift Register LSB+1 (Internal in 1st Device) 4th Data (1) 48-Bit Shift Register MSB-1 (Internal in 1st Device) 47th Data , ) 1st Data (0) 1st Data (0) 2nd Data (0) 2nd Data (0) 48-Bit Shift Register MSB (Internal , tWO SDO tF0 tR0 SCLK Signal (Internal in 2nd Device) 48-Bit Shift Register LSB (Internal ... Texas Instruments
Original
datasheet

26 pages,
531.18 Kb

SDI-12 circuit TLC5973 SBVS225 TEXT
datasheet frame
Abstract: (Internal in 1st Device) 48-Bit Shift Register LSB (Internal in 1st Device) 48-Bit Shift Register LSB+1 (Internal in 1st Device) 48-Bit Shift Register MSB-1 (Internal in 1st Device) 48-Bit Shift Register MSB , New GS Data SDO tF0 SCLK Signal (Internal in 2nd Device) 48-Bit Shift Register LSB (Internal in 2nd , Generator MSB 48-Bit Shift Register 47 Upper 8 Bits Lower 36 Bits Command Decoder (3AAh) SDO LSB gslat , CONFIGURATION The TLC5973 TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the ... Texas Instruments
Original
datasheet

27 pages,
408.26 Kb

TLC5973 SBVS225A TEXT
datasheet frame
Abstract: consists of 48-bit shift register. 48-bit latch and 48-bit LCD driver. The display data, which was input to the 48-bit shift register, is shifted to the 48-bit latch by the LOAD signal. Then the data is output to the LCD panel through the 48-bit LCD driver. FEATURES • 48 dots static LCD driving capability , Self/External oscillation ■ i r A. Joscl gndÒ- LCD Driver & E-OR 48-bit Data Latch 48-bit , signal and CLOCK signal. It is transferred to the 48-bit latch by the LOAD signal and it is output to ... OCR Scan
datasheet

7 pages,
154.59 Kb

oki lcd driver MSM5219BG lcd 60-pin lcd 60 pin 7 pin connection lcd wire 48-dot MSM5219BGS MSM5219B 48-DOT TEXT
datasheet frame
Abstract: consists of 48-bit shift register. 48-bit latch and 48-bit LCD driver. The display data, which was input to the 48-bit shift register, is shifted to the 48-bit latch by the LOAD signal. Then the data is output to the LCD panel through the 48-bit LCD driver. FEATURES • 48 dots static LCD driving capability , LCD Driver & E-OR T2 48-bit Data Latch ■ A S 48-bit Shift Register Seif/External oscillation , signal. It is transferred to the 48-bit latch by the LOAD signal and it is output to the LCD panel ... OCR Scan
datasheet

7 pages,
154.12 Kb

SEG23 MSM5219BGS msm5219bg MSM5219B MSM5219 lcd 60-pin 48-DOT TEXT
datasheet frame
Abstract: CHARACTERISTICS ■ 256 word x 48-bit Content Addressable Memory (CAM) - Optimized for Address Decoding in , 48-bit maskable comparator - Maskable-bits and maskable-words ■ 48-blt input word compared , DIAGRAM D,5 -Do ■+Comparand Register Command Register CAM Word 0 48-bit Reg Mask Register , _ CAM Word 255 O -J j? CD Q w - 48-bit Reg Compare with Mask o Logic r Status , and many other applications. The Am99C10 Am99C10 CAM is composed of 256 words, each consisting of a 48-bit ... OCR Scan
datasheet

29 pages,
529.5 Kb

Am99C10 TEXT
datasheet frame
Abstract: Command Register CAM Register CAM Word 0 48-bit Reg Compare with Mask Ü? Logic CAM Word 255 48-bit , of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10 Am99C10 is shown below. When , : ML0-ML255 ML0-ML255. 3 2 t JJ CAM Word 48-bit Register I Skip Empty Bit Bit 48-bit Comparator A=B with Mask 7 , , an exclu-sive-NOR comparator, an OR gate for masking, and a transistor for performing a 48-bit , register. 48-bit Data Transfers Data is transferred to and from the Am99C10 Am99C10 in 16-bit words. Data for the ... OCR Scan
datasheet

28 pages,
922.2 Kb

cd 4028 BA9S BA9876543210 AM99C10 Am99C10 TEXT
datasheet frame
Abstract: Command Register CAM Register CAM Word 0 48-bit Reg Compare with Mask Ü? Logic CAM Word 255 48-bit , Networks and many other applications. The Am99C10 Am99C10 CAM is composed of 256 words, each consisting of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10 Am99C10 is shown below. When data (the comparand) is , 2 t JJ CAM Word 48-bit Register I Skip Empty Bit Bit 48-bit Comparator A=B with Mask 7 i , exclu-sive-NOR comparator, an OR gate for masking, and a transistor for performing a 48-bit wire-AND across the ... OCR Scan
datasheet

28 pages,
922.21 Kb

Priority Encoder CAM AM99C10 BA9S cd 4028 CMOS 16-Bit Priority Encoder limit switch cam type ML0-ML255 08125-012A Am99C10 TEXT
datasheet frame
Abstract: Am99C1 OA 256 X 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS ■ 256 word x 48-bit , bridging applications ■ Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words ■ 48-bit input word compared against all 256 words In the CAM in a single , applications. The Am99C1 OA CAM is composed of 256 words, each consisting of a 48-bit comparator and a 48-bit , operation. When command write of Opcode 0 follows a second data write of the 48-bit data write sequence ... OCR Scan
datasheet

26 pages,
881.16 Kb

CD4028 block diagram of 7 segment AM99C10A AM99C1 FIFO CAM CMOS 16-Bit Priority Encoder TEXT
datasheet frame
Abstract: Am99C10 Am99C10 256 x 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS 256 word x 48-bit , bridging applications Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words 48-bit Input word compared against ail 256 words In the CAM in a single (100ns , Word 0 48-bit Reg T Compare with Mask - Ö Logic -MTCH « S D/C W CAM Word 255 -FULL I t LU m 'S Is !i CAM Register ie^sl 48-bit Rea S E è-1 ,Q - 1 £ 8 Z 3 T ... OCR Scan
datasheet

27 pages,
779.29 Kb

equivalent for transistor tt 2222 Am99ClO Priority Encoder CAM Am99C10 TEXT
datasheet frame
Abstract: Am99C10A Am99C10A 256 x 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS 256 word x 48-bit , technology - 880 mW max. operating power - 55 mW max. standby a Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words 48-bit input word , words, each consisting of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10A Am99C10A is , write of the 48-bit data write se quence, Opcode 0 must be preceded by Opcode F com mand write (Set ... OCR Scan
datasheet

26 pages,
881.16 Kb

Priority Encoder CAM CD4028 AM99C10A Am99C10A TEXT
datasheet frame

Archived Files

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Interface (OpenLDI) TQFP (VJD100A VJD100A) 100  Status   Full production DS90CR481VJD DS90CR481VJD 48-Bit production DS90CR481VJDX DS90CR481VJDX 48-Bit LVDS Channel Link Serializer - 65 - 112 MHz Channel Link TQFP (VJD100A VJD100A) 100  Status   Full production DS90CR482VS DS90CR482VS 48-Bit LVDS Channel Link Deserializer DS90CR482VSX DS90CR482VSX 48-Bit LVDS Channel Link Deserializer - 65 - 112 MHz Channel Link TQFP (VJD100A VJD100A) 100  Status   Full production DS90CR483VJD DS90CR483VJD 48-Bit Channel Link Serializer - 33-112MHz Channel
/datasheets/files/national/tqfp.html
National 25/09/2003 20.46 Kb HTML tqfp.html
14mm  1mm  Full production DS90CR481VJD DS90CR481VJD 48-Bit LVDS Channel Link Serializer - 65 - 112 MHz DS90CR481VJDX DS90CR481VJDX 48-Bit LVDS Channel Link Serializer - 65 - 112 MHz Channel Link TQFP (VJD100A VJD100A) 100  MSL   COPPER  14mm  14mm  1mm  Full production DS90CR482VS DS90CR482VS 48-Bit LVDS Channel Link Full production DS90CR482VSX DS90CR482VSX 48-Bit LVDS Channel Link Deserializer - 65 - 112 MHz Channel DS90CR483VJD DS90CR483VJD 48-Bit Channel Link Serializer - 33-112MHz Channel Link TQFP (VJD100A VJD100A) 100  MSL  
/datasheets/files/national/htm/nsc02429-v3.htm
National 16/08/2002 28.99 Kb HTM nsc02429-v3.htm
National P/N LM9823 LM9823 - 3 Channel 48-Bit Color Scanner Analog Front End   LM9823 LM9823  Product Folder 3 Channel 48-Bit Color Scanner Analog Front End     See Also:    LM9832 LM9832 - 16 bit (48 48-Bit Color Scanner Analog Front End 238 Kbytes 3-Oct-00 View Online Download Receive via Email LM9823 LM9823 3 Channel 48-Bit Color Scanner Analog Front End ( JAPANESE ) 726 Kbytes  
/datasheets/files/national/pf/lm9823.html
National 17/02/2005 10.06 Kb HTML lm9823.html
National P/N LM9823 LM9823 - 3 Channel 48-Bit Color Scanner Analog Front End   Products > Imaging > Analog Front End (AFE) > LM9823 LM9823 LM9823 LM9823  Product Folder 3 Channel 48-Bit Color Channel 48-Bit Color Scanner Analog Front End 238 Kbytes 3-Oct-00 View Online Download Receive via Email LM9823 LM9823 3 Channel 48-Bit Color Scanner Analog Front End ( JAPANESE ) 367
/datasheets/files/national/htm/nsc03548-v1.htm
National 16/08/2002 15.39 Kb HTM nsc03548-v1.htm
No abstract text available
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Xilinx 07/09/2004 12.39 Kb ZIP ug073_c07.zip
National P/N DS90CR481 DS90CR481 - 48-Bit LVDS Channel Link Serializer - 65 Link > DS90CR481 DS90CR481   DS90CR481 DS90CR481  Product Folder 48-Bit LVDS DS90CR481 DS90CR481 DS90CR482 DS90CR482 48-Bit LVDS Channel Link SER DES - 65 - 112 MHz 657 Kbytes 23-May-02 View Online Download Receive via Email DS90CR481 DS90CR481 DS90CR482 DS90CR482 48-Bit LVDS Channel Link SER DES - capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel
/datasheets/files/national/pf/ds90cr481.html
National 17/02/2005 12.43 Kb HTML ds90cr481.html
48-Bit LVDS Channel Link Serializer - 65 - 112 MHz Channel Link TQFP (VJD100A VJD100A) 100  MSL   Cu 7025  14mm  14mm  1mm  Full production DS90CR481VJDX DS90CR481VJDX 48-Bit LVDS Channel Link Full production DS90CR482VS DS90CR482VS 48-Bit LVDS Channel Link Deserializer - 65 - 112 MHz Channel DS90CR482VSX DS90CR482VSX 48-Bit LVDS Channel Link Deserializer - 65 - 112 MHz Channel Link TQFP (VJD100A VJD100A) 100  MSL   Cu 7025  14mm  14mm  1mm  Full production DS90CR483VJD DS90CR483VJD 48-Bit Channel Link
/datasheets/files/national/htm/nsc00957.htm
National 01/11/2002 29.6 Kb HTM nsc00957.htm
AMD - PCnet Family Developers Tools - Understanding 48-bit IEEE 48-bit IEEE Ethernet Addresses Supplement to Address Manager/EESETUP This Application Note describes the how's and why's of getting and stuffing your assigned 48-bit IEEE Physical Address (globaly) unique 48-bit physical address. Companies are therefore required to possess their own block(s) of and sends each requesting company a binary number representing the upper 24-bits of a 48-bit address.
/datasheets/files/amd/docs/wcd00002/wcd00221.htm
AMD 29/04/1999 9.53 Kb HTM wcd00221.htm
National P/N DS90CR483 DS90CR483 - 48-Bit Channel Link Serializer - 33-112MHz   Products > Analog - Interface > LVDS Circuits > Channel Link > DS90CR483 DS90CR483 DS90CR483 DS90CR483  Product Folder 48-Bit Channel Link Serializer - 33-112MHz Generic P/N Date View Online Download Receive via Email DS90CR483 DS90CR483 DS90CR484 DS90CR484 48-Bit LVDS rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With
/datasheets/files/national/htm/nsc01825-v5.htm
National 01/11/2002 17.36 Kb HTM nsc01825-v5.htm
DS90CR485 DS90CR485    133MHz LVDS 48-bit Channel Link Serializer  $12.90  evaluation board, TQFP   -10   70   2.50   3.3V   6384   133   48:8   Transmitter    DS90CR484 DS90CR484    48-Bit Channel :48   Receiver    DS90CR483 DS90CR483    48-Bit Channel Link Serializer - 33-112MHz  $11.00 DS90CR482 DS90CR482    48-Bit LVDS Channel Link Deserializer - 65 - 112 MHz  $11.00  TQFP   -10   70   3.30   -   5376   112   8:48   Receiver    DS90CR481 DS90CR481    48-Bit LVDS Channel Link
/datasheets/files/national/0,185241.htm
National 27/02/2004 22.91 Kb HTM 0,185241.htm