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CS48560-CQZR Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 30MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 visit Digikey
CS48560-DQZR Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 30MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 visit Digikey
CS48540-DQZR Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 30MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 visit Digikey
CS48540-CQZR Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 30MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 visit Digikey
CS48520-CQZR Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 30MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 visit Digikey
CS48520-CQZ Cirrus Logic Digital Signal Processor, 32-Bit Size, 0-Ext Bit, 27MHz, CMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-48 BUY

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48-bit

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: into the bit bucket. An ADSP-21160 2-Mbit block of memory that contains 48-bit instruction words can , single-precision IEEE floating-point data. 48-bit words contain either instructions or 40-bit extended-precision , data into the appropriate internal word width, either 64-bits, or 48-bits. Direct core accesses to , in internal memory. The 64-bit PM Data bus is used to transfer 48-bit instructions (and 64-bit, 40 , the DM data bus. This register also provides 40- and 48-bit data transfer support between the Analog Devices
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32Kx16bit 00000x4 00000x7 ADSP-21160- RND32
Abstract: PCM-4381 PCI-104 48-bit LVDS1 SATA2 SATA1 ATX/ AT Power USB3, 4 USB 5, 6 48-bit LVDS2 COM2, 3, 4 & , ® Pentium® M/ Celeron® M Processor on board/ Socket type Display combination: 48-bit LVDS1 + 48-bit LVDS2, CRT + 48-bit LVDS Dual 10/100/1000 Mbps Ethernet 16-bit GPIO, 4 COM (Supports Auto flow control), 2 , DVMT 3.0 supports up to 128 MB Mobile Intel GMA 900 3D/2D engine 1 x 48-bit LVDS1, 1 x 48-bit LVDS2 , ) 48-bit LVDS connector Chrontel 7308 48-bit LVDS Connector VGA Connector SDVO BUS DDR2 400/533 Advantech
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RTL8111B-GR VGA 15 PIN CABLE CONNECTION DIAGRAM LVDS 30 pin connector cable 910GMLE 915GME 910GMLE/
Abstract: 18-bit (i.e., DS90C365), 24-bit (i.e., DS90C385) and 24/48-bit (i.e., DS90C387) appli- cations , -bit (i.e., DS90C364A), 24-bit (i.e., DS90CF384A) and 48-bit (i.e., DS90CF388). These receivers sample the , Receiver Output Data Pin 24-bit 24-bit Tx 18-bit Tx 48-bit Tx (C385) (C365) (C387) 24-bit Rx 18-bit Rx 48-bit Rx (CF364A) (CF384A) (CF388) LSB 18-bit TFT Panel Data Signal R0 , -bit 24-bit Tx 18-bit Tx 48-bit Tx (C385) (C365) (C387) 24-bit Rx 18-bit Rx 48-bit Rx (CF364A National Semiconductor
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GE-4 TxIN10 GE-2 GE-1 C387 DS90C387/DS90CF388 AN-1127
Abstract: SRAM Total Size Block size (2) # of 48-bit words (per block) # of 32-bit words (per block) # of , -2106x processors. 32-bit memory words are used for single-precision IEEE floating-point data. 48-bit words , processor access the same block. Core Processor 32 x 48-Bit DAG 1 PROGRAM SEQUENCER DAG 2 , controller automatically packs external data into the appropriate word width, either 48-bit instructions or , combinations of 48-bit instruction words and 32-bit data words. Maximum efficiency (i.e. single-cycle Analog Devices
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ADSP-21060 ADSP-21062 ADSP-21061 blocks in memory organization 8kx16bit 0x0002 fast page mode dram controller ADSP-2106X ADSP-2106
Abstract: are available for 18-bit (i.e., DS90C365), 24-bit (i.e., DS90C385) and 24/48-bit (i.e., DS90C387 , available in 18-bit (i.e., DS90C364A), 24-bit (i.e., DS90CF384A) and 48-bit (i.e., DS90CF388). These , -bit 18-bit 48-bit Rx Rx Rx (CF384A) (CF364A) (CF388) 24-bit Tx (C385) 48-bit Tx (C387 , Output Data Pin 18-bit Tx (C365) 24-bit 18-bit 48-bit Rx Rx Rx (CF384A) (CF364A) (CF388) 24-bit Tx (C385) 48-bit Tx (C387) TFT Panel Data Signal B0 Txin16 B16 Rxout16 National Semiconductor
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rgb 18 bit to lvds ds90C364 HSYNC, VSYNC, DE, input, output C385 C365
Abstract: . · Applications to configure memory to store 16-, 32-, 40-, or 48-bit words or combinations of these. The processor uses 32-bit memory words for single-precision IEEE floating-point data and 48-bit words , (PMD) bus, a 48-bit transmission path. Controlled by the processor's core, the PM bus provides a , for passing data between the 48-bit PM bus and the 40-bit DM bus or the 40-bit Register File , processor's core can access as one 48-bit register or as two separate registers, one 16-bit register (PX1 Analog Devices
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ADSP-21065L pin diagram for core i7 processor addressing mode in core i7 sec memory 32 pin pm47-32 px270 EPD controller
Abstract: Data (0) 1st Data (0) 48th Data (0) SCLK Signal (Internal in 1st Device) 48-Bit Shift , ) 1st Data (0) 2nd Data (0) 3rd Data (1) 5th Data (1) 48-Bit Shift Register LSB+1 (Internal in 1st Device) 4th Data (1) 48-Bit Shift Register MSB-1 (Internal in 1st Device) 47th Data , ) 1st Data (0) 1st Data (0) 2nd Data (0) 2nd Data (0) 48-Bit Shift Register MSB (Internal , tWO SDO tF0 tR0 SCLK Signal (Internal in 2nd Device) 48-Bit Shift Register LSB (Internal Texas Instruments
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SDI-12 circuit TLC5973 SBVS225 12-MH ISO/TS16949
Abstract: (Internal in 1st Device) 48-Bit Shift Register LSB (Internal in 1st Device) 48-Bit Shift Register LSB+1 (Internal in 1st Device) 48-Bit Shift Register MSB-1 (Internal in 1st Device) 48-Bit Shift Register MSB , New GS Data SDO tF0 SCLK Signal (Internal in 2nd Device) 48-Bit Shift Register LSB (Internal in 2nd , Generator MSB 48-Bit Shift Register 47 Upper 8 Bits Lower 36 Bits Command Decoder (3AAh) SDO LSB gslat , CONFIGURATION The TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the Texas Instruments
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SBVS225A
Abstract: consists of 48-bit shift register. 48-bit latch and 48-bit LCD driver. The display data, which was input to the 48-bit shift register, is shifted to the 48-bit latch by the LOAD signal. Then the data is output to the LCD panel through the 48-bit LCD driver. FEATURES â'¢ 48 dots static LCD driving capability , Self/External oscillation â  i r A. Joscl gndÃ'- LCD Driver & E-OR 48-bit Data Latch 48-bit , signal and CLOCK signal. It is transferred to the 48-bit latch by the LOAD signal and it is output to -
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MSM5219B MSM5219BGS 48-dot 7 pin connection lcd wire lcd 60 pin lcd 60-pin 48-DOT QFP60-P-1519-K DFP60-P-1519-VK SEG32
Abstract: consists of 48-bit shift register. 48-bit latch and 48-bit LCD driver. The display data, which was input to the 48-bit shift register, is shifted to the 48-bit latch by the LOAD signal. Then the data is output to the LCD panel through the 48-bit LCD driver. FEATURES â'¢ 48 dots static LCD driving capability , LCD Driver & E-OR T2 48-bit Data Latch â  A S 48-bit Shift Register Seif/External oscillation , signal. It is transferred to the 48-bit latch by the LOAD signal and it is output to the LCD panel -
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SEG23 MSM5219 msm5219bg QFP60-P-1519-VK SEG30 SEG28 SEG26 SEG24
Abstract: Am99C10A 256 x 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS 256 word x 48-bit , technology - 880 mW max. operating power - 55 mW max. standby a Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words 48-bit input word , words, each consisting of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10A is , write of the 48-bit data write se quence, Opcode 0 must be preceded by Opcode F com mand write (Set -
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CD4028 Priority Encoder CAM 99C10A KS000010 08125-009B 08125-010B
Abstract: : ftp.analog.com, WEB: www.analog.com/dsp Executing Code Directly From 8, 16, 32, or 48-bit External Memory , -bits, it can directly execute instructions (48bit opcodes) from external memories of four different widths: 8-bits, 16-bits, 32-bits, and 48-bits. With this new flexibility, the DSP engineer now has a , execution from 48-bit wide memory at the full core clock rate (100 MHz); or if cost is the overriding , the 21161N EZ-Kit to experiment with this feature? multiple external words into a single 48-bit Analog Devices
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ADSP-21161N ADSP21161N ADSP21161 256kwords EE-69 EE137 EE-137
Abstract: : ftp.analog.com, WEB: www.analog.com/dsp Executing Code Directly From 8, 16, 32, or 48-bit External Memory , -bits, it can directly execute instructions (48bit opcodes) from external memories of four different widths: 8-bits, 16-bits, 32-bits, and 48-bits. With this new flexibility, the DSP engineer now has a , execution from 48-bit wide memory at the full core clock rate (100 MHz); or if cost is the overriding , CoreSpeed 2 CoreSpeed 2 x (# waitstates) 48-bit . . . . Table-1. External Execution Analog Devices
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256K-words EE-132 eprom ram 512k x 16 bits
Abstract: 97SD3248 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: · 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks) · RAD-PAK® radiation-hardened , Technologies All rights reserved. 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM 97SD3248 Vcc Vss NC CKE6 , All rights reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM ` TABLE 1. ABSOLUTE , without notice 3 ©2005 Maxwell Technologies All rights reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit Maxwell Technologies
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AX12 MIL-PRF-38535
Abstract: August 2004 ASM4SSTVF32852 rev 2.0 DDR 24-Bit to 48-Bit Registered Buffer Features To , , when coming out of low power standby state, the register will Product Description The 24-Bit to 48-Bit , W 114-Pin Ball BGA DDR 24-Bit to 48-Bit Registered Buffer 2 of 13 August 2004 , Input reference, 1.25V nominal. DDR 24-Bit to 48-Bit Registered Buffer 3 of 13 August 2004 , D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 DDR 24-Bit to 48-Bit Alliance Semiconductor
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ASM4SSTVF16857 ASM4SSTVF16859 ASM5CVF857 Q13A
Abstract: 97SD3248 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: â'¢ 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks) â'¢ RAD-PAK® radiation-hardened , notice 1 ©2006 Maxwell Technologies All rights reserved. 1.5Gb (8-Meg X 48-Bit X 4 , notice 2 ©2006 Maxwell Technologies All rights reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4 , reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM TABLE 4. DC ELECTRICAL CHARACTERISTICS Maxwell Technologies
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Abstract: 97SD3248 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: · 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks) · RAD-PAK® radiation-hardened , reserved. 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM 97SD3248 Vcc Vss NC CKE6 CKE5 CKE4 CKE3 , reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM ` TABLE 1. ABSOLUTE MAXIMUM RATINGS , without notice 3 ©2004 Maxwell Technologies All rights reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit Maxwell Technologies
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Abstract: 97SD3248B 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: â'¢ 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks) â'¢ RAD-PAK® radiation-hardened , Maxwell Technologies All rights reserved. 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM 97SD3248B Vcc , 2 ©2013 Maxwell Technologies All rights reserved. 97SD3248B 1.5Gb (8-Meg X 48-Bit X 4 , without notice 3 ©2013 Maxwell Technologies All rights reserved. 97SD3248B 1.5Gb (8-Meg X 48-Bit Space Electronics
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Abstract: 97SD3248 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks Logic Diagram (One Amplifier) Memory FEATURES: DESCRIPTION: â'¢ 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks) â'¢ RAD-PAK® radiation-hardened , notice 1 ©2006 Maxwell Technologies All rights reserved. 1.5Gb (8-Meg X 48-Bit X 4 , notice 2 ©2006 Maxwell Technologies All rights reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4 , reserved. 97SD3248 1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM TABLE 4. DC ELECTRICAL CHARACTERISTICS Maxwell Technologies
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Abstract: â  256word x 48-bit Content Addressable Memory (CAM) â  - Optimized for Address Decoding , capability through user programmable control logic Each CAM word has a 48-blt register and 48-bit ,   48-bit input word compared against all 256 words In the CAM In a single cycle â  â , of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10A is shown below. When , Comparand Register 1 CAM Word 0 â'˜ t > 48-bitR egT M ask Reg ister I S| E ± Compare -
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DS5752
Abstract: CHARACTERISTICS â  256 word x 48-bit Content Addressable Memory (CAM) - Optimized for Address Decoding in , 48-bit maskable comparator - Maskable-bits and maskable-words â  48-blt input word compared , DIAGRAM D,5 -Do â +Comparand Register Command Register CAM Word 0 48-bit Reg Mask Register , _ CAM Word 255 O -J j? CD Q w - 48-bit Reg Compare with Mask o Logic r Status , and many other applications. The Am99C10 CAM is composed of 256 words, each consisting of a 48-bit -
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99C10 06837C
Abstract: Command Register CAM Register CAM Word 0 48-bit Reg Compare with Mask Ã? Logic CAM Word 255 48-bit , of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10 is shown below. When , : ML0-ML255. 3 2 t JJ CAM Word 48-bit Register I Skip Empty Bit Bit 48-bit Comparator A=B with Mask 7 , , an exclu-sive-NOR comparator, an OR gate for masking, and a transistor for performing a 48-bit , register. 48-bit Data Transfers Data is transferred to and from the Am99C10 in 16-bit words. Data for the -
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BA9876543210 BA9S cd 4028 06971C WCP-10M-
Abstract: Command Register CAM Register CAM Word 0 48-bit Reg Compare with Mask Ã? Logic CAM Word 255 48-bit , Networks and many other applications. The Am99C10 CAM is composed of 256 words, each consisting of a 48-bit comparator and a 48-bit register. A block diagram of the Am99C10 is shown below. When data (the comparand) is , 2 t JJ CAM Word 48-bit Register I Skip Empty Bit Bit 48-bit Comparator A=B with Mask 7 i , exclu-sive-NOR comparator, an OR gate for masking, and a transistor for performing a 48-bit wire-AND across the -
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08125-012A limit switch cam type gc227 CMOS 16-Bit Priority Encoder
Abstract: Am99C1 OA 256 X 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS â  256 word x 48-bit , bridging applications â  Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words â  48-bit input word compared against all 256 words In the CAM in a single , applications. The Am99C1 OA CAM is composed of 256 words, each consisting of a 48-bit comparator and a 48-bit , operation. When command write of Opcode 0 follows a second data write of the 48-bit data write sequence -
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FIFO CAM AM99C1 block diagram of 7 segment D16-3V
Abstract: Am99C10 256 x 48 Content Addressable Memory DISTINCTIVE CHARACTERISTICS 256 word x 48-bit , bridging applications Each CAM word has a 48-bit register and 48-bit maskable comparator - Maskable-bits and maskable-words 48-bit Input word compared against ail 256 words In the CAM in a single (100ns , Word 0 48-bit Reg T Compare with Mask - Ö Logic -MTCH « S D/C W CAM Word 255 -FULL I t LU m 'S Is !i CAM Register ie^sl 48-bit Rea S E è-1 ,Q - 1 £ 8 Z 3 T -
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Am99ClO equivalent for transistor tt 2222 D32-47
Abstract: p iC-MD 48-BIT QUADRATURE COUNTER reliminary WITH RS422 RECEIVER AND SPI/BISS INTERFACE Rev A3 , http://www.ichaus.com p iC-MD 48-BIT QUADRATURE COUNTER reliminary WITH RS422 RECEIVER AND SPI , www.biss-interface.com/bua p iC-MD 48-BIT QUADRATURE COUNTER reliminary WITH RS422 RECEIVER AND SPI/BISS INTERFACE , Touch Probe Input p iC-MD 48-BIT QUADRATURE COUNTER reliminary WITH RS422 RECEIVER AND SPI/BISS , Typ. Max. 125 ºC p iC-MD 48-BIT QUADRATURE COUNTER reliminary WITH RS422 RECEIVER AND SPI iC-Haus
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RS-422/TTL TSSOP20 D-55294
Abstract: CHARACTERISTICS 256 word x 48-bit Content Addressable Memory (CAM) - Optimized for Address Decoding in Local , Each CAM word has a 48-blt register and 48-bit maskable comparator - Maskable-bits and maskable-words , Am99C10A CAM is composed of 256 words, each consisting of a 48-bit comparator and a 48-bit register. A , masking, and a transistor for performing a 48-bit wire-AND across the 48 data bits, as shown in Figure 2 . , write of the 48-bit data write se quence, Opcode 0 must be preceded by Opcode F com mand write (Set -
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