NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| MAX6430NSUS+ | Maxim Integrated Products | Low-Power, Single/Dual-Level Battery Monitors with Hysteresis | 
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| MAX6430NSUS | Maxim Integrated Products | Low-Power, Single/Dual-Level Battery Monitors with Hysteresis |
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| MAX6430NSUS+T | Maxim Integrated Products | IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4, SOT-143, 4 PIN, Power Management Circuit |
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| MAX6430NSUS-T | Maxim Integrated Products | IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4, SOT-143, 4 PIN, Power Management Circuit |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: AVo63 /"^ CS / / dB H :50V/jU s #-te I- y ;/ V - y -f A:430ns (10V + 0.1%) •®«®EÍ5H:±2.5~± 15V -t t¡ y H ... | OCR Scan |
1 pages, |
LT1200 LT1200C LT1200 abstract |
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| Abstract: OUT S t CS COMP 0.5V pfm LEB Delay 430ns pfm_d COMP 0.46V VDD I Tons , the sense-resistor. To avoid falsetermination of the switching pulse, a 430ns leadingedge blanking is ... | Original |
10 pages, |
SOT-23 IP GA1703 sot-235 Marking c1 GA3703 GA1703 abstract |
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| Abstract: 3.50ns 3.10ns 1.60ns Rise Time 4.20ns 4.10ns 4.30ns 3.20ns 1.70ns 960ps ... | Original |
4 pages, |
ALVCH16244 ALVCH16244 abstract |
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| Abstract: Driver Q OUT Vea S t CS COMP 0.5V pfm LEB Delay 430ns pfm_d COMP 0.46V , pulse, a 430ns leadingedge blanking is built in. During this blanking period, the current sense ... | Original |
11 pages, |
GA1706 flyback ac charger AP3706 GA1706 abstract |
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| Abstract: Q CV_ctrl pfm 1 OUT Driver S t CS COMP 0.5V pfm LEB Delay 430ns , falsetermination of the switching pulse, a 430ns leadingedge blanking is built in. During this blanking period ... | Original |
11 pages, |
IC LM 324 SOT-23 IP AP3703 AP3703 abstract |
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| Abstract: 1 Driver OUT S t CS COMP 0.5V pfm LEB Delay 430ns pfm_d COMP 0.46V , the sense-resistor. To avoid falsetermination of the switching pulse, a 430ns leadingedge blanking is ... | Original |
11 pages, |
AP3703 AP3703 abstract |
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| Abstract: Q CV_ctrl pfm 1 OUT Driver S t CS COMP 0.5V pfm LEB Delay 430ns , falsetermination of the switching pulse, a 430ns leadingedge blanking is built in. During this blanking period ... | Original |
11 pages, |
AP3703 AP3703 abstract |
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| Abstract: pfm Driver OUT Vea S 1 t CS COMP 0.5V pfm LEB Delay 430ns pfm_d COMP , of the switching pulse, a 430ns leadingedge blanking is built in. During this blanking period, the ... | Original |
13 pages, |
mobile battery AP3706MTR-E1 AP3706P AP3706P-E1 IC LM 324 3706M application AP3706 3706m-e1 AP3706M-E1 AP3706P-G1 3706M 265VAC AP3706 abstract |
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| Abstract: pfm Q Driver OUT Vea S CS 5 t COMP 0.5V pfm LEB Delay 430ns pfm_d , sense-resistor. To avoid falsetermination of the switching pulse, a 430ns leadingedge blanking is built in. During ... | Original |
12 pages, |
IC LM 324 AP3705M-G1 AP3705 3705M-G1 3705M AP3705 abstract |
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| Abstract: COMP 0.5V pfm LEB Delay 430ns pfm_d COMP VDD 0.46V I Tons 3.75V COMP R Q , will occur on the sense-resistor. To avoid falsetermination of the switching pulse, a 430ns leadingedge ... | Original |
13 pages, |
IC LM 324 AP3708N 3708nm AP3708 AP3708N abstract |
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| Abstract: -218- 501 2B Hex Non Inverting 3 State Buffer »iG> INs I 1»3 (S> IN4 ©- i aae m *m iss 3Xt- f- Httl 5: t PRC ii7r HSffllR DISABLE INPUT INPUT OUTPUT L L L L H H H * HZ *> : Don' HZ: High Care Impedance VDD typ -ax a « niT-. tr 5V 130 400 ns DIP SOI 10V G5 200 ns if 15V 50 100 ns tf 5V 70 200 ns JRC 10V 40 100 ns * TC5012BP TC5012BP • « 15V 35 80 ns H* tPLH (IN -> OUT ) 5V 320 430 ns B4 10V 150 220 ns *+a 15V 110 200 ns BfF tPHL (I* -> ... | OCR Scan |
1 pages, |
TC5012BP datasheet abstract |
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| Abstract: - 152 4506B 4506B Dual Expandable AOI Gate - -i -I • f -< -y ^ A - m f-Y SS AO I Ai» 4 2 1/3- 5 7 h tcl - DO " ' ... | OCR Scan |
1 pages, |
HD14506B 4506B MC14506B 4506B abstract |
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| Abstract: HVIC M81700FP M81700FP M 8 1 7 0 0 F P 6 0 0 V I G B T / MOSFET LO 1 NC 15 GND VCC 3 14 LIN NC 4 13 SD NC 5 12 HIN VS 6 11 VDD VB 7 10 NC HO 8 HID ACIGBT/MOSFET 16 LGND 2 ¡ 600V ¡ ±2A ¡ ¡16SOP 16SOP 9 NC 16P2N 16P2N NC 7 VDD HIN 11 12 SD 13 LIN 14 GND 15 VDD/VCC LEVEL SHIFT S VDD/VCC LEVEL SHIFT VDD/VCC LEVEL SHIFT 8 HO 3 VS VCC ... | Original |
6 pages, |
M81700FP 16P2N 16SOP M81700FP abstract |
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| Abstract: Anti-Aliasing and Reconstruction TFT range YUV COMPONENT SAMPLING These very small, low cost filters are intended for use with A-D and D-A video converters where some deviation from full ITU-R BT601 BT601 standard can be tolerated, ie single pass applications. These filters are designed for use in 4:2:2 sampling systems, ie 13.5 MHz for the luminance (Y) channel and 6.75 MHz for the chrominance (U and V) channels. · Ideal for single pass or monitor outputs · Choice of package format to suit ... | Original |
2 pages, |
TFT1350S TFT1350F TFT0675F filter lowpass 430 MHz DR00008B BT601 BT601 abstract |
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| Abstract: GFG SERIES ANTIALIASING FILTERS These very small, low cost, filters are intended for use with A-D and D-A video converters where some deviation from full multicodec standards is allowed. The cut off rate is slower than recommended to reduce time domain ringing. The filters are designed for use in systems adhering to the EBU standard for 4:2:2 A-D and D-A conversion i.e. sampling rates of 13.5 MHz for the luminance (Y) channel and 6.75 MHz for the chrominance (U and V) channels. The pre-fi ... | Original |
2 pages, |
GFG1350S GFG1350F GFG0675S GFG0675F DR00008B datasheet abstract |
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| Abstract: Anti-Aliasing and Reconstruction TFT range YUV COMPONENT SAMPLING These very small, low cost filters are intended for use with A-D and D-A video converters where some deviation from full ITU-R BT601 BT601 standard can be tolerated, ie single pass applications. These filters are designed for use in 4:2:2 sampling systems, ie 13.5 MHz for the luminance (Y) channel and 6.75 MHz for the chrominance (U and V) channels. · Ideal for single pass or monitor outputs · Choice of package format to suit ... | Original |
2 pages, |
TFT1350S TFT0675F DR00008B BT601 TFT1350F BT601 abstract |
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| Abstract: No. N 2 9 3 6 A SB007W03C SB007W03C No. N 2 9 3 6 A D2000 D2000 No.2936 SB007W03C SB007W03C 30V70mA , , VF max=0.55V trr max=10ns Absolute Maximum Ratings / Ta=251 VRRM IO IFSM 35 V 70 2 mA A - 55 125 - 55 125 Tj Tstg unit V min max unit 0.55 V V VRSM 30 50Hz 1 Electrical Characteristics / Ta=251 VR VF IR=20uA IF=70mA IR C typ 30 VR=15V VR=10V, f=1MH ... | Original |
3 pages, |
SB007W03C D2000 SB007W03C abstract |
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| Abstract: MILITARY DATA SHEET Original Creation Date: 11/30/95 Last Update Date: 01/30/96 Last Major Revision Date: 11/30/95 MNLM760-X MNLM760-X REV 1A0 HIGH SPEED DIFFERENTIAL COMPARATOR General Description The LM760 LM760 is a differential voltage comparator offering considerable speed improvement over the LM710 LM710 family and operates from symmetric supplies of +4.5V to +6.5V. The LM760 LM760 can be used in high speed analog-to-digital conversion systems and as a zero crossing detector in disc file and tape amplif ... | Original |
8 pages, |
LM760J/883 LM760H/883 LM760 LM710 lm776 MNLM760-X MNLM760-X abstract |
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| Abstract: Anti-Aliasing and Reconstruction TFT range YUV COMPONENT SAMPLING These very small, low cost filters are intended for use with A-D and D-A video converters where some deviation from full ITU-R BT601 BT601 standard can be tolerated, ie single pass applications. These filters are designed for use in 4:2:2 sampling systems, ie 13.5 MHz for the luminance (Y) channel and 6.75 MHz for the chrominance (U and V) channels. · Ideal for single pass or monitor outputs · Choice of package format to suit ... | Original |
2 pages, |
TFT1350S TFT1350F TFT0675F DR00008B BT601 BT601 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| NA 6 5 NA .530ns .430ns .630ns 9 7 NA .530ns .430ns .630ns 11 10 NA .530ns .430ns .630ns 13 12 NA .530ns .430ns .630ns 16 14 NA .530ns .430ns .630ns 18 17 NA .530ns .430ns .630ns 20 19 NA .530ns .430ns .630ns 23 21 NA .530ns .430ns .630ns 25 24 NA .530ns .430ns .630ns www.datasheetarchive.com/files/on_semiconductor/simulation-models/mc10e111fn_50.ibs |
On Semiconductor | 24/07/2011 | 6.78 Kb | IBS | mc10e111fn_50.ibs |
| XDelay: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:57:06 1994 XDelay Report File: Design: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB16H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:57:06 1994 XDelay Report File: Design: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB16H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:57:06 1994 XDelay Report File: Design: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB16H.XRP) |
Xilinx | 09/04/1997 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:57:06 1994 XDelay Report File: Design: CLDB16H CLDB16H CLDB16H CLDB16H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/49705392-987186ZC/wcd02ec8.zip (CLDB16H.XRP) |
Xilinx | 13/07/1998 | 193.16 Kb | ZIP | wcd02ec8.zip |
| XDelay: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:58:09 1994 XDelay Report File: Design: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB20H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB24H CLDB24H CLDB24H CLDB24H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:59:34 1994 XDelay Report File: Design: CLDB24H CLDB24H CLDB24H CLDB24H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB24H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:58:09 1994 XDelay Report File: Design: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB20H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB24H CLDB24H CLDB24H CLDB24H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:59:34 1994 XDelay Report File: Design: CLDB24H CLDB24H CLDB24H CLDB24H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB24H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:58:09 1994 XDelay Report File: Design: CLDB20H CLDB20H CLDB20H CLDB20H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB20H.XRP) |
Xilinx | 09/04/1997 | 193.16 Kb | ZIP | xapp002v.zip |