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Part Manufacturer Description Datasheet BUY
TPS54116QRTWRQ1 Texas Instruments Automotive DDR Power Solution with 4-A, 2-MHz VDDQ DC/DC Converter, 1-A VTT LDO and VTTREF 24-WQFN -40 to 125 visit Texas Instruments Buy
GC4116-PB-ASY Texas Instruments SPECIALTY TELECOM CIRCUIT, PBGA160, 15 X 15 MM, PLASTIC, BGA-160 visit Texas Instruments
TPS54116QRTWTQ1 Texas Instruments Automotive DDR Power Solution with 4-A, 2-MHz VDDQ DC/DC Converter, 1-A VTT LDO and VTTREF 24-WQFN -40 to 125 visit Texas Instruments
SN74116N3 Texas Instruments Dual 4-bit D-type latches with clear 24-PDIP 0 to 70 visit Texas Instruments
GC4116-PBZ Texas Instruments 4 Channel Narrowband DUC 160-BGA -40 to 85 visit Texas Instruments
SN74116N Texas Instruments Dual 4-bit D-type latches with clear 24-PDIP 0 to 70 visit Texas Instruments

4116 DRAM

Catalog Datasheet MFG & Type PDF Document Tags

information applikation

Abstract: U880D k t s n o n i k Heft 30: HALBLEITERSPEICHER Teil 2 SRAM und DRAM v e b halbleiterw , Inhetliebnahme/ Nachnutzung 28 7«.2t4,?* Dynamische Sehreib-/Lese-Speicher (DRAM) Grundlagen. Prinzip der dynamischen Speicherzelle 8.1.1. 8.1.2. Aufbau von DRAM - Schaltkreisen Funktionsweise und Betriebsarten von DRAM's 8.1.38.1.3.1. Adressierung 8.1.3.2. Betriebsarten 8.1.3.3. Datenausgang 8. 8.1. 31 31 31 33 34 34 35 37 38 33 Biographie wichtiger DRAM - Typen. T J 256 C/D Kurzcharakteristik Schaltbild
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PF8681

Abstract: OM1016 Corporation PO Box 275 17 Model Ave Hopewell New Jersey 08525 USA Tel. Fax +001 609 466 1751 +001 609 466 4116 , -BASED SYSTEMS OM4160 Microcore-1 dem onstration/evaluation board: SCC68070, 128K EPROM, 512K DRAM, l2C, RS
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OM1022 OM5027 PF8681 OM1016 pm3580 OM1018 ICA-90 OM4151 68000-BASED RS-232C

MCD270

Abstract: MCD251 Shadowing . 4 MByte DRAM Direct Drive (256K x 4, 1M x 4, and 256K x 16 DRAM Types Supported) · Up to 768 x , memory and provides chip-select signals for system ROM and peripherals. The on-chip DRAM controller can support up to 4 MByte of DRAM and controls access to the unspecialized System or Video DRAM. The CPU can , the Video DRAM. Each channel has a Real Time file decoder permitting the display of normal, runlength , P IN DESCRIPTION JTA6 TEST INTERFACE VIDEO INTERFACE DRAM INTERFACE IO PIN
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MCD212 MCD270 MCD251 4116 Dram MCD212/D MCD211 680X0 MCD214 MCD211/212

4116 DRAM

Abstract: 1/DRAM 4116 [M IC R O N 512K X 32, 1 MEG x MT16D(T)51232 16 DRAM MODULE DRAM _ MODULE _ _ Ä , standby current, 3.2^A maximum (L-version) · Thin outline using TSOP version DRAM MODULE M T 1 6 D , X MT16D(T)51232 32, 1 MEG x 16 DRAM MODULE correct state by maintaining power and executing , memory organization. FUNCTIONAL B LO C K DIAGRAM DRAM MODULE U1-U16 = MT4C4256 U M J16 = MT4C4256 , 16 DRAM MODULE ADDRESSES FUNCTION RAS ÜÄ!f WF *R 'C DATA-IN/OUT DQ1-DQ32 Standby READ
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1/DRAM 4116 S1232 51232 dram 4116 DE-10 DE-25 125US

MCD214

Abstract: 1/DRAM 4116 , Including ROM Shadowing 4 MByte DRAM Direct Drive (256K x 4, 1M x 4, and 256K x 16 DRAM Types Supported) Up , occurred. MCD214 will only operate with 4- bit DRAM, or with 16-bit DRAM chips with two CAS inputs and one , using 68000/6 8070-16 or 68340/3 41-16 series processors, tie DTACKSEL low; for 68340/341 - 2 5 designs , line outputs for DRAM control. Bidirectional M emory Data bus, thre e-state. Used to transfer data between DRAM bus and the M CD214. Stable when W R is asserted during a write cycle. Driven by the M CD214
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MCD214/D 160-P CD214FU
Abstract: MT16D(T)51232 32, 1 MEG x 16 DRAM MODULE 512 K x 32,1 MEG X 16 DRAM MODULE FAST-PAGE-MODE , . DRAM MODULE OPTIONS 72-Pin SIMM (DE-10) SOJ Version (DE-25) TSOP Version MICRON , . b 111S 4 ^ DDQÃ022 SST â  MRN X MT16D(T)51232 32,1 MEG x 16 DRAM MODULE For x l6 , organization. FUNCTIONAL BLOCK DIAGRAM DRAM MODULE 4 -1 1 4 MICRON SEMICONDUCTOR INC MICRON b3E D 512K X â  32, 1 MEG x 0006053 H T b _ M H R N MT16D(T)51232 16 DRAM MODULE -
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8051 using I2C BUS

Abstract: rs232 to I2c version 2.6 I2C PLL version 2.3 I2C CELL Tel.+1 609 466 1751 Fax+1 609 466 4116 version , -BASED SYSTEMS OM4160 Microcore-1 demonstration/evaluation board: SCC68070, 128K EPROM, 512K DRAM, I2C, RS
Philips Semiconductors
Original
SCC66470 8051 using I2C BUS rs232 to I2c Users guide to I2C-bus control programs I2C Printer Port Adapter philips 8051 i2c s87c00ksd MIIC-101 OM527 80C51-BASED PDS51 OM4160/3

93BIY

Abstract: mt4c4256 883c M IC R O N 512K X 32, 1 MEG x MT16D(T)51232 16 DRAM MODULE DRAM _ MODULE IV IV L , MICRON B StMICONlJUCTOH IN C 512K X 32, 1 MEG x MT16D(T)51232 16 DRAM MODULE correct , |IC=r o N 512K X 32, 1 MEG x MT16D(T)51232 16 DRAM MODULE TRUTH TABLE ADDRESSES , 16 DRAM MODULE ABSOLUTE MAXIMUM RATINGS* Voltage on V cc Supply Relative to V s s . , |CC7 3.2 3.2 3.2 mA 24 4-116 Micron Semiconductor, Inc. reserves the nght to
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93BIY mt4c4256 883c

IPC 4104

Abstract: 4116 DRAM 4.4 Graphics DRAM Controller registers CR3C - DRAM Timing Parameter register CR3D-DRAM Arbitration , 4.6.2 4.6.3 4.6.4 4.6.5 Host DRAM controller registers DRAM Bank 0 register DRAM Bank 1 register DRAM Bank 2 register DRAM Bank 3 register Memory Bank Width DRAM Bank 0 Timing Parameter register Graphics memory size register Memory Type register DRAM Bank 1 Timing Parameter register DRAM Refresh DRAM Bank 2 Timing Parameter register DRAM Bank 3 Timing Parameter register ADPC PCI related
STMicroelectronics
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IPC 4104 C 4751-1 0X094 0x00000001 0x10-0x13 dram 4164

TMS9900

Abstract: OZ 9930 .3-1 3.1.3 VDP to DRAM Address Connections , . .2~25 3-1 VDP to DRAM Address Connections , selects 4027 RAM operation 1 selects 4108/4116 RAM operation BIT 1 BLANK enable/disable 0 causes the
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TMS9900 OZ 9930 pal 007c TMS9929 oloa 8888 oloa 8888 LUBRICANT TMS9918A/TMS9928A/TMS9929A TMS4116 4116-XX MP010A
Abstract: i s m 256K X 16 FPM DRAM W03.pm5 - ftev.3/97 UNITS ns ns ns DG11SSG 4-116 MIN 35 , 256KX 16 FPM DRAM (MICRON M T 4 C 16257 DRAM FEATURES PIN ASSIGNMENT (Top View) â , products or specifications wlttiout notice. ©1997, Micron Technology, Inc. F M DRAM P OPTIONS 40-Pin SOJ (DA-6) P IIC n O N 256K X 16 FPM DRAM FUNCTIONAL BLOCK DIAGRAM F M DRAM P , specifications withoul notice. ©1997, Micron Techrwlogy, Inc. 2 5 6 K X 16 FPM DRAM (MICRON FUNCTIONAL -
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MT4C16257DJ-6 MT4C16257
Abstract: MEG x 36, 4 MEG x 18 IC DRAM CARD MICRON B SSE TECKNOlOC'MMC IC DRAM CARD 8 MEGABYTES , PCMCIA standard 88-pin IC DRAM card â'¢ Polarized receptacle connector â'¢ Industry standard DRAM , megabyte, IC DRAM card organized as a 2 Meg x 36 bit memory array. It may also be configured as a 4 Meg x , BACKUP (BBU) cycle refresh; a very low current, data retention mode. Standard component DRAM refresh , MT24D88C236 36, 4 MEG x 18 1C DRAM CARD FUNCTIONAL BLOCK DIAGRAM T -4 6 -2 3 - Ili DQ35 NEWJ -
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jeida dram 88 pin

Abstract: sm 4109 (V /IIC R O N MT24D88C236 2 MEG x 36, 4 MEG x 18 IC DRAM CARD IC DRAM CARD FEATURES · JEIDA, JEDEC and PCMCIA standard 88-pin IC DRAM card · Polarized receptacle connector · Industry standard DRAM , access MARKING -6 -7 -8 GENERAL DESCRIPTION The MT24D88C236 is an 8 m egabyte, IC DRAM card , very low current, data retention mode. Standard component DRAM refresh m odes are supported as well , thB right to change protfcjcts w 4-107 |V|CRON MT24D88C236 2 MEG x 36, 4 MEG x 18 IC DRAM
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jeida dram 88 pin sm 4109 dram card 60 pin MT24D

32T200

Abstract: 4116 Dram available on this device for greater system flexibility. MCM32230«MCM32T200 4-116 MOTOROLA DRAM RA , 32 Bit Dynamic Random Access Memory Module The MCM32230 is a 64M dynamic random access memory (DRAM , on a substrate along with a 0.22 nF (min) decoupling capacitor mounted under each DRAM. The , 69 70 7 1 72 Name DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS REV 3 10/95 MOTOROLA DRAM , MOTOROLA DRAM A B S O L U T E MAXIMUM RA TIN G S Rating P o w e r S u p p ly Voltage Voltage R e la
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32T200 MCM54400AN MCM32230-60 MCM32230-70 32T200SH

VL82C202

Abstract: VL82C202-16QC feature allows up to 384K-bytes of memory space to be copied to and executed out of high speed DRAM , active high output used to enable the Row Address Strobe to DRAM banks 0 and 3. An active high output used to enable the Row Address Strobe to DRAM banks 1 and 2. An active high output used to enable the Column Address Strobe to DRAM banks 0 and 2. An active high output used to enable the Column Address Strobe to DRAM banks 1 and 3. Lower Megabyte Chip Select - An active low output that indicates that the
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VL82C202 VL82C202-16QC TI 4116 dram CS8042 VL82C2 512K- 384K- VL82C202-16QI VL82C202-20QC

ic 74ls245

Abstract: PAL22V10-25 SRAM EEPROM DRAM Slave QUICC DRAM Controller 21 21 21 21 21 21 21 22 22 22 23 23 23 , 4.11.5 M68360QUADS-040 Status Register 4.11.5.1 Status Register Bits Description 4.11.6 Ethernet , Memory Map DRAM SIMM Types Port A Pins Description Port B Pins Description Port C Pins Description , , accessed with 3,2,2,2 clock cycles. Support for dram SIMMs upto 8 Mbyte with automatic size and speed , disabled in 68EC040 companion mode) providing the following functions: 1. DRAM Controller 2. Chip Select
Motorola
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ic 74ls245 PAL22V10-25 SMD LD3 xc68ec040* motorola MC68360 MC68EC040 RS-232 PAL16R4 QUICC040EVB

BT 4840 amp

Abstract: 3620* IBIS Synchronous DRAM Revision 1.2 November 2006 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION , 128M GDDR SDRAM 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data , (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins , normal write operation, even numbers of Din are to be written inside DRAM. 2. tRCDWR should be always , 58.24 39.88 58.72 40.12 59.12 40.36 59.44 40.56 59.72 40.76 60.00 40.96 60.28 41.16 60.48 41.36 60.72
Samsung Electronics
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BT 4840 amp 3620* IBIS K4D261638K-LC50 cs 2648 K4D261638K-LC40 k4d261638k K4D261638K 65TYP 20MAX 25TYP

K4D261638K-LC40

Abstract: BT 4840 amp Synchronous DRAM Revision 1.3 July 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO , Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 1.0 FEATURES · 2.5V + , ) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before , operation, even numbers of Din are to be written inside DRAM. 2. tRCDWR should be always greater or equal , 40.12 59.12 40.36 59.44 40.56 59.72 40.76 60.00 40.96 60.28 41.16 60.48 41.36 60.72 41.52
Samsung Electronics
Original
DIN 3968 ap 6928 K4D261638
Abstract: 13.5V) £ 20ns FALLTIME (13.5V to 1.5V) £ 2 0 n s 4-116 H I-3 0 6 /8 8 3 Burn-In Circuit H I , ' Cl TEMPERATURE ~ °C The net leakage in to the s o u rce o r dram is the N -channel leakage m , 10 12 14 It 0 Vd - DRAM VOLTAGE (VOLTS! 4 « < I» 12 14 II -
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HI-306/883 DG306 HI-304 HI-307 HI-3041 HI-300
Abstract: x 1 CMOS Static Column DRAM - e. optional processing Blank - Standard processing B *= Burn-in -d. , the 4-116 This Material Copyrighted By Its Respective Manufacturer time specified by tRHZ and will , , high-performance CMOS 256K DRAM which combines the fastest DRAM speed available (100-ns access time) with low power -
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90C257 WF010871
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