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Part Manufacturer Description PDF Samples Ordering
CD4047BE Texas Instruments CMOS Low-Power Monostable/Astable Multivibrator 14-PDIP -55 to 125 ri Buy
CD4047BEE4 Texas Instruments CMOS Low-Power Monostable/Astable Multivibrator 14-PDIP -55 to 125 ri Buy
CD4047BD3 Texas Instruments CMOS Low-Power Monostable/Astable Multivibrator 14-CDIP SB -55 to 125 ri Buy

4047 DIP

Catalog Datasheet Results Type PDF Document Tags
Abstract: 2 to 6 45 TSSOP H1G 7 SO 0 to VDD DIP 3 to 18 Packages Output resistor , only BEY M013TR M013TR DIP (tube) SO (T and R) For HC/HCT only B1R RM13TR RM13TR TTR DIP (tube) SO (T , 3-State 4042; 4099 373; 533; 563; 573; 16373; H16373 H16373 Multivibrator 123; 221; 423; 4538 4047 , 4025 4027 4028 4029 4030 4033 4035 4040 4042 4046 4047 4048 4049 4050 4051 4052 4053 , SOT323-5L, SOT23-5L/8L, TFBGA42 TFBGA42, Flip-Chip4 LFBGA96 LFBGA96 Through-hole packages DIP-24 DIP-20 Bulk ... Original
datasheet

10 pages,
1086.94 Kb

hct 4049 datasheet hct 4010 vhct 126 hcf 4093 datasheet 4049 DIP14 4017 14 pin package 4048 datasheet hct hcf 4541 be m74 display cmos 4047 equivalent hct 4049 HC 4093 vhc 595 datasheet abstract
datasheet frame
Abstract: outline) 2,500 pcs 1,000 pcs 3,000 pcs 3,500 pcs Through-hole packages February 2005 DIP-20 DIP-24 Bulk qty 2,000 pcs 25 pcs 1,000 pcs DIP-20 DIP-16 50 pcs DIP-14/16 DIP-14 Base qty DIP-8 DIP-8 Package 20 pcs 1,000 pcs DIP-24 15 pcs 750 pcs , 45 TSSOP H1G 7 SO 0 to VDD DIP 3 to 18 Packages Output resistor , only for LVC family as competition compliant Packages and packing for CMOS4000 CMOS4000 only BEY DIP (tube ... Original
datasheet

10 pages,
417.98 Kb

MM 4054 M22100 LVT 4502 LVC 161284 4000B LVC 139 hcf 4093 HCT CMOS 4017 family characteristics hct 4094 hct 4010 datasheet C3245 hcf 4541 be m013tr CMOS4000 datasheet abstract
datasheet frame
Abstract: .300±.002 Max. 10° 4.78±0.05 .188±.002 AQY21 AQY21(DIP) AQY41 AQY41(DIP) Series 3.2±0.2 .126±.008 , .008 2.54 .100 1.0 .039 Through hole terminal type AQV10 AQV10(DIP) AQV11 AQV11(DIP) AQV20 AQV20(DIP) AQV21 AQV21(DIP) AQV22 AQV22(DIP) AQV23 AQV23(DIP) AQV25 AQV25(DIP) AQV41 AQV41(DIP) AQV45 AQV45(DIP) Series 8.3 .327 0.47 .019 , 3.4 .134 3.4 .134 Recommended mounting pad (Top view) APV1122 APV1122(DIP) 3.4 .134 3.9±0.2 , 8-.031 dia. Max. 10° 2.54 .100 Max. 10° 6.4 .252 AQW21 AQW21(DIP) AQW22 AQW22(DIP) AQW25 AQW25(DIP) AQW41 AQW41 ... Original
datasheet

4 pages,
169 Kb

AQW61EH AQY21 AQV21 AQV20 AQV10 AQW21HL datasheet abstract
datasheet frame
Abstract: /5055 A m 4056/5056 A m 4047/5057 RC V DD D IE S IZ E 0 . 1 0 1 " X 0 .1 4 0 " 8-Pin Molded DIP P H YSIC AL D IM ENSIONS T op Views 8-Pin Herm etic DIP , i c 16-Pin Side Brazed DIP 9 f 310 16-Pin Molded DIP I'* ' 3 , .255 ^35 , I 16 9 Z) ' L J L VJ U 8 lv J l , Package Type 16-Pin Molded DIP 16-Pin Herm etic DIP 16-Pin Herm etic DIP TO-IOO Can TO-IOO Can 8-Pin Molded DIP 8-Pin Herm etic DIP 8-Pin Herm etic DIP Temperature Range 0°C to +70°C 0 C to +70 C - 5 5 ... OCR Scan
datasheet

4 pages,
257.81 Kb

IC 4047 BE pin diagram 4057D 4055D IC 4047 pin diagram Am4055/5055 Am4056/5056 Am4057/5057 Am4055/5055 abstract
datasheet frame
Abstract: Relays DIP/SIP Series CS Series Solid-State Voltage Sensors Adjustable pick-up, drop-out voltages. , contact. Maximum Switching Current: DIP, 1 or 2 makes - 0.5 A, 1 changeover - 0.25 A; SIP, 1 make - 0.5 A. KUL Maximum Continuous Current: DIP, 1 and Magnetic Latching Relays 2 makes - 1 A, DIP 1 changeover , power. Contacts rated DIP - Low Profile 10 amps at 28 VDC or 120 VAC, 80% power factor. Temperature , 3 A @ 280 VAC 11.03 9.93 9.01 - 3-32 VDC 0.05-50 A rms @ 80°C 40.47 36.79 33.73 Output 886-8002 ... Original
datasheet

1 pages,
106.63 Kb

V23100-V4005-A000 v23100 OAC5H V23100 V23100 abstract
datasheet frame
Abstract: , CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA , 4047 VA = 2.7V to 5.5V VA = 4.5V to 5.5V (Note 10) Bits (min) ± 2.6 ±8 LSB (max) +0.25 , range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C, unless , , input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C , Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated DNL at VA = ... Original
datasheet

19 pages,
891.8 Kb

DAC121S101CIMK DAC081S101 DAC101S101 DAC121S101 DAC121S101CIMKX DAC121S101CIMM DAC121S101CIMMX DAC121S101EVAL DAC7512 mk06a cmos 4047 AD5320 4047 application note 4047 DIP DAC121S101 abstract
datasheet frame
Abstract: 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) 12 12 Over Decimal codes 48 to 4047 , 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = , to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all , , TA = 25C, Input Code Range 48 to 4047, INL at VA = 5.0V 20195252 20195253 DNL at VA = 3.0V ... Original
datasheet

19 pages,
858.87 Kb

mark x73c X72C DAC122S085 DAC122S085 abstract
datasheet frame
Abstract: VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047 , Parameter Conditions Typical (Note 9) Limits (Note 9) 12 12 Over Decimal codes 48 to 4047 VA = 2.7V to 5.5V , GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other , to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all , , TA = 25C, Input Code Range 48 to 4047, INL at VA = 5.0V 20173252 20173253 DNL at VA = 3.0V ... Original
datasheet

19 pages,
868.7 Kb

DAC124S085 DAC124S085 abstract
datasheet frame
Abstract: , input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX and all other limits are at TA = , pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX and , , RL = 2k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits , 20173256 20173257 9 www.national.com DAC124S085 DAC124S085 Typical Performance Characteristics to 4047 , , TA = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) INL/DNL vs fSCLK at VA = ... Original
datasheet

18 pages,
821.21 Kb

cmos 4047 equivalent DAC084S085 DAC104S085 DAC124S085 DAC124S085CIMM DAC124S085CIMMX DAC124S085EVAL LM4050 LM4130 x66c DAC124S085 abstract
datasheet frame
Abstract: , VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for , +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits , , RL = 2k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits , 20195256 20195257 9 www.national.com DAC122S085 DAC122S085 Typical Performance Characteristics to 4047 , , TA = 25C, Input Code Range 48 to 4047, unless otherwise stated (Continued) INL/DNL vs fSCLK at VA = ... Original
datasheet

18 pages,
811.26 Kb

cmos 4047 equivalent DAC082S085 DAC102S085 DAC122S085 DAC122S085CIMM DAC122S085CIMMX DAC122S085EVAL LM4050 LM4130 X72C DAC122S085 abstract
datasheet frame

Datasheet Content (non pdf)

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LEVEL PROTOCOLS 52 PIN PLCC AND 48-PIN 48-PIN 48-PIN 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE ST X.25 CHIP (MK5025 MK5025 MK5025 MK5025) AND DAL 2-9 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a below for pin 16. Note: Pin out shown is for 48 pin dip. MK5027 MK5027 MK5027 MK5027 2/19 Table 1: Pin Description
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4284-v1.htm
STMicroelectronics 02/04/1999 26.81 Kb HTM 4284-v1.htm
LEVEL PROTOCOLS 52 PIN PLCC AND 48-PIN 48-PIN 48-PIN 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE ST X.25 CHIP (MK5025 MK5025 MK5025 MK5025) AND DAL 2-9 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a below for pin 16. Note: Pin out shown is for 48 pin dip. MK5027 MK5027 MK5027 MK5027 2/19 Table 1: Pin Description
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4284-v2.htm
STMicroelectronics 14/06/1999 26.78 Kb HTM 4284-v2.htm
BELLCORE SIGNALLING SYS- TEM NUMBER 7 LINK LEVEL PROTOCOLS 52 PIN PLCC AND 48-PIN 48-PIN 48-PIN 48-PIN DIP PIN-FOR-PIN Pin(s) Type Descriplion DAL 2-9 40-47 IO/3S The time multiplexed Data Address bus. During pin dip. MK5027 MK5027 MK5027 MK5027 2/19 Table 1: Pin Description (continued) Signal Name Pin(s) Type Descriplion
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4284.htm
STMicroelectronics 20/10/2000 29.91 Kb HTM 4284.htm
48-PIN 48-PIN 48-PIN 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025 MK5025 MK5025 MK5025) AND NEARLY PIN-FOR- 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a memory transfer pin dip. MK5027 MK5027 MK5027 MK5027 2/19 Table 1: Pin Description (continued) Signal Name Pin(s) Type
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4284-v3.htm
STMicroelectronics 25/05/2000 28.73 Kb HTM 4284-v3.htm
* Library of junction field-effect transistor (JFET) model parameters * Copyright 1988-1994 by MicroSim Corporation * Neither this library nor any part may be copied without the express * written consent of MicroSim Corporation. * $Revision: 1.9 $ * $Author: ANW $ * $Date: 21 Jun 1994 18:39:26 $ *- * MicroSim Corporation would like to acknowledge Sandia National Laboratories * for the contrib
www.datasheetarchive.com/files/spicemodels/misc/models/jfet1.lib
Spice Models 01/09/2003 109.85 Kb LIB jfet1.lib
* Library of junction field-effect transistor (JFET) model parameters * Copyright 1988-1995 by MicroSim Corporation * Neither this library nor any part may be copied without the express * written consent of MicroSim Corporation. * $Revision: 1.13.3.0 $ * $Author: MSB $ * $Date: 09 Sep 1996 09:00:46 $ * *- * MicroSim Corporation would like to acknowledge Sandia National Laboratories * for the contrib
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Spice Models 17/06/1998 109.03 Kb LIB jfet.lib
* Library of junction field-effect transistor (JFET) model parameters * Copyright Cadence Design Systems, Inc. 2002 All Rights Reserved. * * * $Revision: 1.2 $ * $Author: HIRASUNA $ * $Date: 11 May 2000 13:26:32 $ * *- * Cadence Design Systems, Inc. would like to acknowledge Sandia National * Laboratories for the contribution of their measurement-based models * included in this library. * The par
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Spice Models 19/12/2001 108.87 Kb LIB jfet.lib
* Library of junction field-effect transistor (JFET) model parameters * Copyright OrCAD, Inc. 1998 All Rights Reserved. * $Revision: 1.14 $ * $Author: RPEREZ $ * $Date: 17 Apr 1998 15:20:50 $ * *- * OrCAD Incorporated would like to acknowledge Sandia National Laboratories * for the contribution of their measurement-based models included in this * library. *-
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Spice Models 29/07/2012 108.92 Kb LIB jfet.lib
DIP packages. SECTION 2 - INTRODUCTION The SGS - Thomson MK502H5 MK502H5 MK502H5 MK502H5 Link Level Con- troller is a NAME PIN(S) TYPE DESCRIPTION DAL 2-9 40-47 [2-10 44-51] IO/3S The time multiplexed
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4285-v3.htm
STMicroelectronics 25/05/2000 118.33 Kb HTM 4285-v3.htm
pin PLCC(for use with external ROM), or 48 pin DIP packages. SECTION 2 - INTRODUCTION The SGS - ) MK50H25 MK50H25 MK50H25 MK50H25 3/64 SIGNAL NAME PIN(S) TYPE DESCRIPTION DAL 2-9 40-47 [2-10 44-51] IO/3S The time
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/4285-v1.htm
STMicroelectronics 02/04/1999 115.99 Kb HTM 4285-v1.htm