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Part Manufacturer Description Datasheet BUY
LTC1564CG#PBF Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1564CG#TR Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1564IG#PBF Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1564CG#TRPBF Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1564IG Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1564IG#TR Linear Technology LTC1564 - 10kHz to 150kHz Digitally Controlled Antialiasing Filter and 4-Bit P.G.A; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

4-bit bcd subtractor

Catalog Datasheet MFG & Type PDF Document Tags

8 bit bcd adder subtractor

Abstract: 4 bit serial subtractor Binary Full Adder w /Fast Carry Quad Serial Adder/Subtractor 4-Bit BCD Adder - 54F/74F283 54F/74F385 54F/74F583 Yes Multipliers Function Device Expandable\ Adder/Subtractor' Leads 8-Bit Serial/Parallel Multiplier 8-Bit Serial/Parallel Multiplier 54F/74F384 54F/74F784 Yes / .- y T-r CO P
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8 bit bcd adder subtractor 4 bit serial subtractor binary 4 bit serial subtractor bcd subtractor 4 Bit BCD Subtractor 4-bit bcd subtractor S0115S 54F/74F151A 54F/74F153 54F/74F157A 54F/74F158A 54F/74F251A

full adder circuit using nor gates

Abstract: full subtractor circuit using nand gate Non-Inverting Booth decoder Inverting Booth decoder 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on Shifters Arithmetic Right (Padded , CNC4 CND4 CND4A CNE4 CNF4 CNG4 BCD counter/4 bit latch decoder/driver 4 bit counter latch 4 , data bit (transparent) with update latch JTDUF Test register data bit (transparent)] with update latch JTDDT Test register data bit (transparent) Power Supply Cells JTDDF Test
Zarlink Semiconductor
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full adder circuit using nor gates full subtractor circuit using nand gate full subtractor circuit using nor gates full subtractor circuit using decoder 8 bit carry select adder verilog codes half adder 74 CLA70000 DS2462

8 bit carry select adder verilog codes

Abstract: full subtractor circuit using decoder decoder Inverting Booth decoder SUBTRACTOR BLOCKS ADSU4 ADSU8 ADSU16 ADSU24 ADSU32 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on , register data bit (transparent) with update latch Test register data bit (transparent)] with update latch Test register data bit (transparent) Test register data bit (transparent) Test register data bit (clocked) with update latch Test register data bit (clocked) with update latch Test register data bit
GEC Plessey Semiconductors
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CLA60000 3 bit carry select adder verilog codes gec plessey semiconductor tdb 158 dp VHDL program 4-bit adder 8 bit subtractor 8 bit carry select adder vhdl codes 602858F

full subtractor circuit using decoder

Abstract: full subtractor circuit using nor gates Non-Inverting Booth decoder Inverting Booth decoder 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on Shifters Arithmetic Right (Padded , CNC4 CND4 CND4A CNE4 CNF4 CNG4 BCD counter/4 bit latch decoder/driver 4 bit counter latch 4 , data bit (transparent) with update latch JTDUF Test register data bit (transparent)] with update latch JTDDT Test register data bit (transparent) Power Supply Cells JTDDF Test
Zarlink Semiconductor
Original
full subtractor circuit using nand gates full subtractor circuit nand gates 0-99 counter by using 4 dual jk flip flop circuit for core bit excess 3 adder 74 full subtractor barrel shifter with flip flop

full subtractor circuit using xor and nand gates

Abstract: full subtractor circuit using nor gates Conditional Sum Accumulator 32-bit Conditional Sum Accumulator 4-bit Conditional Sum Subtractor 8-bit Conditional Sum Subtractor 16-bit Conditional Sum Subtractor 32-bit Conditional Sum Subtractor 4-bit by 4-bit , BCD to 7-segment decoder dual D FFs with preset & clear 4-bit D latch dual J-K FFs with common , B[0:7] EQCOMP8 A[0:7] B[0:7] CI S[0:7] RIPADD8 8,16 bit 8,16 bit C O A [0 :1 1 ] CSSUB4 8,16 bit Q [0 :3 ] CSACC4 EQ B [0 :1 1 ] EQCOMP12 A [0 :1 5 ] B [0
QuickLogic
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full subtractor circuit using xor and nand gates 4-bit full adder using nand gates and 3*8 decoder 2 bit magnitude comparator using 2 xor gates BCD adder and subtractor half adder using x-OR and NAND gate full adder circuit using xor and nand gates 7400-S TTL244

low power and area efficient carry select adder v

Abstract: IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER Generator Cell Count Typical Delay 60 45 5.5ns 3.0ns BCD Counter/4 bit Latch BCD Decoder , Carry Select Adder, with reduced area SUBTRACTOR BLOCKS: ADSU4 4 bit Subtractor for use with Adder Cells ADSU8 8 bit Subtractor for use with Adder Cells ADSU16 16 bit Subtractor for use with Adder Cells ADSU24 24 bit Subtractor for use with Adder Cells ADSU32 32 bit Subtractor for use with Adder , during a clock cycle. (One 8 bit word from a 1k x 8 bit block for example.) Another important factor in
Zarlink Semiconductor
Original
low power and area efficient carry select adder v IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER 32 bit carry select adder 16 bit carry select adder 8 bit carry select adder full subtractor implementation using NOR gate MVA60000 DS5499

full subtractor circuit nand gates

Abstract: 8 bit carry select adder verilog codes 32 bit adder 7 CLA70000 SERIES SUBTRACTOR BLOCKS BMB16X12 Single pipeline multiplier , 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on SHIFTERS ARITHMETIC RIGHT (PADDED WITH MSB) SHA4 SHA8 SHA16 SHA24 , CNG4 BCD counter/4 bit latch decoder/driver 4 bit counter latch 4 bit synchronous counter 4 bit , JTDUT Test register data bit (transparent) with update latch JTDUF Test register data bit
Zarlink Semiconductor
Original
PLESSEY CLA advantages of master slave jk flip flop 32 bit barrel shifter vhdl VHDL program to design 4 bit ripple counter cla74000 SRG4

full subtractor circuit using decoder and nand ga

Abstract: GP144 ADSU16 ADSU24 ADSU32 BMC24X24 Mixed mode multiplier (24 x 24 bits) 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on , multiplier (16 x 16 bits) Mixed mode multiplier (24 x 24 bits) BCD counter/4 bit latch decoder/driver 4 , PDS-BIST JTAG Identification Register TEST REGISTER COMPONENT CELLS Test register data bit (transparent) with update latch JTDUF Test register data bit (transparent)] with update latch JTDDT Test
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full subtractor circuit using decoder and nand ga GP144 LC28 full adder 2 bit ic

GP144

Abstract: 16 bit adder 24 bit adder CLA70000 SERIES ADT32 32 bit adder SUBTRACTOR BLOCKS BMB16X12 , Mixed mode multiplier (24 x 24 bits) 4 bit subtractor add-on 8 bit subtractor add-on 16 bit subtractor add-on 24 bit subtractor add-on 32 bit subtractor add-on SHIFTERS ARITHMETIC RIGHT (PADDED , CNB4 CNC4 CND4 CND4A CNE4 CNF4 CNG4 BCD counter/4 bit latch decoder/driver 4 bit counter , REGISTER COMPONENT CELLS Test register data bit (transparent) with update latch JTDUF Test register
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half subtractor

Abstract: HEF4751 half channel offset). Programming is performed in BCD code in a bit-parallel, digit-serial format. To , negative; P = A - B - bjn + M; · 10s. The numbers A and B, each consisting of six four bit digits n g A jo , of the programme data subtractor, which is valid after fetch period 5. Input SI is the borrow input , from a lower to a higher significant U.D. subtractor, the U.D.s have to be programmed sequentially in , d2 BORROW LATCH DATA SUBTRACTOR SI l / 1 dV borrow LATCH DATA SUBTRACTOR IN < ÔSYC
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half subtractor HEF4751 HEF4751V

23TRX6B

Abstract: 11CDX4b » SUBTRACTOR SCOTT ZE3I COSINE WUlTlPLIEf m SUBTRACTOR Figure 6.2. Electronic Control , in the converter be of the BCD type, rather than the binary-coded type. Figure 6.3 shows the block , Diagram. 63 Converter Busy (CB) and a Built-ln-Test (BIT) signal are also provided. Input scaling , protection, digital cor rection and calibration, IEEE 488 interface and binary or BCD input. They are , power dissi pation by 50% over a DC operated amplifier. They have a disable input and a BIT output
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23TRX6B 11CDX4b input scott-t transformer SIM-31200 18TRx6b synchro receiver transmitter 18TRX6B

74F126

Abstract: 74F154 /Parallel-ln, Serial Out Shift Register 8-Bit Bidirectional Universal Shift Register 4-Bit Up/Down BCD Binary , Ahead Carry Generator 64-Bit Random Access Memory, INV (3-State) Asynchronous Presettable Up/Down BCD Binary Counter Up/Down BCD Binary Counter with Separate Up/Down Clocks 4-Bit Bidirectional Universal , DESCRIPTION 4-Bit Arithmetic Logic Unit 4-Bit Arithmetic Logic Unit Quad Serial Adder/Subtractor Dual 4-Bit , -Input, 2-Wide 3-Input AND-OR-INVERT Gate 4-2-3-2 Input AND/OR Gate Dual D-Type Flip-Flop 4-Bit Magnitude
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74F112 74F126 74F154 16 line to 1 multiplexer IC 74F00 74F02 74F04 74F06 74F06A 74F07

PC6015

Abstract: Full Adder 1-Bit Adder/Subtractor 2-Bit Adder/Subtractor DELAY GATE NS EQUIV. 10 4.1 5.7 , Decade Counter Synchronous 4-Bit Binary Counter Synchronous BCD Counter Synchronous 4-Bit Binary , Parallel-ln-Serial-Out Shift Register Synchronous BCD Decade Up/Down Counter Synchronous 4-Bit Binary Up/Down Counter , 4-Bit Binary Up Counter 82 5-Bit Binary Up Counter 98 6-Bit Binary Up Counter Presettable BCD , are available for PLA, datapath, multiplier, and 2901 Bit Slice cells. Also available are a
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PC6015 EER004 EER008 EER016 EER032 EER064 EER128

74f847

Abstract: 74F154 , REGISTER FILES FUNCTION Quad 2 Port, NINV, INV Quad 2 Port, NINV Dual Octal, 3-State Register File 10-Bit, NINV, 3-State 10-Bit, INV, 3-State 9-Bit, NINV, 3-State 9-Bit, INV, 3-State 8-Bit, NINV, 3-State 8-Bit , of 74F373) 8-Bit Addressable 8-Bit Interface, 3-State 8-Bit Interface, 3-State 9-Bit Interface, 3-State 9-Bit Interface, 3-State 10-Bit Interface, 3-State 10-Bit Interface, 3-State DEVICE NUMBER 74F256 , , 10/9 Bit Serial-ln/Parallel-ln/Parallel-Out, Shift Right, 3-State Serial-ln/Parallel-ln/Serial-Out
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74f847 4 bit identity comparator 74F07A ALU of 4 bit adder and subtractor 4 bit binary full adder and subtractor 74F14 74FOO 74F10 74F20 74F30 74F132

sdc 339

Abstract: SIM-31200 . 21,45 BCD (see binary-coded-decimal) binary code, natural. 7,9,78 binary-coded-decimal (BCD) coding. 63-64 B.I.T. (see built-in-test) bit, binary. 8 bode plot. 21,45 brush encoder (see transducer) built-in-test (B.I.T.) logic to test malfunction , /D or R/D with an IBM PC/AT/XT 98 using BIT to speed up slew rate. 100
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sdc 339 scott-t transformer DTC-19300 Motorola xt 912 DSC 10 servo resolver SIM-36010 RDC-19220

hef4751

Abstract: HEF4751V selection), and a mode H stage (H = 1 or 2, stage for half channel offset). Programming is performed in BCD , six four bit digits ng^ to n5A anc' n0B t° n5B> are applied in fetch period 0 to 5 to the inputs Ag , output of the programme data subtractor, which is valid after fetch period 5. Input SI is the borrow , from a lower to a higher significant U.D. subtractor, the U.D.s have to be programmed sequentially in
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HEF4751VD HEF4751VT S028

HE4000B

Abstract: HEF4751V half channel offset). Programming is performed in BCD code in a bit-parallel, digit-serial format , and B, each consisting of six four bit digits n0A to n5A and n0B to n5B, are applied in fetch period , . Output OFB3 is converted to the borrow output of the programme data subtractor, which is valid after , , to LOW. For proper transfer of the borrow from a lower to a higher significant U.D. subtractor, the
Philips Semiconductors
Original
HE4000B HEF4751VP IC04 LOCMOS HE4000B Logic programme

ic 74 LS 138 DECODER

Abstract: Alu 181 -lnput Multiplexer, Inverting A 16 LS 160 BCD Decade Counter, Asynchronous Reset (9310 Type) A 16 LS161A 4-Bit , Flip-Flop with Enable A 16 LS385 Quad 4-Bit Adder/Subtractor A 20 LS386 2-lnput Quad/Exclusive OR Gate A , /Inverting A 16 ALS160 BCD Decade Counter/Asynchronous Reset (9310 Type) A 16 ALS161 4-Bit Binary , -lnput NAND Buffer A 14 LS42 1-of-10 Decoder A 16 LS47 BCD to 7-Segment Decoder/Driver, Open-Collector A 16 LS48 BCD to 7-Segment Decoder/Driver, with Pull-Ups A 16 LS49 BCD to 7-Segment Decoder
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ic 74 LS 138 DECODER Alu 181 8 bit bcd adder/subtractor f245 motorola lal 2084 internal circuitry for sr flip flop SG60R4

circuit diagram of BCD subtractor

Abstract: MC10137 620,648,650 Dual High Speed Adder/Subtractor MC 10180 MC 10580 4.5 360 620,648,650 4-Bit Arithmetic , 150 MHz 625 620,650 Bi-Quinary Counter MC 10138 - f = 150 MHz 370 620 64-Bit Random Access Memory , f = 200 MHz 425 620,648,650 64-Bit Random Access Memory (50 U) MCM10142 - »Access = 10
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MC10137 MC10537 MCM10140 MC10141 MCM10143 MCM10144 circuit diagram of BCD subtractor Hex Set-Reset Latch 256-B

mcm10147

Abstract: 8 bit bcd adder subtractor 620,648,650 Dual High Speed Adder/Subtractor MC 10180 MC 10580 4.5 360 620,648,650 4-Bit Arithmetic , 150 MHz 625 620,650 Bi-Quinary Counter MC 10138 - f = 150 MHz 370 620 64-Bit Random Access Memory , f = 200 MHz 425 620,648,650 64-Bit Random Access Memory (50 U) MCM10142 - »Access = 10
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MCM10145 MCM10148 MCM10150 mcm10147 10216 128-B MCM10147 1024-B
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