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Part Manufacturer Description Datasheet BUY
CS496122-CQZR Cirrus Logic IC DSP 32BIT 16CH SER IO 144LQFP visit Digikey
CS48520-DQZR Cirrus Logic IC DSP HP 32BIT 4CH I/O 48LQFP visit Digikey
CS48520-DQZ Cirrus Logic IC DSP HP 32BIT 4CH I/O 48LQFP visit Digikey
CS4365-CQZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PQFP48, LEAD FREE, MS-022, LQFP-48 visit Digikey
CS4365-DQZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PQFP48, LEAD FREE, MS-022, LQFP-48 visit Digikey
CS4344-CZZR Cirrus Logic D/A Converter, 1 Func, Serial Input Loading, PDSO10, 3 MM, MO-187, TSSOP-10 visit Digikey

4+input+4+output+on+off+ic+dip+16

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: NAND Gate (Open C o lle c to r). Dual 4-Input NAND Schmitt T r ig g e r , AND Gate (Open C o lle c to r). Dual 4-Input NAND Gate . Dual 4-Input AND Gate . Dual 4-Input NAND , . Quad 2-Input NAND Buffer (Open Collector) . Dual 4-Input NAND B u f f e r , -lnput AND-OR-INVERT Gate . . . . 2-3-3-2-lnput AND-OR-INVERT G a t e . 2-Wide 4-Input -
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T74LS02 T74LS244 t74LS161a sgs T74LS293 T74LS5 T74LS00 T74LS01 T74LS03 T74LS04 T74LS05
Abstract: Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time *7+14+ *7 -1 4 *11-14+ *11-14*12+14+ *1 2-1 4 *10+14*7+14+ *7-14- *setup *hold t+ t14 14 14 14 14 14 14 14 14 14 14 14 14 3.7 3.7 2.7 2.7 1.6 , page 3-63. 3. Input level on data input taken from +0.4V up to voltage level given. 4. Input level on , Reset input Hysteresis Mode Setup Time Hold Time Rise Ttme Fall Time 1. 2. 3. 4. 5. Pin 5 to V ^ g , 1.16 1,16 1,16 1,5,16 1,5,16 1,16 1,16 1,16 1,16 13 4 6 7 13 >CBO I1-) 9 9 9 9 9 9 9 9 9 9 9 9 -
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MC10129 DL122
Abstract: Reference Clocks (8 kHz, 1.5, 2, 4, 8, 16, 19.4 MHz) 1 K Channel (16 input and 16 output streams , Conversion (2, 4, 8, 16 Mbps) ZL50050 8 K Channel (32 input and 32 output streams) High Jitter , with Per-Stream Rate Conversion (2, 4, 8, 16, 32 Mbps), pin compatible with MT90870 64 Input , Per-Stream Data Rate 2, 4, 8, 16, 32 Mbps 16 K x 16 K Input Delay 12 K Channel (48 input and 48 , Per-Stream Rate Conversion (2, 4, 8, 16, 32 Mbps) ZL50061 16 K Channel (64 input and 64 output streams Zarlink Semiconductor
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ZL50018 ZL50019 MT90810 ZL50022 ZL50021 ZL50015 ZL50030 MT90812 MT9080B
Abstract: ZL50011 512 Channel (16 input and 16 output streams) Flexible Digital Switch with Stratum 4 DPLL , ) Per-Stream Data Rate 2, 4, 8, or 16 Mbps Output Timing MT8986 512 x 256 Channel (16 input and 10 , 16 BiDirectional Streams 2 K Input Channel 2Kx4K 4 K Output Channel 1Kx1K 2Kx2K , (32 input and 32 output streams) Flexible Digital Switch with Per-Stream Rate Conversion (2, 4, 8, 16 , Conversion (2, 4, 8, 16, 32 Mbps) ZL50057 12 K Channel (48 input and 48 output streams) High Jitter Zarlink Semiconductor
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ZL50010 MT90863 MT89L86 MT8920B MT90840 10ZL059
Abstract: Half-Shlft Reglster(w/o Inverter) 4-Input NOR Gate Half Adder 2-Input Buffer Dual 2-Input NOR Gate 4-Input OR , NOR Gate Dual 3-Input NOR Gate Dual 4-Input NOR Gate 900/G.H 901/G.H 902/G.H 903/G.H 904/G.H 905 , ,A 918/C,H,I 919/C,A 80 16 13 16 16 13 13 16 - 25 5 4 5 5 4 4 5 - - 14 12 14 22 22 12 _ - 4 30 4 4 4 3 - 60 57 27 60 66 75 12 12 - - 16 16 10 - 5 5 3 - , Dual 4-Input NOR Gate J-K Flip-Flop Quad Inverter 5-Input NOR Gate 5-Input NOR Gate Dual Exclusive OR -
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full subtractor 00D0353 T-43-01 14-LEAD 16-LEAD 10-LEAD 905/G
Abstract: LE res LE load cs DO0 to DO15 Configuration Register 16 Load Register 4 4 to 16 Decode 4 Output Address Input Address Figure 2 shows the hierarchy of design files that , (1) input address[4] tri output address[3.0] 4 cs out_add data_in 16 MAX/MAX II , ] 4 cs out_add MAX/MAX II di do in_add input address[3.0] 16 tri 4 cs out_add 16 , . 4-Bit Decoder Inputs & Outputs Decoder Input [3.0] Decoder Output [15.0] Enabled Output Altera
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EPM240T100C3 epm3064 EPM570F256C3 epm3064atc100-4 EPM570 AN-294-2 800-EPLD
Abstract: 13 16 16 13 13 16 - - - - - - 16 16 10 - 25 5 4 5 5 4 4 5 - - - - - - 5 5 3 - - - - , Half-Shift Register Half-Shift Register (w/o Inverter) 4-Input NOR Gate Half Adder 2-Input Buffer Dual 2-Input NOR Gate 4-Input OR/NOR Gate Half Adder Type D Flip-Flop Dual 2-Input NOR Gate Dual 3-Input NOR Gate J , - - 16 16 16 - 10 - - - - - 5 5 5 5 - 5 - - - 5 5 5 - 3 - - 3 - - 4 4 - - - 25 5 , FUNCTION Dual 3-Input NOR Gate Dual 4-Input NOR Gate J-K Flip-Flop Dual 2-Input Gate Expander J-K -
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4 bit binary full adder and subtractor Inverter GH half subtractor 9824 motorola RTL integrated circuits gh902 906/G 907/G 908/G
Abstract: DUAL 4-INPUT MULTIPLEXER 20 14 B M D T54LS/T74LS155 DUAL 1-OF-4 DECODER 20 16 B M D T54LS/T74LS156 DUAL 1-OF-4 DECODER (OPEN COLLECTOR) 20 16 B M D T54LS/T74LS157 QUAD 2-INPUT MULTIPLEXER , B M D T54LS/T74LS251 8-INPUT MULTIPLEXER (3-STATE) 20 16 B M D T54LSnV4LS253 DUAL 4-INPUT , MULTIPLEXER WITH OUTPUT LATCHES 20 16 B M D T54LS/T74LS352 4-INPUT MULTIPLEXER 20 16 B M D T54LS/T74LS353 DUAL 4-INPUT MULTIPLEXER (3-STATE LS352) 20 16 B M D T54LS/T74LS365 HEX BUFFER WITH COMMON ENABLE (3 -
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74LS00 t74ls157 74LS00E 74LS00 fan out T74LS74 74LS00 QUAD 2-INPUT NAND GATE 74LS00 nand gate TTL-54/74 T54LSXXD2 T74LSXXB1 T74LSXXD1 T74LSXXM
Abstract: Register cs res 16 Load Register load 4 to 16 Decode 4 Output Address Input Address , Input 13 1001 Input 14 1000 Input 15 You can select one of the 16, 4-bit registers in the , tri cs cs out_add 16 MAX di do in_add data_in tri 4 input address[3.0 , in_add input address[3.0] do tri 4 cs out_add MAX 16 di do in_add data_in 16 , . Figure 3. Switch Matrix Circuit Output Cell 16 Inputs Output 4 Select Pin 1 Altera Altera
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EPM3256ATC144-7 EPM3256A AN-294 Crosspoint Switches EPM3064A verilog code for switch AN-294-1
Abstract: and Logic Allocator 16 Macrocells 16 Output Switch Matrix 4 Input Switch Matrix , Cells 8 16 16 16 Input Switch Matrix 16 Macrocells 4 4 8 Clock Generator , 8 OE Output Switch Matrix OE 4 OE 16 Input Switch Matrix 16 4 33 24 , Cells 8 I/O24­I/031 16 16 24 24 16 16 Input Switch Matrix 4 4 33 , Clock Generator 4 4 8 4 I/O Cells 8 Input Switch Matrix 33 16 16 8 Vantis
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STR F 6168 1 - bit full adder multisim grid tie inverters circuit diagrams tms 3755 PAL 007 B HI-LO ALL-07 175MH 17466E-059 PQR100 100-P 17466E-060 PQL100
Abstract: Clock Input Internal: /1 /4 /16 /64 /256 /1024 /4096 Interrupt request signals Channel 0 , capture TGR compare match or input capture Channel 3 / 1 / 4 / 16 / 64 / 256 / 1024 , match or input capture TGR4A TGR4B - Channel 5 / 1 / 4 / 16 / 64 / 256 TCLKA TCLKC , match or input capture Channel 4 / 1 / 4 / 16 / 64 / 1024 TCLKA TCLKC Interrupt , x 16-bit · · · · · · · · · · · Maximum 8-pulse input/output A total of 8 timer Hitachi Semiconductor
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TSR definition H8S/2312 H8S/2352 H8S2240 Hitachi DSA0071 HITACHI microcontroller h8s H8S/2636 H8S/2245
Abstract: . Flip-Flop 3-INPUT NOR Gate Half-Adder Half-Shlft Register Half-Shift Register(w/o Inverter) 4-Input NOR Gate Half-Adder 2-Input Buffer Dual 3-Input (NOR Gate) 4-Input OR/NOR Gate Half-Adder Type D Flip-Flop Dual 2-Input NOR Gate Dual 3-Input NOR Gate J.K. Flip-Flop Quad 2-Input NOR Gate Dual 3-Input NOR Gate Dual 4-Input , 5 4 5 5 4 4 5 4 30 4 4 4 4 16/45 2 55 22 19/5 2 45 53 36 19/5 2 14/8.5 2 5.5/16 2 8/1 2 6/3.5 2 11.5/5.5 2 17.5/13 3 38/10 2 16 16 10 5 5 3 4 4 4 55/15 2 91/79 3 20/5.0 2 12/2/5 2 13/2.5 2 -
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d998 d 986 d986 gh903 hi9801 TSJ-21 MIL-M-38510 24-LEAD 12-LEAD 40-LEAD 20-LEAD
Abstract: mAdc Input Current IinH 4 6 7 10 11 12 13 150 150 150 720 390 390 150 95 95 , +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level , 8 Positive Power Supply Drain Current ICC 9 Input Current IinH 4 6 7 10 11 , Input Strobe Input Reset Input Hysteresis Mode Setup Time Hold Time Rise Time Fall Time 4 6 7 13 1,16 1,16 1,16 4 6 4 6 11,12 10 10,11 10,12 12 12 12 1,16 1,16 1,5 Motorola
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T714 T1214 MC10129/D
Abstract: -Channel (Single-Ended) Analog-to-Digital Input PCI Product Individually-Isolated 16-Bit 4-Channel (Single-Ended) Simultaneous-Sampling Analog-to-Digital Input PCI Product Individually-Isolated 16-Bit 4-Channel (Differential , , Digital Input/Output, and Counter Low Profile PCI Product 16-Bit 4-Channel Digital-to-Analog Output (Bipolar +/-10 V) and 8-Channel Digital Input/Output Low Profile PCI Product Bus-Isolated 16-Bit 4 , -632104 32-Bit 4-Channel 3-Mode Pulse Counter and 16-Channel Digital Input/Output Low Profile PCI Product 32 Interface Amita Solutions
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LPC-530115 LPC-530121 LPC-530215 LPC-530221 LPC-530421 LPC-530521
Abstract: Inverter Schmitt Trigger Dual 4-Input NAND Gate Triple 3-Input NOR Gate 8-Input NAND Gate Quad 2-Input OR Gate Quad 2-Input NAND Buffer (OC) Quad 2-Input NAND Buffer Dual 4-Input NAND Buffer Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate 4-2-3-2 Input AND/OR Gate Dual D-Type Flip-Flop 4-Bit Magnitude , /Demultiplexer Dual 1-of-4 Decoder/Demultiplexer 8 Line to 3 Line Priority Encoder 8-Input Multiplexer Dual 4-Input Multiplexer 1-of-16 Decoder/Demultiplexer Quad 2-Input Data Selector/Multiplexer NINV Quad 2-Input Data -
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74F112 74F126 74F154 16 line to 1 multiplexer IC BCD adder and subtractor 74F00 74F02 74F04 74F06 74F06A 74F07
Abstract: Switch Matrix 16 Input Switch Matrix 16 Macrocells 4 16 OE 16 8 Clock , Switch Matrix 16 Macrocells 16 16 4 8 4 Input Switch Matrix Clock Generator , Matrix Input Switch Matrix 16 4 68 X 90 AND Logic Array and Logic Allocator 33 8 4 16 33 16 Macrocells 16 16 Input Switch Matrix 4 16 16 4 4 Output , 24 Macrocells 16 Clock Generator Input Switch Matrix 16 16 16 Macrocells 4 Vantis
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FOUR INPUT AND GATE generator 4...20 mA HP3070 Latches mach 1 family amd MACH111SP MACH4-192/MACH4LV-192 MACH111SP- MACH4-192 M4-192 MACH4LV-192 M4LV-192
Abstract: Clock Input Internal: /1 /4 /16 /64 /256 /1024 /4096 Interrupt request signals Channel 0 , capture TGR compare match or input capture Channel 3 / 1 / 4 / 16 / 64 / 256 / 1024 , match or input capture TGR4A TGR4B - Channel 5 / 1 / 4 / 16 / 64 / 256 TCLKA TCLKC , match or input capture Channel 4 / 1 / 4 / 16 / 64 / 1024 TCLKA TCLKC Interrupt , x 16-bit · · · · · · · · · · · Maximum 8-pulse input/output A total of 8 timer Hitachi Semiconductor
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H8S2636
Abstract: Supply Drain Current ICC 9 8.0 8.0 8.0 mAdc Input Current IinH 4 6 7 10 11 , +0.4V up to voltage level given. 4. Input level on data input taken from +4.0V down to voltage level , Current ICC 9 Input Current IinH 4 6 7 10 11 12 13 VIHAmin VILAmax VIH 13 , Hold Time Rise Time Fall Time 4 6 7 13 1,16 1,16 1,16 1,16 10 11 12 1,16 1,16 1,16 4 6 4 6 1,16 1,16 1,5,16 1,5,16 4 6 4 6 2 (2.) 2 2 2 2 (3.) 2 (4.) 10,12 ON Semiconductor
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MC10129FN MC10129L MC10129P
Abstract: 16 16 8 4 Output Switch Matrix 8 16 4 16 Macrocells OE 16 Input Switch , Switch Matrix 8 16 Clock Generator 16 8 16 Macrocells 16 4 24 Input Switch , Allocator 2 16 Input Switch Matrix 4 Clock Generator Clock Generator I/O Cells I/O , 16 Macrocells Block D 24 16 16 Input Switch Matrix 8 OE 4 16 66 X 90 AND Logic Array and Logic Allocator 33 4 4 4 8 OE 16 Input Switch Matrix 16 Lattice Semiconductor
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160 e7 m4lv-256/128 M4-32/32 M4LV-32/32 M4-64/32 M4LV-64/32 M4-96/48 M4LV-96/48
Abstract: Allocator 4 4 8 4 MACH 4 Family 16 Input Switch Matrix 16 Macrocells 4 16 , 16 16 4 8 4 Input Switch Matrix 24 68 X 90 AND Logic Array and Logic Allocator , Allocator 24 Input Switch Matrix Input Switch Matrix 4 33 24 16 16 68 X 90 AND Logic Array and Logic Allocator 24 Macrocells OE Input Switch Matrix 16 4 16 16 , Latch Gate 4 14 16 ns tIGSS Input Latch Gate to Output Latch Setup Using Global Output Vantis
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MACH4LV-192/96-12/14/18
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