NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 3B302 3B302 XXXX 3B332 3B332 XXXX 3B352 XXXX 3B372 3B372 XXXX 3B502 3B502 XXXX Output Voltage ... | Original |
7 pages, |
GQ2123 3B502 3B312 GQ2123 abstract |
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| Abstract: 3B152 3B152 XXXX 3B252 3B252 XXXX 3B282 3B282 XXXX 3B302 3B302 XXXX 3B332 3B332 XXXX 3B352 XXXX 3B372 3B372 XXXX 3B502 3B502 XXXX ... | Original |
7 pages, |
3B312 3B502 SQ2123 SQ2123 abstract |
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| Abstract: SGS-THOMSON iy M M54HC279 M54HC279 M74HC279 M74HC279 QUAD S - R LATCH HIGH SPEED tPD = 13 ns (TYP.) at VCc= 5V LOW POWER DISSIPATION ICC = 2 iiA (MAX.) at Ta = 25°C HIGH NOISE IMMUNITY VnIH = VnIL= 28% Vcc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IIOHI = lOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54/74LS279 54/74LS279 DESCRIPTION The M54/74HC279 M54/74HC279 Is a high speed CMOS QUAD S - R LATCH ... | OCR Scan |
5 pages, |
SGS 54HC M74HC279 M54HC279 74LS279 equivalent 74ls279 74HC 54HC 74hc279 M54HC279 abstract |
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| Abstract: METRIC MIL-STD-1760C MIL-STD-1760C 20 March 1997 _ SUPERSEDING MIL-STD-1760B MIL-STD-1760B 15 April 1991 DEPARTMENT OF DEFENSE INTERFACE STANDARD FOR AIRCRAFT/STORE ELECTRICAL INTERCONNECTION SYSTEM AMSC: N/A AREA: GDRQ DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. MIL-STD-1760C MIL-STD-1760C FOREWORD 1. This standard is approved for use by all Departments and Agencies of the Department of Defense. 2. Prior to this standard, an aircraft and the stores ... | Original |
183 pages, |
connector cross reference mil-c-38999 STANAG connector MIL-STD-1553 connector drones aircraft M85049/80-12 datasheet m85049/80 mil-b-5087 MIL-C-39029/58 MIL-C-39029/90 MIL-C-39029/56 umbilical connector umbilical connector missile MIL-STD-1760C MIL-STD-1760B MIL-STD-1760C abstract |
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| Abstract: Features · High Performance, Low Power Atmel® AVR® 8-bit Microcontroller · Advanced RISC Architecture · · · · · · · 129 Powerful Instructions - Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 1 MIPS throughput per MHz On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory 8K Bytes Flash of In-System Programmable Program Memory · Endurance: 10,000 Write/Erase Cycles Optional Boot Code Sectio ... | Original |
361 pages, |
SO32 bldc c source code AVR dali emergency lighting schematic DALI gateway AT90PWM2 dali schematic AT90PWM3B QFN32 schematic automotive hid lamp ballast SO24 dali transmiter schematic AT90PWM3 psc AT90PWM3 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| www.datasheetarchive.com/download/40220571-917099ZC/sbvm122.zip (TLV71733.LIB) |
Texas Instruments | 17/01/2012 | 33.23 Kb | ZIP | sbvm122.zip |
| 4b6085f2012636675a0aa31c52 $CDNENCFINISH .ends RF_sel_u1_S4 *$ .subckt RF_sel_u1 www.datasheetarchive.com/download/14643526-922815ZC/tps53219_pspice_transient_model.zip (tps53219_trans.lib) |
Texas Instruments | 11/08/2011 | 66.96 Kb | ZIP | tps53219_pspice_transient_model.zip |
| (DELAYFILE (SDFVERSION "2.1") (DESIGN "res_xdw_no_share") (DATE "Mon Jan 26 20:07:06 1998") (VENDOR "Xilinx") (PROGRAM "Xilinx VERILOG SDF writer") (VERSION "M1.4.12") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS) (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1ps) (CELL (CELLTYPE "X_BUF") (INSTANCE U200) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0) (IOPATH IN OUT (2050:2050:2050) (2050:2050:2050) ) ) ) (CELL (CELLTYPE "X_ www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| (DELAYFILE (SDFVERSION "2.1") (DESIGN "res_no_share") (DATE "Mon Jan 26 20:00:09 1998") (VENDOR "Xilinx") (PROGRAM "Xilinx VERILOG SDF writer") (VERSION "M1.4.12") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS) (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1ps) (CELL (CELLTYPE "X_BUF") (INSTANCE U200) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0) (IOPATH IN OUT (2050:2050:2050) (2050:2050:2050) ) ) ) (CELL (CELLTYPE "X_BUF" www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| (DELAYFILE (SDFVERSION "2.1") (DESIGN "res_no_share") (DATE "Mon Jan 26 20:00:09 1998") (VENDOR "Xilinx") (PROGRAM "Xilinx VERILOG SDF writer") (VERSION "M1.4.12") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS) (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1ps) (CELL (CELLTYPE "X_BUF") (INSTANCE U200) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0) (IOPATH IN OUT (2050:2050:2050) (2050:2050:2050) ) ) ) (CELL (CELLTYPE "X_BUF" www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| (DELAYFILE (SDFVERSION "2.1") (DESIGN "res_xdw_no_share") (DATE "Mon Jan 26 20:07:06 1998") (VENDOR "Xilinx") (PROGRAM "Xilinx VERILOG SDF writer") (VERSION "M1.4.12") (DIVIDER /) (VOLTAGE 5.00:5.00:5.00) (PROCESS) (TEMPERATURE 25.00:25.00:25.00) (TIMESCALE 1ps) (CELL (CELLTYPE "X_BUF") (INSTANCE U200) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0) (IOPATH IN OUT (2050:2050:2050) (2050:2050:2050) ) ) ) (CELL (CELLTYPE "X_ www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| // Xilinx Verilog produced by program ngd2ver, Version M1.4.12 // Date: Mon Jan 26 20:07:06 1998 // Design file: time_sim.nga // Device: 4005epc84-2 `timescale 1 ns/1 ps `uselib libext=.vmd module res_xdw_no_share (COND_1, A1, B1, C1, D1, Z1); input COND_1; input [7:0] A1; input [7:0] B1; input [7:0] C1; input [7:0] D1; output [7:0] Z1; wire n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149 www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| // Xilinx Verilog produced by program ngd2ver, Version M1.4.12 // Date: Mon Jan 26 20:00:09 1998 // Design file: time_sim.nga // Device: 4005epc84-2 `timescale 1 ns/1 ps `uselib libext=.vmd module res_no_share (COND_1, A1, B1, C1, D1, Z1); input COND_1; input [7:0] A1; input [7:0] B1; input [7:0] C1; input [7:0] D1; output [7:0] Z1; wire n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149 , www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| // Xilinx Verilog produced by program ngd2ver, Version M1.4.12 // Date: Mon Jan 26 20:00:09 1998 // Design file: time_sim.nga // Device: 4005epc84-2 `timescale 1 ns/1 ps `uselib libext=.vmd module res_no_share (COND_1, A1, B1, C1, D1, Z1); input COND_1; input [7:0] A1; input [7:0] B1; input [7:0] C1; input [7:0] D1; output [7:0] Z1; wire n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149 , www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| // Xilinx Verilog produced by program ngd2ver, Version M1.4.12 // Date: Mon Jan 26 20:07:06 1998 // Design file: time_sim.nga // Device: 4005epc84-2 `timescale 1 ns/1 ps `uselib libext=.vmd module res_xdw_no_share (COND_1, A1, B1, C1, D1, Z1); input COND_1; input [7:0] A1; input [7:0] B1; input [7:0] C1; input [7:0] D1; output [7:0] Z1; wire n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149 www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |