NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N OW20N= L, OW18N OW18N= H LRCO BCKO (LSB) DOUT L2 100ns L1 100ns 354ns NIPPON PRECISION CIRCUITS INC.-24 SM5844AF SM5844AF Please pay your ... | Original |
25 pages, |
400H 001H SM5844AF TSBH1 ym3613 PD0052 SM5844AF abstract |
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| Abstract: ($12) OCLK= 59ns (fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, QW20N QW20N= L, OW18N OW18N= H LRCO BCKO DOUT \ A./ A V . (LSB) _ -L2 - 100ns 354ns 100ns - 23 - OJPC NIPPON PRECISION ... | OCR Scan |
24 pages, |
LITB SM5844AF qsaa code a7n lisn baco KAE V9 YM3613 1FM2 MTI LTC 010 PD0052 SM5844AF abstract |
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| Abstract: /354ns Cette liste n'est pas exhaustive, d'autres longueurs ou exécutions peuvent être livrées sur , 101 A004-3/32ns VL 101 A004-3/64ns VL 101 A004-3/128ns VL 101 A004-3/152ns VL 101 A004-3/354ns ... | Original |
28 pages, |
rg-400 mil-c-17 MIL-C-17 CuZn39Pb2 A0043 A004 a0041 29020 Crimp Tool datasheet abstract |
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| Abstract: 100ns L1 100ns 156ns (example 2) OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N OW20N= L, OW 1 8 N = H LRCO BCKO (LSB) DOUT L2 100ns L1 100ns 354ns NIPPON ... | Original |
26 pages, |
ym3613 SM5844AF 400H 001H PD0052 SM5844AF abstract |
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| Abstract: /354ns Cette liste n'est pas exhaustive, d'autres longueurs ou exécutions peuvent être livrées sur , 101 A004-3/32ns VL 101 A004-3/64ns VL 101 A004-3/128ns VL 101 A004-3/152ns VL 101 A004-3/354ns ... | Original |
28 pages, |
MIL-P-14078 MIL-C-17 cinch coaxial A004 29020 Crimp Tool BNC crimp RG 174 Coaxial Connectors datasheet abstract |
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| Abstract: volume Sound output CLK 8 clock CLK 8 326ns @ CLK=24.576MHz 326ns@CLK=24.576MHz 354ns @ CLK=22.5792MHz 354ns@CLK=22.5792MHz Fig.12 Relation between PWM Reset and PWMEN, PWM Output 5.4 BPZ ... | Original |
24 pages, |
SSOP44 CP1201 CP1201 usb CS10 CS29 CABLE IEC60958 NJU26060 NJU26060V AES17 CS29 Coaxial Cable NJU26060 abstract |
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| Abstract: 51PWM 326ns @ CLK=24.576MHz 354ns @ CLK=22.5792MHz 12 PWM PWMEN,PWM Ver.2009-12-16 - 21 - ... | Original |
29 pages, |
SYS-2722 SSOP44 NJU26060 IEC60958 CP1201 usb CP1201 AES17 NJU26060V NJU26060 abstract |
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| Abstract: /354ns Cette liste n'est pas exhaustive, d'autres longueurs ou exécutions peuvent être livrées sur , 101 A004-3/32ns VL 101 A004-3/64ns VL 101 A004-3/128ns VL 101 A004-3/152ns VL 101 A004-3/354ns ... | Original |
28 pages, |
OU CINCH MIL-C-17 A004 29020 Crimp Tool datasheet abstract |
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| Abstract: tSYS 22ns, 44ns, 89ns, 177ns, 354ns, 708ns -2- CXD5091AGG CXD5091AGG 12CXD5091AGG 12CXD5091AGG U T R P N M ... | Original |
31 pages, |
CXD5091AGG CXD5091A CXD5091AGGLSI CXD5091AGG abstract |
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| Abstract: F9222 , 177ns, 354ns or 708ns -2- CXD5091GG CXD5091GG Pin Configuration Fig. 1 and Fig. 2 show the package of ... | Original |
31 pages, |
CXD5091GG CXD5091GG abstract |
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| Abstract: - 315 - 74843 9-Bit 3-State D-Latches with Common Preset and Common Clear A QOE CLR PR D G 1, II, If, II QOE -CLR V 3 I-14| |Sj |6| |_7| [8j |_9j QOj [llj |12[ OUTPUT W D1 D2 D3 D4 DS D6 D7 D8 PR GND o 74573 9 Bit® (7' ')t7K 7 'I 7 ft) o74844l±|5ll:f>S ... | OCR Scan |
1 pages, |
Latches 74373 74373 74573 datasheet abstract |
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| Abstract: NEC ELECTRONICS INC blE ]> â- h42?525 D03540b bBD HINECE /iPB100A484 i^MYW 4,096 x 4-Bit NEC Electronics Inc. 100K ECL RAM Description The ¿tPB100A484 is a very high-speed 100K interface ECL RAM organized as 4K words by 4 bits and designed with open emitter outputs (noninverted). it is available in 28-pin cerdip or flatpack packages. Features Pin Configurations 28-Pin Cerdip 4096 word x 4-bit organization 100K ECL interface Full voltage and temperature compensation Open emitter outputs ( ... | OCR Scan |
5 pages, |
nec A2C datasheet abstract |
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| Abstract: E C ELECTRONICS INC ZVfi'C NEC Electronics Inc. blE D b427555 DD3SMD1 OST «NECE ¿iPB100484A 4,096 x 4-BIT 100K ECL RAM Description The ftPB100484A is a very high-speed 100K interface ECL RAM. It is organized as 4,096 words by 4 bits with noninverted, open-emitter outputs and low power consumption. Two access time versions are available: 5 ns and 7 ns maximum. The juPB100484A is available in a hermetic, 400-mil, 28-pin cerdip or 28-pin ceramic flat-pack. Features Pin Configurations 28-Pi ... | OCR Scan |
5 pages, |
IPB100484AB-5 DD354 datasheet abstract |
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| Abstract: fax id: 5210 V CYPRESS CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K 32K/64K/128K x 8/9 ronous Dual Port Static RAM Synch Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices - 32K x 8/9 organizations (CY7C09079V/179V CY7C09079V/179V) - 64K x 8/9 organizations (CY7C09089V/189V CY7C09089V/189V) - 128K x 8/9 organizations (CY7C09099V/199V CY7C09099V/199V) • 3 Modes - Flow-Through - Pipelined - Burst • Pipelined output mode on both ports a I lows fast ... | OCR Scan |
16 pages, |
hcn 73 CY7C09079V/89V/99V CY7C09179V/89V/99V 32K/64K/128K CY7C09079V/89V/99V abstract |
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| Abstract: fax id: 5211 V CYPRESS CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K 16K/32K/64K x 16/18 ronous Dual Port Static RAM Synch Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 6 Flow-Through/Pipelined devices - 16K x 16/18 organization (CY7C09269V/369V CY7C09269V/369V) - 32K x 16/18 organization (CY7C09279V/379V CY7C09279V/379V) - 64K x 16/18 organization (CY7C09289V/389V CY7C09289V/389V) • 3 Modes - Flow-Through - Pipelined - Burst • Pipelined output mode on both ports allows fas ... | OCR Scan |
16 pages, |
hcn 73 CY7C09269V/79V/89V CY7C09369V/79V/89V 16K/32K/64K CY7C09269V/79V/89V abstract |
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| Abstract: CY7C4808V25 CY7C4808V25 CY7C4806V25 CY7C4806V25 CY7C4804V25 CY7C4804V25 5/0251 ADVANCE INFORMATION 2.5V 4K/16K/64K 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching Features · Bus matching on both ports: x80, x40, x20, x10 · Free-running CLKA and CLKB. Clocks may be asynchronous or coincident · CY standard or First-Word Fall-Through modes · Serial and parallel programming of Almost Empty/Full flags, each with 3 default values (8, 16, 64) · Master and Partial reset capability · Retransmit capability · All I ... | Original |
5 pages, |
CY7C4808V25 CY7C4806V25 CY7C4804V25 A790 4K/16K/64K CY7C4808V25 abstract |
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| Abstract: -- CY7C4808V25 CY7C4808V25 ST. CY7C4806V25 CY7C4806V25 y CYPRESS ÂD¥ÂNCE iNFORMATjlON CY7C4804V25 CY7C4804V25 ~ 2.5V 4K/16K/64K 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching Features • High-speed, low-power, unidirectional, first-in first-out (FIFO) memories w/bus matching capabilities • 64K x 80 (CY7C4808V25 CY7C4808V25) • 16K x 80 (CY7C4806V25 CY7C4806V25) • 4K x 80 (CY7C4804V25 CY7C4804V25) • 2.5V ±125 mV power supply • Fabricated using Cypress 0.21-micron CMOS Technology for optimum speed/power • Individual clock frequency up to 200 MHz (5 ns ... | OCR Scan |
5 pages, |
CY7C4808V25 CY7C4806V25 CY7C4804V25 LBEH 4K/16K/64K CY7C4808V25 abstract |
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| Abstract: NEC ELECTRONICS INC blE ]> â- b457S25 0D35342 0D35342 710 «NECE JJPB10A484 JJPB10A484 4,096 x 4-Blt NEC Electronics Inc. 10K ECL RAM 7-Hh-aS-otf Description The juPB10A484 is a very high-speed 10K interface ECL RAM organized as 4,096 words by 4 bits with nonin-verted, open-emitter outputs. Two versions with access times of 5 ns and 7 ns maximum are available. The ¿iPB10A484 is packaged in a hermetic, 400-mil, 28-pin cerdip or 28-pin ceramic flatpack. Features ° 4,096-word x 4-bit organization â-¡ 10K ECL int ... | OCR Scan |
6 pages, |
CERAMIC FLATPACK 6165A 6164B 0D35342 JJPB10A484 0D35342 abstract |
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| Abstract: NEC ELECTRONICS INC blE ]> â- b427525 0Q3S33b 4T7 MNECE %TM4*f /tPB10484A i^f-E/ W 4,096 x 4-BIT NEC Electronics Inc. 10K ECL RAM Description The ¿tPB10484A is a very high-speed 10K interface ECL RAM. It is organized as 4,096 words by 4 bits and designed with noninverted, open-emitter outputs and low power consumption. Two versions with access times of 5 or 7 ns maximum are available. The ¿lPB10484A is packaged in a hermetic, 400-mii, 28-pin cerdip or 28-pin ceramic flatpack. Features â-¡ 4, ... | OCR Scan |
6 pages, |
TA-75 nec A2C HPB10484AD-5 HPB10484AB-5 D-03C datasheet abstract |
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| Abstract: SAW Bandpass Filter 271102B 271102B 1. Features IF Bandpass Filter High Attenuation Single-Ended Operation DIP Package Maximum Storage Temperature Range : -40 ~ 85 Electrostatics Sensitive Device (ESD) Package : D3512 D3512 2.5�2 25.4�2 7.6�2 0.45�05 5.5max 6.0max ITF 08A001 08A001 271102B 271102B 70-11.0M 35.1�5 12.8�5 2.5�2 2. Package Dimension Pin Configuration 1 5 Output 2, 4 Ground 3, 6 Case ground Dimensions shown are nominal in millimeters Base : Fe(SP ... | Original |
5 pages, |
D3512 271102B 271102B abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Delay for this design is: 1.354 ns The Average Connection Delay on critical nets is: 0 www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| Delay for this design is: 1.354 ns The Average Connection Delay on critical nets is: 0 www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| Delay for this design is: 1.354 ns The Average Connection Delay on critical nets is: 0 www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| Delay for this design is: 1.354 ns The Average Connection Delay on critical nets is: 0 www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| XDelay: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:55:47 1994 XDelay Report File: Design: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB12H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| |* | Intersil ISL32179E ISL32179E ISL32179E ISL32179E | | 24 PIN QFN, FOR VCC=VL=3.3V | |* | [IBIS Ver] 3.2 [File name] isl32179e3v3.ibs [File Rev] 2.0 [Date] January 20,2011 [Source] Data used in this IBIS mo www.datasheetarchive.com/files/intersil/documents/isl3/isl32179e3v3.ibs |
Intersil | 10/12/2011 | 40.59 Kb | IBS | isl32179e3v3.ibs |
| XDelay: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:55:47 1994 XDelay Report File: Design: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB12H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:55:47 1994 XDelay Report File: Design: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB12H.XRP) |
Xilinx | 09/04/1997 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:55:47 1994 XDelay Report File: Design: CLDB12H CLDB12H CLDB12H CLDB12H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/49705392-987186ZC/wcd02ec8.zip (CLDB12H.XRP) |
Xilinx | 13/07/1998 | 193.16 Kb | ZIP | wcd02ec8.zip |
| .5ns 990mV/86.75ns 1.6V/46.8ns dV/dt_r 1.31V/358ns 1.00V/359ns .63V/354ns R www.datasheetarchive.com/files/on_semiconductor/simulation-models/24c08td_22v_rev_k.ibs |
On Semiconductor | 13/03/2012 | 35.11 Kb | IBS | 24c08td_22v_rev_k.ibs |