NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SN74ACT534NSR | Texas Instruments | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85 | 
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| SN74AC534NSR | Texas Instruments | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85 |
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| SN74ACT534NSRG4 | Texas Instruments | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85 |
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| SN74AC534NSRE4 | Texas Instruments | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO -40 to 85 |
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| SN74ALS1034NSR | Texas Instruments | Hex Noninverting Drivers 14-SO 0 to 70 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: dimension 0.1~1.3ns 0.295 max. 1.04 max. 1.4~2.5ns 0.400 max. 1.04 max. 2.6~3.4ns , 2.8 ~ 3.4ns 3.6 ~ 4.8ns 5.0ns 0.2ns steps -0.05/+0.1ns �1ns 5.5 ~ 10.0ns 0.5ns steps ... | Original |
2 pages, |
marking A00 DL02M520 DL02M520 abstract |
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| Abstract: MAX2550 Max. 0.8V ~ 2 V, 4.5-5.5Vdd, CL = 15 : 0.9ns Max. 0.2V ~ 0.8 Vdd, 4.5-5.5Vdd, CL = 50 : 3.4ns Max. ... | Original |
1 pages, |
OSC74 OSC74 abstract |
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| Abstract: ~ 2 V, 4.5-5.5Vdd, CL = 15 : 0.9ns Max. 0.2V ~ 0.8 Vdd, 4.5-5.5Vdd, CL = 50 : 3.4ns Max. 0.2V ~ 0.8 ... | Original |
1 pages, |
OSC71 OSC72 OSC72 abstract |
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| Abstract: 0.8V ~ 2 V, 4.5-5.5Vdd, CL = 15 : 0.9ns Max. 0.2V ~ 0.8 Vdd, 4.5-5.5Vdd, CL = 50 : 3.4ns Max. 0.2V ... | Original |
1 pages, |
ttl 7008 oscillator 50mhz DIP OSC73 OSC73 abstract |
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| Abstract: 200 200 200 400 400 400 TYPICAL RISE TIME 4.0nS 4.0nS 4.0nS 4.0nS 3.4nS 3.4nS 3.4nS 3.4nS 2.3nS 2.3nS 2.3nS 6.5nS 6.5nS 6.5nS SCREENING LEVEL Industrial Mil-PRF-38534 Class H ... | Original |
6 pages, |
RS170 MSK1902-4 MSK1902-2 MSK1902-0 ac 440 v to dc 110v converter 5962-8997201HX 1902 transistor 1902 110v to 5v dc schematic ISO-9001 ISO-9001 abstract |
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| Abstract: FLEX 10KA-1 10KA-1: TECHNICAL BRIEF 38 FEBRUARY 1998 FLEX®10KA-1 10KA-1 FLEX 10K-3 10K-3 PLD FLEX 10KA-1 10KA-1 FLEX 10KA-1 10KA-1 FLEX 10KA-1 10KA-1 FLEX 10KA-1 10KA-1 FLEX 10KA-1 10KA-1 (1) FLEX 10KA-1 10KA-1 16 FIRFinite Impulse Response 119MHz a16450 UART Universal Asynchronous Receiver/Transmitter MegaCoreTM 31 MHz 16 3.4ns 256 - 8 RAM 143MHz 256 - 8 RAM 106MHz (1) Source: Altera Applications Engineering FLEX 10KA-1 10KA-1 XC4000XL-09 XC4000XL-09 FLEX 10KA-1 10KA-1 FLEX 10KA-2 10KA-2 Xilinx ... | Original |
4 pages, |
XC4062XL XC4000XL 10KA-1 10KA1 10KA-1 abstract |
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| Abstract: is between 25ns and 34ns, which is less than the minimum 35ns required by some physical layer ... | Original |
2 pages, |
77V011 77V011 abstract |
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| Abstract: ,PA C,M 5V Now 2543 54/74FCT162373T 54/74FCT162373T 16-bit Non-inverting Latch 3.4ns PV,PA , C 5V Now 2618 54/74FCT162543T 54/74FCT162543T 16-bit Non-inverting Latched Transceiver 3.4ns PV , PV,PA C,M 5V Now 2556 54/74FCT162841T 54/74FCT162841T 20-bit Non-Inverting Latch 3.4ns PV,PA , Non-inverting Latch 3.4ns PV,PA C,M 5V Now 2542 54/74FCT16374T 54/74FCT16374T 16-bit non-inverting , Non-inverting Latched Transceiver 3.4ns PV,PA C,M 5V Now 2544 54/74FCT166244T 54/74FCT166244T 16-bit ... | Original |
14 pages, |
29FCT520T 29FCT52T 7201 fifo 74FCT88915T 79S381 C 2577 transistor 1K x 8 static ram SRAM 35ns datasheet and application 7217 Octal latch open PY 88 MQUAD 74FST3390 dual-port RAM 10A474 10A484 10A474 abstract |
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| Abstract: 5.1ns 5.0ns 5.0ns 5.6ns 3.9ns 5.8ns 5.8ns 3.2ns 3.2ns 3.2ns 3.6ns 3.8ns 3.4ns 3.7ns 3.2ns 3.2ns 3.2ns 3.8ns 3.8ns 4.2ns 3.4ns 3.6ns 3.8ns 3.8ns 5.5ns PGA SO,P,PY SO,P Q,SO,P,PY , /Register Speeds 4.4ns 3.2ns 3.4ns 3.7ns 3.2ns 3.2ns 5.2ns 3.8ns 3.7ns 5.8ns 4.1ns 4.1ns 4.6ns 4.2ns 5.2ns 4.6ns 4.1ns 5.4ns 3.4ns 3.7ns 4.4ns 6.3ns 4.1ns 5.0ns 3.8ns 3.8ns 3.4ns 3.2ns 3.8ns 3.8ns 4.4ns 3.2ns 3.4ns 3.7ns 7.8ns 6.9ns 3.6ns 3.6ns 3.8ns 3.8ns 4.2ns 4.3ns ... | Original |
8 pages, |
SRAM 64Kx1 29FCT520T 29FCT52T 79S381 7M4084 7MPV6214 8kx9 sram d 2689 datasheet and application 7217 Octal latch open c 3198 transistor MQUAD ram 6116 6116 RAM 10A474 10A484 10A474 abstract |
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| Abstract: OKI 2008 10 1 OKI OKI OKI 2008 10 1 OKI 193-8550 550-1 http://www.okisemi.com/jp/ J2L0028-17-Y1 J2L0028-17-Y1 1998 1 MSM514212 MSM514212 l 1997 9 ¡ MSM514212 MSM514212 5,048-Word-8-Bit n MSM5142125 MSM5142125,048-8FIFO1CMOS RAM MSM5142121 MSM5142121 28nsNTSCPALSECAM8fsc 405,048VTRIDTVEDTV 048VTRIDTVEDTV HDTV1K-8 n l 5,048-8 l 405,048 l TTL l 28ns l l VCC5V ± 10% l l 28400milZIP ZIP28-P-400-1 ZIP28-P-400-1.27 MSM514212-xxZS xx n MSM514212-28 MSM514212-28 28ns 28ns 230mW MSM514212-34 MSM514212-34 34ns 34ns ... | Original |
14 pages, |
MSM514212 datasheet abstract |
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| Abstract: HD10117 HD10117 Dual 2-wide 2-3-input OR-AND/OR-ANP-INVERT Gates The HD10117 HD10117 » designed for use as a data control The E input (pin 9) is the common input of dual, of digital Multiplexer, data distribution and etc. gates. I PIN ARRANGEMENT (Top View) IDC CHARACTERISTICS (VEe=-5.2V, Ta-30~ + 85'C) Test Condition IAC CHARACTERISTICS ( + Test Condition Item Symbol Propagai ion 1 PL» Delay Time t pa i Itlh Rise/Fall Time Rt = 50n min typ max Unit -30'C 1.4 - 3.9 25"C 1.4 2.3 3.4 ns ... | OCR Scan |
1 pages, |
HD10117 HD10117 abstract |
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| Abstract: HD10117 HD10117 Dual 2-wide 2-3-input OR-AND/OR-ANP-INVERT Gates The HD10117 HD10117 » designed for use as a data control The E input (pin 9) is the common input of dual. of digitai Multiplexer, data distribution and etc. gates. IPIN ARRANGEMENT (Top View) IDC CHARACTERISTICS (VEe=-5.2V, Ta-30~+ 85'C ) Test Condition IAC CHARACTERISTICS ( + Test Condition Item Symbol Propagai ion 1 PL» Delay Time t pu 1 Itlh Rise/Fall Time Rt = 50n min typ max Unit -30'C 1.4 - 3.9 25"C 1.4 2.3 3.4 ns 85'C 1.4 - 3.8 -30 ... | OCR Scan |
1 pages, |
HD10117 HD10117 abstract |
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| Abstract: 74574 74364 to CO CLOCK s® njiiiiuiiinjiiiii^ OUTPUT IQ 10 ID ÍO 10 o 74374 öOih tili ír-kBl TH u-^WHi tl1£l± 4 í'S < L/j^-f-7- (M0S¥«-í>í'-7i - Xffl) VCC »ti 74364 iE mtn H l" ... | OCR Scan |
1 pages, |
74575 74534 74364 74374 datasheet abstract |
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| Abstract: NJU6397D NJU6397D 125MHz IC NJU6397D NJU6397D 100MHz 125MHz C-MOS IC NAND 6mA(2.5V ) C-MOS 2.252.75V IOH/IOL=6mA @VDD=2.5V C-MOS / NJU6397DC-X NJU6397DC-X Thin-Chip CONT XT XT VSS VDD FOUT NJU6397 NJU6397 D Cg/Cd No 1 CONT X -178 Y 231 100125MHz f0 8/9pF 2 3 XT XT -178 -178 77 -77 4 5 8 VSS FOUT VDD -178 206 206 -231 -231 231 : [um] :0.7x0.75mm (C-D): 200�um (C-L) ... | Original |
4 pages, |
NJU6397D NJU6397 NJU6397DC-X NJU6397D abstract |
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| Abstract: 74698 BCD Synchronous Up/Down Counters -303- 3 STATI OUTPUTS VÇÇ MM OA I_I_LJ_1_1_I KCS o* Oa oc Oo _U J J J ï „ ^ U>' COUNTER »»CD fNA«l.( COUNTER RfCIST CNO OOWK CLOCK >74I68i/jii74169c 7 'J 7*1Jil*. 74175, 74257 ¿•ill ^Wh-^f: 9 if 74696 BCD U/D JIM.JIBI 7'J T 74697 16j(L U/D JIM«? >i r 74698 BCD U/D MtBl? 1)7 74699 16j(i U/D |.-J«i ? -) r ENA P-- LOAD- ENA T-- »STATE OUAORUPLE MINE TO « LINE MULTIPLEXER J*s * AJJ IN tan OUT H LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT ... | OCR Scan |
1 pages, |
74697 74257 74175 datasheet abstract |
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| Abstract: -107- 74136 Quad 2 Input O.C. Ex-OR 4A «V m » 3V 1A IB IV ZA » 1Y fll Y = A©B = ÄB + AB 0 7486t-rv o u- 1 9 'S O O 30 -O-ED Of- fktt- ? BO-ft(tifi /A = H. SW = ON â fziì \ U = L. SW = 0FFr-tt) OAND-tieTANDMBA-Bt'j O 74 L S 266 # m. 07486#W «S Ml IN tati OUT N LS ALS ALSK F S AS AC ACT HC HCU HCT BC BCT mti tpd max LA-H Î L-H t la 30 50 20 12.5 45 34 ns tpd nax L/H-L 1 H-*L 1 50 10 15 7.5 12 45 26 ns tpd lax H/H-L 1 L-*H t 22 30 12 20 12.5 8 14 ns tpd - ... | OCR Scan |
1 pages, |
74136 BC 545 7486 74266 datasheet abstract |
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| Abstract: - 300 - 74693 Binary Synchronous Counters 3 STATE OUTPUTS •iLjiirtimrtirtiJtJtin!^ ENABLE "EGlST I O 74160-741631-74175. 74257 ïk&Mîh •tì-fc ? 4 -7° 74690 BCD r 74691 i6 m JIM.JM? r 74692 BCD kJKB 7 ') r 74693 16 iff [a] IBI? 'IT CLEAR > CLOCK Lr 3STATE QUADRUPLE 2 LINE TO 1 LINE MULTIPLEXER me Xfl IN ayj OUT N LS »LS ALSK F S AS AC ACT HC HCU HCT BC BCT m fmax - n 20 20 MHz tw ID n 25 19 ns tsu - n D-ENT JO 1 38 ns tsu in n U/ ... | OCR Scan |
1 pages, |
ttl 74175 74691 74690 74693 74160 74175 74257 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Xilinx Answer #5272 : LogiCORE PCI32 PCI32 PCI32 PCI32 4000XLT 4000XLT 4000XLT 4000XLT: Incorrect 'MIN' clock delay value used to compute the setup time Answers Database LogiCORE PCI32 PCI32 PCI32 PCI32 4000XLT 4000XLT 4000XLT 4000XLT: Incorrect 'MIN' clock delay value used to compute the setup time Record #5272 Product Family: Documentation www.datasheetarchive.com/files/xilinx/docs/rp00018/rp01892.htm |
Xilinx | 29/02/2000 | 4.23 Kb | HTM | rp01892.htm |
| Xilinx Answer #5272 : LogiCORE PCI32 PCI32 PCI32 PCI32 4000: Incorrect 'MIN' clock delay value used to compute the setup time Answers Database LogiCORE PCI32 PCI32 PCI32 PCI32 4000: Incorrect 'MIN' clock delay value used to compute the setup time Record #5272 Product Family: Documentation Product Line: PCI Apps Problem Title: LogiCORE PCI32 PCI32 PCI32 PCI32 4000: Incorrec www.datasheetarchive.com/files/xilinx/docs/wcd0004a/wcd04a43.htm |
Xilinx | 16/02/1999 | 3.65 Kb | HTM | wcd04a43.htm |
| % maximum duty cycle Synchronisation capability to 6MHz Current sense delay of 34ns available through synchronisation. The high speed operation of the MIC9131 MIC9131 MIC9131 MIC9131 is made safe by the very fast, 34ns response from current sense to output, minimizing power dissipation in a fault condition www.datasheetarchive.com/files/micrel/products/products/mic9131.shtml |
Micrel | 26/06/2002 | 9.6 Kb | SHTML | mic9131.shtml |
| XDelay: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:51:33 1994 XDelay Report File: Design: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/82155996-960566ZC/xapp002v.zip (CLDB10H.XRP) |
Xilinx | 05/09/1996 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:51:33 1994 XDelay Report File: Design: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/8224988-988363ZC/wcd036f0.zip (CLDB10H.XRP) |
Xilinx | 12/02/1999 | 193.16 Kb | ZIP | wcd036f0.zip |
| XDelay: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:51:33 1994 XDelay Report File: Design: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/85048902-996229ZC/xapp002v.zip (CLDB10H.XRP) |
Xilinx | 09/04/1997 | 193.16 Kb | ZIP | xapp002v.zip |
| XDelay: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6), XDELAY 5.0.0, Thu Sep 1 08:51:33 1994 XDelay Report File: Design: CLDB10H CLDB10H CLDB10H CLDB10H.LCA (3030APC84-6 3030APC84-6 3030APC84-6 3030APC84-6) Program: XDELAY 5.0.0 Speedsfile: File 3030a.spd, Version 3000A.1, Revision 3030A.4 Xdelay path report options: From all. To all. Output will be sorted by decreasing path delays. Report file may include Clock To Setup paths. A maximum of 20 paths will be reported. - Paths not u www.datasheetarchive.com/download/49705392-987186ZC/wcd02ec8.zip (CLDB10H.XRP) |
Xilinx | 13/07/1998 | 193.16 Kb | ZIP | wcd02ec8.zip |
| to the SYNC pin. The high speed operation of the MIC9130 MIC9130 MIC9130 MIC9130 is made safe by the very fast, 34ns response www.datasheetarchive.com/files/micrel/products/products/mic9130.shtml |
Micrel | 26/06/2002 | 8.1 Kb | SHTML | mic9130.shtml |
| ), + TRN_HL, DELAY(10NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS ), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS,70NS) + ) + } + Y3_O NS,34NS,50NS), + DELAY(-1,52NS,70NS) + ) + } + Y4_O = { + CASE ), + TRN_HL, DELAY(10NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS,70NS www.datasheetarchive.com/files/spicemodels/misc/74l.lib |
Spice Models | 19/12/2001 | 54.03 Kb | LIB | 74l.lib |
| ), + TRN_HL, DELAY(10NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS ), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS,70NS) + ) + } + Y3_O NS,34NS,50NS), + DELAY(-1,52NS,70NS) + ) + } + Y4_O = { + CASE ), + TRN_HL, DELAY(10NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS NS,44NS,60NS), + TRN_LH, DELAY(10NS,34NS,50NS), + DELAY(-1,52NS,70NS www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74l.lib |
Spice Models | 29/07/2012 | 54.01 Kb | LIB | 74l.lib |