NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SMJ320C6203 SMJ320C6203 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS033 SGUS033  FEBRUARY 2002 D High-Performance Fixed-Point Digital D D D D D Signal Processor (DSP)  SMJ320C62x  5-ns Instruction Cycle Time  200-MHz Clock Rate  Eight 32-Bit Instructions/Cycle  1600 Million Instructions Per Second (MIPS) 429-Pin Ball Grid Array (BGA) Package (GLP Suffix) VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core  Eight Highly Independent Functional Units:  Six Arithmetic Lo ... | Original |
80 pages, |
SMJ320C6203 PCI2040 jito-2 C6000 SGUS033 SMJ320C6203 abstract |
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| Abstract: TMS320C6203B TMS320C6203B, TMS320C6203C TMS320C6203C FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS086G SPRS086G  JANUARY 1999  REVISED JANUARY 2002 D D D D D Signal Processor (DSP)  TMS320C62x  4-, 3.33-ns Instruction Cycle Time  250-, 300-MHz Clock Rate  Eight 32-Bit Instructions/Cycle  2000, 2400 MIPS C6203B C6203B and C6202/02B C6202/02B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 C6204 GLW BGA Package VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core  Eight Highly Independent Fu ... | Original |
101 pages, |
TMS320C6203C TMS320C6203B diode byt 52m 352-PIN 114 XBE 10000 SPRS086G TMS320C6203B abstract |
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| Abstract: TMS320C6203B TMS320C6203B, TMS320C6203C TMS320C6203C FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS086F SPRS086F  JANUARY 1999  REVISED SEPTEMBER 2001 D D D D D Signal Processor (DSP)  TMS320C62x  4-, 3.33-ns Instruction Cycle Time  250-, 300-MHz Clock Rate  Eight 32-Bit Instructions/Cycle  2000, 2400 MIPS C6203B C6203B and C6202/02B C6202/02B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 C6204 GLW BGA Package VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core  Eight Highly Independent ... | Original |
90 pages, |
TMS320C6203C TMS320C6203B 352-PIN SPRS086F TMS320C6203B abstract |
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| Abstract: SMJ320C6203 SMJ320C6203 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS033 SGUS033 - FEBRUARY 2002 D High-Performance Fixed-Point Digital D D D D D Signal Processor (DSP) - SMJ320C62x - 5-ns Instruction Cycle Time - 200-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 1600 Million Instructions Per Second (MIPS) 429-Pin Ball Grid Array (BGA) Package (GLP Suffix) VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core - Eight Highly Independent Functional Units: - Six Arithmetic Lo ... | Original |
82 pages, |
SMJ320C6203 PCI2040 C6000 SGUS033 SMJ320C6203 abstract |
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| Abstract: TMS320C6711 TMS320C6711, TMS320C6711B TMS320C6711B, TMS320C6711C TMS320C6711C FLOATINGPOINT DIGITAL SIGNAL PROCESSORS SPRS088O SPRS088O - FEBRUARY 1999 - REVISED NOVEMBER 2005 D Excellent-Price/Performance Floating-Point D D D D D Digital Signal Processors (DSPs): TMS320C67x (C6711 C6711, C6711B C6711B and C6711C C6711C) - Eight 32-Bit Instructions/Cycle - 100-, 150-, 167-, 200-MHz Clock Rates - 10-, 6.7-, 6-, 5-ns Instruction Cycle Time - 600, 900, 1000, 1200 MFLOPS Advanced Very Long Instruction Word (VLIW) C67x DSP Core - Eight ... | Original |
132 pages, |
TMS320C6711C TMS320C6711B TMS320C6711 SPRS088O C6711 C6711B C6711C TMS320C6711 abstract |
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| Abstract: TMS320C6713 TMS320C6713 FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS186L SPRS186L - DECEMBER 2001 - REVISED NOVEMBER 2005 D Highest-Performance Floating-Point Digital D D D D D Signal Processor (DSP) - Eight 32-Bit Instructions/Cycle - 32/64-Bit Data Word - 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates - 4.4-, 5-, 6-Instruction Cycle Times - 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS - Rich Peripheral Set, Optimized for Audio - Highly Optimized C/C+ Compiler - Extended ... | Original |
148 pages, |
TMS320C6713B TMS320C6713 IEC60958-1 C67x AC97 SPRS186L TMS320C6713 abstract |
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| Abstract: SMJ320C6203 SMJ320C6203 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS033 SGUS033  FEBRUARY 2002 D High-Performance Fixed-Point Digital D D D D D Signal Processor (DSP)  SMJ320C62x  5-ns Instruction Cycle Time  200-MHz Clock Rate  Eight 32-Bit Instructions/Cycle  1600 Million Instructions Per Second (MIPS) 429-Pin Ball Grid Array (BGA) Package (GLP Suffix) VelociTI Advanced Very-Long-InstructionWord (VLIW) C62x DSP Core  Eight Highly Independent Functional Units:  Six Arithmetic Lo ... | Original |
81 pages, |
SMJ320C6203 PCI2040 C6000 SGUS033 SMJ320C6203 abstract |
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| Abstract: Waveforms FIGURE 32. VOUT Response to Load Current Step Figure 33Figure 35 Figure 37 4 1 ... | Original |
30 pages, |
LM2586T-ADJ TA07B LM2586T-12 LM2586S-12 LM2586 flyback transformer 12v dc 12V to 24V boost ic regulator 12v 30a PE-68482 3A Step top Switching voltage Regulator D1N5820 24v to 5V 2A SW regulator RL-5532 LM2586 abstract |
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| Abstract: 34 "Switchers Made Simple® " (Version 4.3 ) Figure 33Figure 35 Figure 37 4 ... | Original |
27 pages, |
T05D ic regulator 48v 30a LM2585 LM2585S-12 LM2585S-ADJ LM2585T-12 LM2585T-ADJ 3A Step top Switching voltage Regulator LM2585-12 LM2585-ADJ LM2585 abstract |
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| Abstract: TMS320C6204 TMS320C6204 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS152A SPRS152A  OCTOBER 2000  REVISED JUNE 2001 D D D D D Signal Processor (DSP)  TMS320C6204 TMS320C6204  5-ns Instruction Cycle Time  200-MHz Clock Rate  Eight 32-Bit Instructions/Cycle  1600 MIPS C6204 C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03 C6202/02B/03 GLS BGA Package VelociTI Advanced Very-Long-InstructionWord (VLIW) TMS320C62x DSP Core  Eight Highly Independent Functional Units:  Six ALUs (32-/40-Bit ... | Original |
81 pages, |
TMS320C6204 TMS320C6203 TMS320C6000 k 55 c5 v1 SPRS152A C6204 C6202/02B/03 TMS320C6204 abstract |
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| Abstract: RGG5C : 3 0 0 GHMC + X-GX F'TC : , 7X DC â-¡ PEPATI N G F: A N G E : - G G T G 10 0 C CTGRAGG RANGE :-05 TG 15 0 C ^THERMAL TIME CE NG T A NT: 30 G EC MA X * El I G GI F' A T I â-¡ N C G N G T A N T ! G , 5 n W / C M I N POWER RATI N G ! , G 5 W G 2 5 C., DERATE TE 100 n As tested pei- M I L-R-GGG43 L-R-GGG43 May vary dependent on nonniing PECICTANCO MULTIPLIER RFCICTANCO TOLERANCE -00 5 0 0 17 f 1 -1 G 73 0 1 0 il 33 0 4 a G 1 , 0 0 D Gl 1,13 4 LJ /G 1,40 6 1 il il 1 , 33 FIG, 1: PERFORMANCE CHARACTE ... | OCR Scan |
1 pages, |
L-R-GGG43 L-R-GGG43 abstract |
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| Abstract: C B A .453 11.5 D REV .091 2.3 DATE DRN DRAWING RELEASE ECN 06-229 ECN 06-233 CO2010372 CO2010372 CO2010405 CO2010405 CO2010642 CO2010642 05/10/06 11/10/06 03/09/08 23/09/08 01/05/09 NJB NJB SF TC SF 02 03 04 05 1 .078 2 .578 14.7 .571 14.5 .07 1.8 1 .482 12.2 MODIFICATION 01 .591 15 .508 12.9 F E FIG 1 FIG 3 .701 17.8 FIG 2 .618 15.7 2 .972 24.7 .832 21.1 .089 2.3 .102 2.6 2 NOTE 1) OTHE ... | Original |
1 pages, |
RMS-19 BPF-A414-19NT datasheet abstract |
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| Abstract: Pulse* FEE A TECHNITROL COMPANY FE 2X Series Current compensated Noise Supression Chokes Inductances compensées d'antiparasitage Electrical spécification at 25°C Key Features Caractéristiques Comply with VDE 565-2 En conformité avec la norme VDE 565-2 UL recognized (94V0) Pièce reconnue UL (94V0) Nominal voltage 250 VAC Tension nominale 250 V alternatif Withstanding voltage: 1500 VAC 50 Hz during 60 seconds minimum Tension essai de bobinage : 1500 VAC / 50 Hz> 60 sec Note Remarque Additionnai va ... | OCR Scan |
3 pages, |
triple chokes c 565-2 3X050-10-7 27 mH, 1.5 A, Common Mode Choke VDE 565-2 565-2 vde datasheet abstract |
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| Abstract: NO. FUZETEC TECHNOLOGY CO., LTD. PQ08-101E PQ08-101E Product Specification and Approval Sheet Version 5 Page 1/3 Radial Leaded PTC Resettable Fuse : FRG Series 1. Summary (a) RoHS Compliant (Lead Free) Product (b) Applications : Wide variety of electronic equipment (c) Product Features : Very Low resistance, Very High hold current, Solid state, Radial leaded product ideal for up to 16V (d) Operation Current : 2.5A~14.0A (e) Maximum Voltage : 16V (f) Temperature Range : -40 to ... | Original |
3 pages, |
Fuzetec FRG800-16F FRG300 E211981 RG300F FRG900-16 FRG250-16F Fuzetec frg250 FRG250 PQ08-101E PQ08-101E abstract |
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| Abstract: AP2762R-A AP2762R-A RoHS-compliant Product Advanced Power Electronics Corp. N-CHANNEL ENHANCEMENT MODE POWER MOSFET 100% Avalanche Test Fast Switching Characteristics Simple Drive Requirement BVDSS 650V RDS(ON) D 1.4 ID G 7A S Description AP2762 AP2762 series are specially designed as main switching devices for universal 90~265VAC 265VAC off-line AC/DC converter applications. G D S TO-262(R) The TO-262 package is widely preferred for commercial-industrial ... | Original |
5 pages, |
2762R AP2762R-A AP2762 AP2762R-A abstract |
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| Abstract: AP13N50W AP13N50W RoHS-compliant Product Advanced Power Electronics Corp. N-CHANNEL ENHANCEMENT MODE POWER MOSFET Low On-resistance Simple Drive Requirement Fast Switching Characteristic BVDSS 500V RDS(ON) D 0.52 ID G 14A S Description Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G D TO-3P S Absolute Maximum Ratings Symbo ... | Original |
5 pages, |
AP13N50W AP13N50W abstract |
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| Abstract: RF 672 001E 1. RACIF with summation transformer type SLCE12 SLCE12 for series trip RACIF together with the summation transformer SLCE12 SLCE12 ensure the protection of feeder bays in medium voltage power systems without any auxiliary power sources. The energy for operation of the relay and tripping of the circuit breaker is derived from the fault current. The system have high sensitivity for ground faults as well as for short circuits. Saturation of the summation transformer at high fault currents protect the ... | OCR Scan |
6 pages, |
UG03-2314 5P20 SUMMATION TRANSFORMER CT 1A 20VA 400-AB trip coil DC circuit breaker 5A circuit diagram of 100 VA transformer SLCE12 over current relay SUMMATION current transformer TRANSFORMER CT 5A transformer winding formula SLCE12 abstract |
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| Abstract: AN10010 AN10010 ISP1181A/ISP1181B/ISP1183 ISP1181A/ISP1181B/ISP1183 Frequently Asked Questions Rev. 07 - 10 July 2009 Application note Document information Info Content Keywords isp1181a, isp1181b, isp1183; faq, usb Abstract This document is a compilation of Frequently Asked Questions (FAQs) on ST-Ericsson Universal Serial Bus Peripheral Controllers at full-speed: ISP1181A ISP1181A, ISP1181B ISP1181B and ISP1183 ISP1183. AN10010 AN10010 ISP1181A/ISP1181B/ISP1183 ISP1181A/ISP1181B/ISP1183 FAQs Revision history Rev Date Description 07 2009071 ... | Original |
15 pages, |
PDIUSBD12 ISP1183 ISP1181A blm11 BLM32A07 self BLM11B102S isp1181b AN10010 ISP1181A/ISP1181B/ISP1183 ISP1181B AN10010 abstract |
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| Abstract: BF1218 BF1218 Dual N-channel dual gate MOSFET Rev. 01 - 14 April 2010 Product data sheet 1. Product profile 1.1 General description The BF1218 BF1218 is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads and an integrated switch. The integrated switch is operated by the gate1 bias of amplifier B. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during Automatic Gain Control ( ... | Original |
23 pages, |
reference table n mosfet dual gate mosfet in vhf amplifier A1 marking code amplifier bf1218 BF1218 BF1218 abstract |
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| Abstract: BF1208D BF1208D Dual N-channel dual gate MOSFET Rev. 01 - 16 May 2007 Product data sheet 1. Product profile 1.1 General description The BF1208D BF1208D is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads and an integrated switch. The integrated switch is operated by the gate1 bias of amplifier B. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during Automatic Gain Control ... | Original |
22 pages, |
BF1208D 097.176 BF1208D abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| set to a logic zero the row reading sequence is 0-1-2.33 (fig.12). If MY is set to a logic one the reading sequence is 32.1-33 (Fig 13). The icon row (BANK8) is always the last being www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7567.htm |
STMicroelectronics | 01/02/2001 | 52.07 Kb | HTM | 7567.htm |
| . The MY bit control the reading process. If MY is set to a logic zero the row reading sequence is 0-1-2.33 (fig.12). If MY is set to a logic one the reading sequence is 32.1-33 (Fig 13). The icon row www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/7566.htm |
STMicroelectronics | 01/02/2001 | 53.63 Kb | HTM | 7566.htm |