NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SPC5602DF1CLL3 | Freescale Semiconductor | 32bit 32MHz 256k flash 100ld | 
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: At 0.1Vdd 0.9Vdd / (max) 0.1Vdd 0.9Vdd Input Current At no Load 1.5mA 32MHz 2.0mA 32MHz 2.5mA 32MHz (max) 2.5mA 32MHz 3.0mA 32MHz 3.5mA 32MHz Driving ... | Original |
1 pages, |
DUT30AT-Y 32MHZ DUT20AT5Y DUT20AT8Y DUT30ATY DUT20AT5Y abstract |
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| Abstract: (fo-32.5MHz) 7.0 X 8.2 X 2.8 c DPC836R25A DPC836R25A 836.00 ±12.5 S 3.0 S 1.0 S 2.0 £18 (fo + 32MHz) £12(fo-32MHz , S 3.0 sí 1.0 S 2.0 £18 (fo + 32MHz) £12 (fo-32MHz) 9.0x11.8x3.8 c DPC899R19A DPC899R19A 899.50 ±9.5 S 3.5 s 1.0 S 2.0 £25 (fo + 32MHz) £17 (fo-32MHz) 8.9x11.8x3.8 c DPC902H25A DPC902H25A 902.50 ±12.5 á3.0 S 1.0 £ 2.0 £12 , 32MHz) £12 (fo-32MHz) 8.7x11.8x3.8 c DPC944R19A DPC944R19A 944.50 ±9.5 £3.5 £ 1.0 S 2.0 £25 (fo + 32MHz) £17 (fo - 32MHz) 8.4x11.8x3.8 c DPC947H25A DPC947H25A 947.50 ±12.5 S3.0 £ 1.0 S 2.0 £12 (fo +32.5MHz) £15 (fo-32.5MHz ... | OCR Scan |
1 pages, |
datasheet abstract |
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| Abstract: 32 DC 120120180 32 DC15V24V DC15V24V V850ES/IK1 V850ES/IK1(32MHz)1 V850E/IG3 V850E/IG3(64MHz) 2 2 RS-232C RS-232C I/F QB-MINI2 I/F U 32bit 32bit CPU Timer Flash ADC Comparator OpAmp shunt V W CPU V850E/IG3 V850E/IG3 2 W SpeedVR I , 120 120 CPU V850ES/IK1 V850ES/IK1(32MHz) QB-MINI2 CPU V85EIG3 V85EIG3(64MHz) QB-MINI2 180 , (32MHz)(64MHz) BEMF U/V/W U/V/W etc. PCUSB / URL ... | Original |
2 pages, |
QB-MINI2 7seg led 7SEG 32Mhz DC15V24V V850ES/IK1 V850E/IG3 DC15V24V abstract |
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| Abstract: 8 8 M Hz to 25MHz 1 12 M Hz to 25MHz 8 25MHz to 32MHz .798 i p-.497 - .200 MAX .018 DIA'- "1 .250 J t .030 PIN FREQUENCY RANGE 1 12MHz to 25MHz 8 32MHz to 40MHz 1 12M Hz to 25MHz 8 40MHz to 48MHz 1 2 5M Hz to 32MHz 8 32MHz to 40MHz 1 25MHz to 32MHz 8 4 0 M Hz to 48MHz GLASS ... | OCR Scan |
2 pages, |
S53DF S52DF 32Mhz 25MHZ 23M3431 T-50-23 23M3431 abstract |
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| Abstract: boards Main clock for 32MHz (OSC -3) Main clock (OSC - 2) User's Manual Option ? M30850T M30850T -EPBM , Maximum operating clock 32MHz (at Vcc1=Vcc2=4.2 to 5.5V) frequency 24MHz (at Vcc1=Vcc2=3.0 to 5.5V) MCU , , 32MHz) Static 516Kbytes for internal ROM of MCU (Fixed F000h -FFFFh and F80000h -FFFFFFh, 32MHz) Dynamic 3,328Kbytes for expansion area (Allocable in 256K -byte or 1,024K-byte blocks, 32MHz, 1ø+1ø Dynamic 4,096K bytes for expansion area (Allocable in 256K -byte or 1,024K-byte blocks, 32MHz, 1ø+1ø ? ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: Item Input impedance Output impedance (R in) (Rout) Center frequency 1.8k 1.8k 3.2MHz , MIN.26dB Group Delay 3.2MHz 1300ns±260ns Within Insertion Loss 3.2MHz MAX.7.5dB Frequency Response (Attenuation 0dB at 3.2MHz) Please refer to the sales offices on our website for a ... | Original |
2 pages, |
cy smd transistor 32Mhz 303MHz 2567-T smd transistor cy datasheet abstract |
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| Abstract: uPD70F3757 uPD70F3757 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3757 uPD70F3757 IDD VS VDD (Ta=25, fx=8/10/16MHz, fxt=32.768kHz) 100 32MHz Nomal operation(PLL ON) 20MHz Nomal operation(PLL ON) 16MHz Nomal operation(PLL OFF) 32MHz HALT(PLL ON) 10 20MHz HALT(PLL ON) 16MHz HALT(PLL OFF) 16MHz IDLE1 8MHz IDLE1 1 16MHz IDLE2 IDD [mA] 8MHz IDLE2 Subclock operation Sub-IDLE STOP 0.1 0.01 0.001 2 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6 The value mentioned above is only ... | Original |
1 pages, |
16MHz uPD70F3757 uPD70F3757 abstract |
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| Abstract: uPD70F3740 uPD70F3740 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3740 uPD70F3740 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 10 4MHz IDLE2 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
4MHZ uPD70F3740 uPD70F3740 abstract |
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| Abstract: uPD70F3752 uPD70F3752 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3752 uPD70F3752 IDD VS VDD (Ta=25, fx=8/10/16MHz, fxt=32.768kHz) 100 32MHz Nomal operation(PLL ON) 20MHz Nomal operation(PLL ON) 16MHz Nomal operation(PLL OFF) 32MHz HALT(PLL ON) 10 20MHz HALT(PLL ON) 16MHz HALT(PLL OFF) 16MHz IDLE1 8MHz IDLE1 1 16MHz IDLE2 IDD [mA] 8MHz IDLE2 Subclock operation Sub-IDLE STOP 0.1 0.01 0.001 2 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6 The value mentioned above is only ... | Original |
1 pages, |
uPD70F3752 uPD70F3752 abstract |
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| Abstract: uPD70F3741 uPD70F3741 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3741 uPD70F3741 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 10 4MHz IDLE2 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
4MHZ uPD70F3741 uPD70F3741 abstract |
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| Abstract: NJU6439 NJU6439 NJU6439LCD1/4LCD NJU6439LCD1/4LCD 440 160 LCD NJU6439 NJU6439 NJU6439CH NJU6439CH LCD 40 - 1/4-(160),1/3 ( 2MHz MAX) INH 2.43.6V 6.0V(MAX) C-MOS NJU6439 NJU6439 MEMO ... | Original |
11 pages, |
NJU6439 NJU6439LCD1/4LCD NJU6439CH NJU6439 abstract |
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| Abstract: uPD70F3745 uPD70F3745 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3745 uPD70F3745 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 10 4MHz IDLE2 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
4MHZ uPD70F3745 uPD70F3745 abstract |
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| Abstract: uPD70F3743 uPD70F3743 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3743 uPD70F3743 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 4MHz IDLE2 10 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
uPD70F3743 4MHZ uPD70F3743 abstract |
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| Abstract: uPD70F3742 uPD70F3742 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3742 uPD70F3742 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 10 4MHz IDLE2 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
4MHZ uPD70F3742 uPD70F3742 abstract |
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| Abstract: uPD70F3739 uPD70F3739 IDD VS VDD(25) Prepared on July 25, 2008 uPD70F3739 uPD70F3739 IDD VS VDD (Ta=25, fx=4MHz, fxt=32.768kHz) 100 32MHz Nomal operation 32MHz HALT 4MHz IDLE1 4MHz IDLE2 10 Subclock operation Sub-IDLE STOP IDD [mA] 1 0.1 0.01 0.001 1 1.5 2 2.5 VDD [V] 3 3.5 4 The value mentioned above is only for your reference. The value was measured under certain conditions and does not guarantee the product's characteristics. ... | Original |
1 pages, |
4MHZ uPD70F3739 uPD70F3739 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/9716124-119101ZC/91362_frt_icu-v22.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 133.85 Kb | ZIP | 91362_frt_icu-v22.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/76882022-119093ZC/91362_adc_lcd_alpha-v22.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 133.04 Kb | ZIP | 91362_adc_lcd_alpha-v22.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/17962778-119102ZC/91362_frt_ocu-v11.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 187.75 Kb | ZIP | 91362_frt_ocu-v11.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/67340833-119115ZC/91362_sw_ramcode-v22.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 133.6 Kb | ZIP | 91362_sw_ramcode-v22.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/63579905-119106ZC/91362_i2c_400khz-v13.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 117.44 Kb | ZIP | 91362_i2c_400khz-v13.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/93751984-119131ZC/91369_template-v35.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 127.6 Kb | ZIP | 91369_template-v35.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/7370902-119128ZC/91366_template-v35.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 133.1 Kb | ZIP | 91366_template-v35.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/1938969-119127ZC/91364_uart0_async-v12.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 128.77 Kb | ZIP | 91364_uart0_async-v12.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/18082702-119126ZC/91364_uart_lin_slave-v14.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 128.44 Kb | ZIP | 91364_uart_lin_slave-v14.zip |
| . # (C) Fujitsu Microelectronics Europe GmbH # PLL_32MHz -file into # the emulator. # The file sets the PLL-Clock to 32MHz for faster download. # # V1.0 - 25.10.2001 by JR # first release # printf "\nprocedure file : PLL_32MHz.prc\n\n" #- printf "CPU Clock set to 32MHz \n" set memory/byte H'484=00 # reset PLL set memory/byte 484=44 # set 32MHz (64=48MHz,74=64MHz) set memory/byte 484=46 # enable (66 ,76 ) set memory www.datasheetarchive.com/download/75094831-119118ZC/91362_wdt-v23.zip (PLL_32MHz.prc) |
Fujitsu | 01/02/2012 | 142.68 Kb | ZIP | 91362_wdt-v23.zip |