NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SC16C650BIA44-T | NXP Semiconductors | 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder | 
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| SC16C652BIBS-S | NXP Semiconductors | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoder |
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| SC16C650BIB48-S | NXP Semiconductors | 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder |
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| SC16C652BIB48-S | NXP Semiconductors | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs and infrared (IrDA) encoder/decoder |
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| SC16C650BIBS-S | NXP Semiconductors | 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: : The 106 will not target-abort after 32-bytes, it will target-disconnect. The distinction being a , PCI-to-system-memory-write-buffer (PCMWB), which is 32-bytes, must snoop the address on the 60x bus and flush its contents to ... | Original |
1 pages, |
MPC106 TO 106 transistor transistor case To 106 MPC106 abstract |
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| Abstract: duplex mode) the IDB is received as the first byte of the 32bytes which are expected from the bootstrap , This workaround reduces the number of usable bytes for a preloader from 32bytes to 28bytes because ... | Original |
2 pages, |
sax c167cr-lm C167SR-LM C167 C166 C165 AP1612 88C166 C167 loader APXXXX01 APXXXX01 abstract |
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| Abstract: , 16- or 32-Bytes Flexible interface for Mitsubishi 37690, Zilog Z80 or Atmel 89C51 89C51 microcontrollers , 32-Bytes per in/out endpoints 2. MAX I/O with on-chip FIFOs, assuming all core signals are routed , decoding and specified descriptor actions. The In and Out FIFOs are 32-Bytes deep and uni-directional for , registerselectable at 8/16/32-Bytes. The In and Out FIFOs can be interfaced either to the microcontroller or to an ... | Original |
4 pages, |
crc 16 verilog HQ240 z80, intel XC4000E micro controller 89c51 circuit 89c51 atmel specification all 89c51 microcontroller datasheet z80 atmel 89C51 89c51 controller microcontroller 89c51 board 89C51 pinout FEATURES OF microcontroller 89C51 datasheet abstract |
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| Abstract: in half duplex mode) the IDB is received as the first byte of the 32bytes which are expected from , bytes for a preloader from 32bytes to 28bytes because 4bytes are necessary for the 'IDB instruction'. ... | Original |
7 pages, |
88C166 C167SR-LM C167 C166 C165 AP16012 Bosch sax c167cr-lm C167 loader C166 INFINEON AP16012 abstract |
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| Abstract: OKI Semiconductor MSM531652F MSM531652F_ 1,048,576-Words x 16-bit or 2,097,152-Bytes x 8-bit MaskROM 16Words x 16-Bit or 32Bytes x 8-Bit/Page Mode MASKROM â- DESCRIPTION The OKI MSM531652F MSM531652F is a 1,048,576-words x 16-bit or 2,097,152-bytes x 8-bit CMOS Mask ROM with an asynchronous page read mode. Each page is organized 16 words x 16-bit or 32bytes x 8-bit. It operates on a single 5.0V power supply and is , ,A1 ,A0) or 32-bytes(A3,A2,A1 ,A0,A-1) / Page • Access time 100ns Max (Normal access) 50ns Max (Page ... | OCR Scan |
9 pages, |
MSM531652F DIP42-P-600-2 48-PIN 44-PIN 42-PIN MSM531652F abstract |
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| Abstract: 32-Bytes · Flexible interface for Mitsubishi 37690, Zilog Z80 or Atmel 89C51 89C51 microcontrollers · , 32-Bytes per in/out endpoints. 2) MAX I/O with on-chip FIFOs, assuming all core signals are routed , netlists are provided for each module. The In and Out FIFOs are 32-Bytes deep and unidirectional for TX , tokens is registerselectable at 8/16/32-Bytes. The In and Out FIFOs can be interfaced either to the ... | Original |
4 pages, |
XC4000E pin diagram of micro controller 89c51 HQ240 89C51 microcontroller 89c51 pin diagram Atmel 89C51 microcontroller datasheet abstract |
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| Abstract: , current accumulation (coulomb counting), 32-bytes EEPROM, and a single wire communication interface. The , integrated current sense resistor, 32bytes of lockable user EEPROM, temperature and current measurements ... | Original |
2 pages, |
MM1292 MAX1726EUK33 geared DC motor DS2761 DS2760 AN405 12v DC geared motor 12v geared DC motor DS2760 abstract |
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| Abstract: Extended RAM: 4K-bytes of builtin S-RAM Page register: 1-byte Configuration: 32-bytes x 128 pages The , I 128 PAGES OF 32-bytes EXTENDED RAM 01 0? PAGE 7F PAGE. 00 XRAM + 20 I ... | OCR Scan |
2 pages, |
rtc65271 BR1225 5201c RTC-65271 RTC-65271 abstract |
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| Abstract: Extended RAM: 4k-bytes of builtin S-RAM Page register: 1-byte Configuration: 32-bytes x 128 pages · The , 128 PAGES OF 32-bytes EXTENDED RAM THRU 04 HOURS 05 HOUR ALARM 06 DAY OF WEEK 3F XRAM + ... | Original |
2 pages, |
RTC-65271 BR1225 5201c rtc ic RTC-65271 abstract |
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| Abstract: Semiconductor MSM531652F MSM531652F 1,048,576-Words x 16-bit or 2,097,152-Bytes x 8-bit MaskROM 16Words x 16-Bit or 32Bytes x 8-Bit/Page Mode MASKROM DESCRIPTION The OKI MSM531652F MSM531652F is a 1,048,576-words x 16-bit or 2,097,152-bytes x 8-bit CMOS Mask ROM with an asynchronous page read mode. Each page is organized 16 words x 16bit or 32bytes x 8-bit. It operates on a single 5.0V power supply and is TTL , ,A0) or 32-bytes(A3,A2,A1,A0,A-1) / Page Access time 100ns Max (Normal access) 50ns Max (Page ... | Original |
8 pages, |
MSM531652F DIP42-P-600-2 48-PIN 44-PIN 42-PIN MSM531652F abstract |
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| Abstract: Microcontrollers ApNote AP1613 AP1613 o additional file APXXXX01 APXXXX01.EXE available Bootstrap Loader Versions Any current step of the SAB 80C166 80C166, C167 and C165 except of the respective bond-out chips implements an on-chip bootstrap loader. Hans Sulzer / Siemens MC Semiconductor Group 03.97, Rel. 01 Bootstrap Loader Versions Question: Which version of the on-chip boostrap loader is implemented in which derivative and step of the 80C166 80C166, C167 and C165 microcontroller families? ... | Original |
2 pages, |
transistor c167 88C166 boostrap C161RI C161V C167 NMI siemens 80C166 C165 siemens C167 BA-STEP AP1613 C167 loader APXXXX01 APXXXX01 AP1613 APXXXX01 abstract |
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| Abstract: 64 Kbit (8192 Ã- 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection ModeTM SLx 24C64/P 24C64/P Preliminary Features · Data EEPROM internally organized as 8192 bytes and 256 pages Ã- 32 bytes · Page protection mode, flexible page-by-page hardware write protection  Additional protection EEPROM of 256 bits, 1 bit per data page P-DIP-8-4  Protection setting for each data page by writing its protection bit  Protection management without switching WP pin · Low power C ... | Original |
1 pages, |
24C64 24C64 WP programming 24c64 eeprom 24c64 24C64/P 24C64/P abstract |
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| Abstract: 32 Kbit (4096 Ã- 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus SLx 24C32 24C32 Preliminary Features · Data EEPROM internally organized as 4096 bytes and 128 pages Ã- 32 bytes · Low power CMOS · VCC = 2.7 to 5.5 V operation · Two wire serial interface bus, I2C-Bus compatible · Three chip select pins to address 8 devices · Filtered inputs for noise suppression with Schmitt trigger · Clock frequency up to 400 kHz · High programming flexibility  Internal programming voltage  ... | Original |
1 pages, |
24C32 CMOS 4000 24C32 abstract |
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| Abstract: 64 Kbit (8192 Ã- 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus SLx 24C64 24C64 Preliminary Features · Data EEPROM internally organized as 8192 bytes and 256 pages Ã- 32 bytes · Low power CMOS · VCC = 2.7 to 5.5 V operation · Two wire serial interface bus, I2C-Bus compatible · Three chip select pins to address 8 devices · Filtered inputs for noise suppression with Schmitt trigger · Clock frequency up to 400 kHz · High programming flexibility  Internal programming voltage  ... | Original |
1 pages, |
eeprom 24c64 24C64 CMOS 4000 24C64 abstract |
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| Abstract: 32 Kbit (4096 Ã- 8 bit) Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection ModeTM SLx 24C32/P 24C32/P Preliminary Features · Data EEPROM internally organized as 4096 bytes and 128 pages Ã- 32 bytes · Page protection mode, flexible page-by-page hardware write protection  Additional protection EEPROM of 128 bits, 1 bit per data page P-DIP-8-4  Protection setting for each data page by writing its protection bit  Protection management without switching WP pin · Low power C ... | Original |
1 pages, |
24c32 6 24C32/P 24C32/P abstract |
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| Abstract: 16 Kbit (2048 Ã- 8 bit) Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C160 25C160 Preliminary Features · Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 · Page Protection ModeTM for protecting the EEPROM against unintended data changes (SLx 25C160 25C160./P types only) · Low power CMOS P-DIP-8-4 · Clock frequency up to 2.1 MHz · VCC = 2.7 to 5.5 V operation · 32-byte page mode · Write protect (WP) pin and write disable instructio ... | Original |
1 pages, |
25C160 25C160 abstract |
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| Abstract: 8 Kbit (1024 Ã- 8 bit) Serial CMOS EEPROMs, Serial Peripheral Interface (SPI) Synchronous Bus SLx 25C080 25C080 Preliminary Features · Serial peripheral interface (SPI) compatible, supports SPI Modes 0,0 and 1,1 · Page Protection ModeTM for protecting the EEPROM against unintended data changes (SLx 25C080 25C080./P types only) · Low power CMOS P-DIP-8-4 · Clock frequency up to 2.1 MHz · VCC = 2.7 to 5.5 V operation · 32-byte page mode · Write protect (WP) pin and write disable instruction ... | Original |
1 pages, |
25C080 25C080 abstract |
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| Abstract: AT28HC64/L AT28HC64/L Features • Fast Read Access Time - 55 ns • Automatic Page Write Operation Internai Address and Data Latches for 32 Bytes Internal Control Timer • Fast Write Cycle Times Maximum Page Write Cycle Time: 2 ms 1 to 32 Byte Page Write Operation • Low Power Dissipation 80 mA Active Current 100 nA CMOS Standby Current (28HC64L 28HC64L) • Direct Microprocessor Control DATA Polling • High Reliability CMOS Technology Endurance: 104 or 10s Cycles Data Retention: 10 years • Slngle5 V+ 10% Su ... | OCR Scan |
2 pages, |
AT28HC64/L AT28HC64/L abstract |
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| Abstract: DS1422 DS1422 PRODUCT PREVIEW DS1422 DS1422 1Kbit AddÂOnly UniqueWare Button SPECIAL FEATURES F5 MICROCANTM · 1024Âbits Electrically Programmable Read Only Memory (EPROM) partitioned into four 256Âbit pages for randomly accessing packetized data records 5.89 0.36 0.51 · Each memory page can be permanently writeÂpro- 16.25 tected to prevent tampering YYWW REGISTERED RR · Device is an "add only" memory where additional data 17 09 17.35 can be programmed into ... | Original |
2 pages, |
DS1427 DS1425 DS1422 DS1422 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| /* * Memory linkscript for RDB1768cmis_usb_bootloader project. * This script has been modified from the original generated * by the Code Red tools to * * 1) Reserve the top 32 bytes of RAMLoc32 for use by the IAP * programming routines, as described in the LPC17xx User * Manual. * * 2) Reduce the size of the flash memory available, to ensure * that it never overflows into the (rwx) : ORIGIN = 0x10000000, LENGTH = 0x7FE0 /* 32k - 32bytes */ RamAHB32 (rwx) : ORIGIN = 0x2007c www.datasheetarchive.com/download/72876757-595958ZC/code.bundle.rdb1768.cmsis.zip (rdb1768cmsis_usb_bootloader_mem.ld) |
NXP | 09/04/2010 | 1633.54 Kb | ZIP | code.bundle.rdb1768.cmsis.zip |
| ST | 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE Datasheet 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE M34S32 M34S32 M34S32 M34S32 Document Format Size Document Number Date Update Pages Portable Document Format 6000 22/06/1998 18 Raw Text Format www.datasheetarchive.com/files/stmicroelectronics/books/all/6000.htm |
STMicroelectronics | 25/05/2000 | 2.95 Kb | HTM | 6000.htm |
| ST | 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE M34S32 M34S32 M34S32 M34S32 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE Document Number: 6000 Date Update: 22/06/98 Pages: 18 The document is available in the following formats: Portable Document Format and Raw Text Format www.datasheetarchive.com/files/stmicroelectronics/stonline/books/all/6000.htm |
STMicroelectronics | 31/03/1999 | 0.96 Kb | HTM | 6000.htm |
| ST | 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE M34S32 M34S32 M34S32 M34S32 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE Document Number: 6000 Date Update: 22/06/98 Pages: 18 The document is available in the following formats: Portable Document Format and Raw Text Format www.datasheetarchive.com/files/stmicroelectronics/stonline/books/all/6000-v1.htm |
STMicroelectronics | 14/06/1999 | 0.94 Kb | HTM | 6000-v1.htm |
| ST | 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE - BRIEF DATA M34S32 M34S32 M34S32 M34S32 32K SERIAL I 2 C BUS EEPROM WITH USER-DEFINED READ-ONLY BLOCK AND 32-BYTE OTP PAGE - BRIEF DATA Document Number: 5999 Date Update: 22/06/98 Pages: 2 The document is available in the following formats: Portable Document Format and Raw Text Format www.datasheetarchive.com/files/stmicroelectronics/stonline/books/all/5999.htm |
STMicroelectronics | 31/03/1999 | 0.99 Kb | HTM | 5999.htm |
| Builtin crystal unit allows adjustment-free efficient operation. A builtin power supply switching circuit makes it possible to provide automatic power supply backup to both the RTC and extended RAM. The RTC block consists of: Indirect register: 1-byte, Control register: 4-bytes, Clock, alarm, calendar: 10-bytes, User RAM: 50-bytes. Extended RAM: 4K-bytes of S-RAM, Page register: 1-byte; Config.: 32-bytes x 128 pages The package is a 28-pin DIP IC with a battery holder, battery replacement www.datasheetarchive.com/files/design-elektronik/crystal/texte/rtc-65271.txt |
Design Elektronik | 11/08/1998 | 0.55 Kb | TXT | rtc-65271.txt |
| Builtin crystal unit allows adjustment-free efficient operation. A builtin power supply switching circuit makes it possible to provide automatic power supply backup to both the RTC and extended RAM. The RTC block consists of: Indirect register: 1-byte, Control register: 4-bytes, Clock, alarm, calendar: 10-bytes, User RAM: 50-bytes. Extended RAM: 4K-bytes of S-RAM, Page register: 1-byte; Config.: 32-bytes x 128 pages The package is a 28-pin DIP IC with a battery holder, battery replacement www.datasheetarchive.com/files/spezial-electronic/crystal/texte/rtc-65271.txt |
Spezial Electronic | 11/08/1998 | 0.55 Kb | TXT | rtc-65271.txt |
| 21050 32-Bit 32 Bytes Shared Not Supported 32-Bit 32 Bytes Not Supported 32 Bytes Shared Not Supported 32-Bit 32 Bytes Not Supported 4 Sets No www.datasheetarchive.com/files/intel/technologies/design/bridge/linecard/index.htm |
Intel | 30/04/1999 | 21.19 Kb | HTM | index.htm |
| radically larger than the dst count (1024 vs 32 bytes). Is this okay? ANSWER: The packet transfer it had been only a 32-32 byte transfer. In fact, in the 128-32 byte case, the buffer doesn't bother to fill up past 32 bytes- the transfer is over as soon as dst count is zero. Now, there www.datasheetarchive.com/files/texas-instruments/sc/docs/dsps/hotline/m046.htm |
Texas Instruments | 20/12/1996 | 4.54 Kb | HTM | m046.htm |
| * * * */ typedef unsigned char BYTE; int iGetNID (BYTE far *buff32,BYTE nid[],int iNIDlength); int iSetNID (BYTE far *buff32,BYTE nid[],int iNIDlength); void vUpdateChecksums (BYTE far *buff32); #endif www.datasheetarchive.com/download/84901517-9405ZC/utldisk2.zip (CIS.H) |
AMD | 13/04/1999 | 785.38 Kb | ZIP | utldisk2.zip |