NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ) branch." · PCI 3+1Port RS232 RS232 Users: PCI 3+1 Port RS232 RS232 will appear under the "Multi-function , PCI 3Port RS232 RS232 users: Chapter 3 Page 16 PCI 3+1Port RS232 RS232 users: PCI 3 Port RS232 RS232 , : PCI 3+1Port RS232 RS232 users: In this window, the COM port assignment may be changed, simply by , PCI Port Configuration window: PCI 3+1Port RS232 RS232 users, these entries under card will appear as: PCI 3+1Port RS232 RS232 Card. Chapter 3 Page 21 Software Configuration PCI 3 Port RS232 RS232 ... | Original |
45 pages, |
RS232 to parallel converter 16750-compatible COM16 dio24 DIO48D IN24D pci card schematic PCI PROJECT rs232 connection rs232 pc rs232 cross 16650 uart RS232 RS232 RS232 RS232 abstract |
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| Abstract: PM7341 PM7341 S/UNI®-IMA-84 -IMA-84 Preliminary 84 Link Inverse Multiplexer for ATM (IMA) / UNI PHY ATM OVER FRACTIONAL T1/E1 · Any-PHY receive slave appears as a single device. The PHY-ID of each cell is identified using in-band addressing. · UTOPIA L2 transmit and receive slave appears as a 31-port multi-PHY. · UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend. · Supports up to 32 ATM over Fractional T1/E1 UNIs over the clock/data interface, compliant ... | Original |
2 pages, |
TEMUX-84 PM8316 PM8315 PM7341 datasheet abstract |
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| Abstract: appears as a 31-port multi-PHY. · UTOPIA L2 receive slave can also appear as a single port with the ... | Original |
2 pages, |
UNI-IMA-32 PM7350 PM7342 PM7326 datasheet abstract |
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| Abstract: PM7341 PM7341 S/UNI®-IMA-84 -IMA-84 Preliminary 84 Link Inverse Multiplexer for ATM (IMA) / UNI PHY ATM OVER FRACTIONAL T1/E1 · Any-PHY receive slave appears as a single device. The PHY-ID of each cell is identified using in-band addressing. · UTOPIA L2 transmit and receive slave appears as a 31-port multi-PHY. · UTOPIA L2 receive slave can also appear as a single port with the logical port provided as a prepend. · Supports up to 32 ATM over Fractional T1/E1 UNIs over the clock/data interface, compliant ... | Original |
2 pages, |
TEMUX-84 PM8316 PM8315 PM7341 datasheet abstract |
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| Abstract: transmit and receive slave appears as a 31-port multi-PHY. · UTOPIA L2 receive slave can also appear as ... | Original |
2 pages, |
TEMUX-84 PM8316 PM8315 PM7342 datasheet abstract |
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| Abstract: appears as a PHY port on the Any-PHY and UTOPIA L2 bus. UTOPIA L2 transmit slave appears as a 31-port ... | Original |
413 pages, |
R2C marking PM7341 27X27 PMC-2000223 S/UNI-IMA-84 PMC-2000223 abstract |
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| Abstract: L2 bus. UTOPIA L2 transmit slave appears as a 31-port multi-PHY. Seamlessly interconnects to ... | Original |
408 pages, |
R2C marking PM7341 27X27 PMC-2000223 S/UNI-IMA-84 PMC-2000223 abstract |
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| Abstract: PM7340 PM7340 S/UNI-IMA-8 PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM PM7340 PM7340 S/UNI-IMA-8 S/UNI INVERSE MULTIPLEXING FOR ATM, 8 LINKS DATA SHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 3: FEBUARY, 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PM7340 PM7340 S/UNI-IMA-8 PRELIMINARY INVERSE MULTIPLEXING OVER ATM DATA SHEET PMC-2001723 PMC-2001723 ISSUE 3 INVERSE ... | Original |
334 pages, |
PM7340 PLA relay PMC-2001723 PMC-2001723 abstract |
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| Abstract: 2: 06 PM S/UNI-IMA-16 S/UNI-IMA-16 Telecom Standard Product Data Sheet Released Su nd ay ,0 5J an S/UNI-IMA-16 S/UNI-IMA-16 ua ry ,2 00 3 11 :0 PM7343 PM7343 sil ico ne xp er to n S/UNI INVERSE MULTIPLEXING FOR ATM, 16 LINKS PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 1: MAY 2002 Do wn lo ad ed by ah m ed m et wa ly of DATA SHEET Proprietary and Confidential to PMC-Sierra, Inc., and for its customers' ... | Original |
329 pages, |
PM7343 PM7326 PM7324 PM4354 G.SHDSL LOOP modems ELLS 110 PM8353 S/UNI-IMA-16 S/UNI-IMA-16 abstract |
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| Abstract: TU405 57 AM S/UNI-IMA-4 Telecom Standard Product Data Sheet Released be to da y, 14 Oc S/UNI-IMA-4 r, 20 03 02 :3 0: PM7348 PM7348 ol og yI nc on Tu es S/UNI INVERSE MULTIPLEXING FOR ATM, 4 LINKS PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 2: JULY, 2002 lo ad ed by Am r Ma ns ou ro fS ilic on Ex pe rt Te cn DATA SHEET Proprietary and Confidential to PMC-Sierra, Inc., and for its cu ... | Original |
318 pages, |
PM7328 PM73124 PM4354 ELLS 110 PM8353 datasheet abstract |
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| Abstract: 1.2 Internal Block Diagram LCD Power Supply P87/SEG32/CL1 P87/SEG32/CL1 P86/SEG31/CL2 P86/SEG31/CL2 P85/SEG30/DO P85/SEG30/DO P84/SEG29/M P84/SEG29/M P83/SEG28 P83/SEG28 P82/SEG27 P82/SEG27 P81/SEG26 P81/SEG26 P80/SEG25 P80/SEG25 P77/SEG24 P77/SEG24 P76/SEG23 P76/SEG23 P75/SEG22 P75/SEG22 P74/SEG21 P74/SEG21 P73/SEG20 P73/SEG20 P72/SEG19 P72/SEG19 P71/SEG18 P71/SEG18 P70/SEG17 P70/SEG17 P67/SEG16 P67/SEG16 P66/SEG15 P66/SEG15 P65/SEG14 P65/SEG14 P64/SEG13 P64/SEG13 P63/SEG12 P63/SEG12 P62/SEG11 P62/SEG11 P61/SEG10 P61/SEG10 P60/SEG9 P60/SEG9 Serial communication interface 3-2 Timer - F 14-bit PWM Timer - G Asynchronous counter WDT A/D (10bit) LCD Controller PB0/AN0 PB1/AN1 PB2/AN ... | Original |
1 pages, |
H8/3867 H8/3827 H8/3867 abstract |
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| Abstract: www.brainboxes.com PCI Features · Four RS232 RS232 Serial ports · PCI Bus - Fully Plug & Play · · 3+1 Port RS232 RS232 auto configuring interrupt and address Sample Programs, Test & Terminal software - all with source code Drivers for all popular operating systems Description This half size card provides 4 industry standard 9 pin RS232 RS232 serial COM ports using just a single PCI slot. The fourth port is a flying lead header which can be either connected to an available slot or knoc ... | Original |
1 pages, |
RS232 laptop bios 8 pin CC-420 RS232 abstract |
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| Abstract: Non-Catalog Model Power Splitter/Combiner PSC-4-1W-75 PSC-4-1W-75 4 Way-0° Important Note This is a non-catalog model and can be manufactured on specific request. Pricing and delivery information can be supplied upon request. CASE STYLE: A05 Please click "Back", and then click "Contact Us" for Applications support. ELECTRICAL SPECIFICATIONS 75@ +25ºC Parameter Frequency Isolation Insertion Loss Above 6.0 dB Phase Unbalance Amplitude Unbalance 5-50MHz 50-325MHz 325-6 ... | Original |
1 pages, |
M114324 PSC-4-1W-75 PSC-4-1W-75 abstract |
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| Abstract: 1.2 Internal Block Diagram LCD Power Supply P87/SEG32/CL1 P87/SEG32/CL1 P86/SEG31/CL2 P86/SEG31/CL2 P85/SEG30/DO P85/SEG30/DO P84/SEG29/M P84/SEG29/M P83/SEG28 P83/SEG28 P82/SEG27 P82/SEG27 P81/SEG26 P81/SEG26 P80/SEG25 P80/SEG25 P77/SEG24 P77/SEG24 P76/SEG23 P76/SEG23 P75/SEG22 P75/SEG22 P74/SEG21 P74/SEG21 P73/SEG20 P73/SEG20 P72/SEG19 P72/SEG19 P71/SEG18 P71/SEG18 P70/SEG17 P70/SEG17 P67/SEG16 P67/SEG16 P66/SEG15 P66/SEG15 P65/SEG14 P65/SEG14 P64/SEG13 P64/SEG13 P63/SEG12 P63/SEG12 P62/SEG11 P62/SEG11 P61/SEG10 P61/SEG10 P60/SEG9 P60/SEG9 Serial communication interface 3-2 Timer - F 14-bit PWM Timer - G Asynchronous counter WDT A/D (10bit) LCD Controller PB0/AN0 PB1/AN1 PB2/AN ... | Original |
1 pages, |
H8/3827R H8/3827R abstract |
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| Abstract: European Electronics Industry Awards WINNER WINNER Product of of t Year Manufacture theh Yea r e r UC-420 UC-420 & UC-431 UC-431 UNIVERSAL 3+1 PORT RS232 RS232 STREAMLINE ` SERIAL CARDS ENGINEERED TO EXCEED EXPECTATIONS ` Description Universal PCI card provides 3 or 4 industry standard 9 Pin RS232 RS232 serial COM ports in a single PCI slot. The fourth port is a flying lead header which can be either connected to an available slot or knockout on the chassis. No additional external cabling neccessary ... | Original |
4 pages, |
TL16C550 RS232 standard UC-420 UC-431 UC-420 abstract |
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| Abstract: C/L Band Fiber Optic Couplers Gould's new C/L Band couplers are ideal for DWDM systems and OTDR applications, providing excellent performance for applications that operate in the C/L Band from 1530nm to 1625nm. These couplers exhibit low insertion loss, and low sensitivity to polarization and wavelength. C/L Band couplers are available in a variety of splitting ratios from 50/50 to 99/1 tap versions. Standard package size is 3mm X 50mm. Specifications for 50/50 Coupling Ratio SERIES 1 Insert ... | OCR Scan |
1 pages, |
OTDR 1625nm datasheet abstract |
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| Abstract: Miniature 3-port Polarization Insensitive Optical Circulators MIOC Series Features Smallest Package Size Low Insertion Loss Low PDL High Channel Isolation Highly Stable & Reliable Low Dispersion Epoxy-Free Optical Path Miniature 3-port Polarization Insensitive Optical Circulators Oplink's polarization insensitive miniature circulator features excellent optical characteristicsover a wide wavelength range while delivering a very small form factor. It possesses lowinsertion loss, hig ... | Original |
2 pages, |
EDFA L-C band datasheet abstract |
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| Abstract: Hitachi Europe Ltd. ISSUE APPLICATION NOTE DATE: : APPS/011/3 APPS/011/3.1 4/1/96 EPROM Security on the H8/300 H8/300, H8/300L H8/300L, H8/500 H8/500, H8/300H H8/300H and SH7000 SH7000 families The H8/300 H8/300 (L), H8/300H H8/300H, H8/500 H8/500 and SH7000 SH7000 microcontrollers have an EPROM security feature that can be used by the application programmer. This feature allows the user of the microcontroller to protect parts (or all) of the code programmed into the on chip EPROM of the device from being read by means other than his or her own pr ... | Original |
4 pages, |
SH7000 P641 hitachi h8/534 hitachi eprom CPU H8/532 CPU H8 534 H8/520 APPS/011/3 APPS/011/3 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| _dcrDBus , DIR= out, BUS=SDCR, VEC=[0:31] PORT CPU_dcrABus = DCR_ABus , DIR= in , BUS=SDCR, VEC=[0: 9] PORT CPU_dcrDBusOut = DCR_Sl_DBus , DIR= in , BUS=SDCR, VEC=[0:31] PORT CPU_dcrWrite = DCR Plane_DCR_cpuDBusIn , DIR= in , VEC=[0:31] PORT DataPlane_CPU_dcrABus = DataPlane_CPU_dcrABus , DIR= out, VEC=[0: 9] PORT DataPlane_CPU_dcrDBusOut = DataPlane_CPU_dcrDBusOut, DIR= out, VEC=[0:31] PORT Data www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (dcr_slave_v2_1_0.mpd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| = IN PORT rst = "", DIR = IN PORT led_button_i = "", DIR = OUT, VEC = [0:31] PORT led_button_o = "", DIR = IN, VEC = [0:31] PORT gp_output_o = "", DIR = IN, VEC = [0:31] PORT plb_arb_error = "", DIR = IN PORT plb2opb_error = "", DIR = IN PORT opb2plb GPIO2_d_out = "", DIR = IN, VEC=[0:31] PORT GPIO2_t_out = "", DIR = IN, VEC=[0:31] PORT www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (misc_logic_v2_1_0.mpd) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| package macrocomps is component acc_sc GENERIC (n_bits : INTEGER := 31); PORT (clk, clr ; component acc_uc GENERIC (n_bits : INTEGER := 31); PORT (clk : IN std _sc GENERIC ( n_bits : INTEGER := 31); PORT ( x : IN std_logic_vector (n_bits-1) DOWNTO 0 _sc GENERIC ( a_bits : INTEGER := 32; b_bits : INTEGER := 31); PORT ( a : IN std _uc GENERIC (a_bits : INTEGER := 32; b_bits : INTEGER := 31); PORT (A : IN std_logic_vector (a_bits-1 www.datasheetarchive.com/download/5692482-988247ZC/wcd03623.zip (macrocomps.vhd) |
Xilinx | 12/02/1999 | 571.77 Kb | ZIP | wcd03623.zip |
| package macrocomps is component acc_sc GENERIC (n_bits : INTEGER := 31); PORT (clk, clr ; component acc_uc GENERIC (n_bits : INTEGER := 31); PORT (clk : IN std _sc GENERIC ( n_bits : INTEGER := 31); PORT ( x : IN std_logic_vector (n_bits-1) DOWNTO 0 _sc GENERIC ( a_bits : INTEGER := 32; b_bits : INTEGER := 31); PORT ( a : IN std _uc GENERIC (a_bits : INTEGER := 32; b_bits : INTEGER := 31); PORT (A : IN std_logic_vector (a_bits-1 www.datasheetarchive.com/download/93627041-987072ZC/wcd02e3f.zip (macrocomps.vhd) |
Xilinx | 13/07/1998 | 571.77 Kb | ZIP | wcd02e3f.zip |
| ; architecture PRBS of PRBS is component XOR_ARRY_31 port ( D : in STD_LOGIC_VECTOR(63 XOR_ARRY_PRBS_31: XOR_ARRY_31 port map ( D => D, SIn => S www.datasheetarchive.com/download/6111223-996050ZC/xapp775.zip (PRBS.vhd) |
Xilinx | 26/08/2004 | 30899.35 Kb | ZIP | xapp775.zip |
| output which is read, or net with declaration delay. component XOR_ARRY_31 port ( D : STD_LOGIC_VECTOR(63 downto 0 ); begin DOut D, SIn => S, SOut => DOut_31 www.datasheetarchive.com/download/6111223-996050ZC/xapp775.zip (PRBS_REPLICA.vhd) |
Xilinx | 26/08/2004 | 30899.35 Kb | ZIP | xapp775.zip |
| # Parameters PARAMETER VERSION = 2.1.0 # Global Ports PORT sys_clk = sys_clk, DIR = I, SIGIS = CLK PORT sys_rst = sys_rst, DIR = IN PORT gpio_out = gpio_out, DIR = OUT, VEC = [0:31] PORT gpio_in = gpio_in, DIR = IN, VEC = [0:31] PORT Uart1_sin = Uart1_sin, DIR = IN PORT Uart1_sout = Uart1_sout, DIR = OUT # Sub Components BEGIN ppc405 PARAMETER INSTANCE = ppc405_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE MDCR = dcr_v29_0 BUS_INTERFACE DSOCM = Bus_DSOCM_IF BUS www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (system.mhs) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| # Parameters PARAMETER VERSION = 2.1.0 # Global Ports PORT sys_clk = sys_clk, DIR = I, SIGIS = CLK PORT sys_rst = sys_rst, DIR = IN PORT gpio_out = gpio_out, DIR = OUT, VEC = [0:31] PORT gpio_in = gpio_in, DIR = IN, VEC = [0:31] PORT Uart1_sin = Uart1_sin, DIR = IN PORT Uart1_sout = Uart1_sout, DIR = OUT # Sub Components BEGIN ppc405 PARAMETER INSTANCE = ppc405_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE MDCR = dcr_v29_0 BUS_INTERFACE DSOCM = Bus_DSOCM_IF BUS www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (system_1cpu.mhs) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| # Parameters PARAMETER VERSION = 2.1.0 # Global Ports PORT sys_clk = sys_clk, DIR = I, SIGIS = CLK PORT sys_rst = sys_rst, DIR = IN PORT gpio_out = gpio_out, DIR = OUT, VEC = [0:31] PORT gpio_in = gpio_in, DIR = IN, VEC = [0:31] PORT Uart1_sin = Uart1_sin, DIR = IN PORT Uart1_sout = Uart1_sout, DIR = OUT # Sub Components BEGIN ppc405 PARAMETER INSTANCE = ppc405_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE MDCR = dcr_v29_0 BUS_INTERFACE DSOCM = Bus_DSOCM_IF BUS www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (system_2cpu.mhs) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| _256Kx32_Mem_A, DIR = output, VEC = [0:31] PORT SRAM_256Kx32_Mem_BEN = SRAM_256Kx32_Mem_BEN, DIR SRAM_256Kx32_Mem_DQ = SRAM_256Kx32_Mem_DQ, DIR = inout, VEC = [0:31] PORT SRAM_256Kx32_Mem_OEN = SRAM www.datasheetarchive.com/download/71796459-995980ZC/xapp482.zip (system.mhs) |
Xilinx | 25/08/2004 | 140.13 Kb | ZIP | xapp482.zip |