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3-8 decoder 74138

Catalog Datasheet MFG & Type PDF Document Tags

3-8 decoder 74138

Abstract: 74138 - 108 -74137 DATA OUTPUTS * 25LS2536(ii v M I- U ittif, ¿fili l te , 25LS2536 3* DF 74138 !sìgne h r TI OF DF
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3-8 decoder 74138 74138 74137 74138 decoder ttl 74138 decoder 74138

pin diagram of ic 74138

Abstract: application of IC 74138 SOJ (small outline J-Lead) package, three 74FCT244A buffers, one 74-138 decoder and forty-two 0.1
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pin diagram of ic 74138 application of IC 74138 IC 3-8 decoder 74138 pin diagram ic 74138 pin diagram AEPSD1M32

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 selector 8 !4 153 4 8SE 8-line to 1-line data selector 18 74151 Decoders 5 4DE 2-line to 4-line decoder with enable 9 74139 6 4DE1 2-line to 4-line decoder 6 7 8DE 3-line to 8-line decoder with enable 20 74138 8 8DE1 3-line to 8-line decoder 15 Latches/ registers 9 4LT 4-bit data latch 11 10 , < 0095 > 4-BIT SHIFT REGISTER 7495 41 » 8 3-LINE TO 8-LINE DECODER/ DEMULTIPLEXER 74138 22 9 , which are frequently used. â'¢ Decoder: 12 â'¢ Comparator: 4 â'¢ Selector/Multiplexer: 7 â'¢ Latch
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asynchronous 4bit up down counter using jk flip flop counter 74168 Multiplexer 74152 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000

counter 74168

Abstract: 3-8 decoder 74138 -line data selector 18 74151 Decoders 5 4DE 2-line to 4-line decoder with enable 9 74139 6 4DE1 2-line to 4-line decoder 6 7 8DE 3-line to 8-line decoder with enable 20 74138 8 8DE1 3-line to 8-line decoder 15 Latches/ registers 9 4LT 4-bit data latch 11 10 4LT1 4-bit data latch with reset 13 11 , 41 » 8 3-LINE TO 8-LINE DECODER/ DEMULTIPLEXER 74138 22 9 2-LINE TO 4 , . â'¢ Decoder: 12 â'¢ Comparator: 4 â'¢ Selector/Multiplexer: 7 â'¢ Latch: 12 â'¢ Counter: 20 â
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counter 74169 74183 adder 74169 binary counter 74381 alu 74175 flip flops flip flop 74379 MSM75V000 MSM-76V000 MSM77V000 MSM78V000

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 74138 74139 Logic Function BCD-to-Decimal Decoder 4-Bit Magnitude Comparator 8-Bit Shift Register Divide-by-twelve Counter 4-Bit Binary Counter 4-Bit Shift Register 4-Bit Shift Register 3-Line to 8-Line Decoder / Demultiplexer 2-line to 4-line Decoder/Demultiplexer 8-line to 3-line Priority Encoder 8-line to 1-line Data , /Multiplexer Dual 2-line to 4-line Decoder/Demultiplexer Macro Block Name (0042) (0085) (0091) (0092) (0093
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74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram CI 74151 pin diagram 41 multiplexer 74153 JK Shift Register 74195 MSM60300 MSM60700 MSM61000

74138 decoder

Abstract: 74138 (hereafter indicated as Hi Z). Since only one row/column must be driven at the same time, a decoder (IC5 = 74138) was implemented to save pin count of the µC. 3 output ports were used for row/column selection , = 74138 can be omitted. IC3 & 4 (=74HC125) are separately addressable 3-state buffers. A simple , output port pins can be limited by using a 1-of-8 decoder (74HC138). The 3 bits (A,B,C, respectively , ; ; Decoder Logic: ; Port1: ; P1.7 : active low input; detects rising edge of C1 OR C2 ; should be set
Sames
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40af interfacing 8051 4066 74138 3 to 8 decoder 74138 logic circuit AN3010 75F003 SAN3010 SA253 SA2531/2

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 7 7495 4-Bit Shift Register (0095) 28 8 74138 3-Line to 8-Line Decoder / Demultiplexer (0138) 14 g 74139 2-line to 4-line Decoder/Demultiplexer (0139) 7 10 74148 8-line to 3-line Priority Encoder , BLOCK LIST No. Logic Function Macro Block Name No. of Cells Comment 1 7442 BCD-to-Decimal Decoder , ) 13 14 74155 Dual 2-line to 4-line Decoder /Demultiplexer (0155) 12 tionat blocks and the macro
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bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 74181 74175 clock 74165 block diagram 74151 demultiplexer 74195 TTL shift register MSMC0300

74139 for bcd to excess 3 code

Abstract: design a bcd counter using jk flip flop 153 4 8SE ; 8-line to 1-line data selector 18 74151 Decoders 5 4DE ! 2-line to 4-line decoder with enable 9 74139 6 4DE1 2-line to 4-line decoder 6 1 7 1 8DE 3-line to 8-line decoder with enable 20 74138 8 8DE1 3-line to 8-line decoder 15 Latches/ registers 9 4 LT 4-bit data latch j 11 , -LINE DECODER/ DEMULTIPLEXER 74138 22 9 2-LINE TO 4-LINE DECODER/ DEMULTIPLEXER 1/2 74139 11 10 , time eight-four types of the circuits are prepared which are frequently used. â'¢ Decoder: 12 â
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74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000

as2531

Abstract: ic 74138 (hereafter indicated as Hi Z). Since only one row/column must be driven at the same time, a decoder (IC5 = 74138) was implemented to save pin count of the µC. 3 output ports were used for row/column selection , = 74138 can be omitted. IC3 & 4 (=74HC125) are separately addressable 3-state buffers. A simple , or low at the same time the number of µC output port pins can be limited by using a 1-of-8 decoder , Microcontroller (80C31) = 11.0592 MHz 15 ; 16 ; 17 ; Decoder Logic: 18 ; Port1: 19
austriamicrosystems AG
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as2531 ic 74138 IC 7490 pin configuration pin configuration of IC 74138 AS253X ic 7490 data sheet AS253 AS2531

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 > 4-BIT SHIFT REGISTER 7495 * 8 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER 74138 9 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER 1/2 74139 10 8-LINE TO 3-LINE PRIORITY ENCODER 74148 11 , DECODER 7442 2 4-BIT MAGNITUDE COMPARATOR 7485 1 3 8-BIT SHIFT REGISTER 7491 * 4 , -BIT BINARY COUNTER 1/2 74393 39 EXCESS-3 TO DECIMAL DECODER 7443 40 EXCESS-3 GRAY TO DECIMAL DECODER 7444 41 4-BIT LATCHES " 1/2 74100 42 3-LINE TO 8-LINE DECODER WITH
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binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 full adder using Multiplexer IC 74151 ic 74151 MSM91H000 72MS40 DQQ023 MSM70H00

priority encoder 74148

Abstract: priority encoder 74147 * 8 < 0138 > 3-LINE TO 8-LINE DECODER/ DEMULTIPLEXER 74138 22 9 2-LINE TO 4-LINE DECODER , which are frequently used. â'¢ Decoder: 12 â'¢ Comparator: 4 â'¢ Selector/Multiplexer: 7 â'¢ Latch , < 0042 > BCD-TO-DECIMAL DECODER 7442 24 2 4-BIT MAGNITUDE COMPARATOR 7485 64 3 8 , -BIT BINARY COUNTER 1/2 74393 33 39 EXCESS-3 TO DECIMAL DECODER 7443 24 40 EXCESS-3 GRAY TO DECIMAL DECODER 7444 24 41 4-BIT LATCHES 1/2 74100 16 42 3-LINE TO 8-LINE DECODER WITH
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MSM72000 priority encoder 74147 shift register 7495 msm7200 MSM7000 msm7500 MSM70000 MSM71000 MSM73000 MSM74000 MSM75000

7474 D flip-flop

Abstract: vhdl code for 74154 4-to-16 decoder . The TTL138q is a 3 to 8 bit decoder/de-multiplexer with enable, that is similar to the 74138. The , library also includes a 2-to-4 decoder,DEC2t4, which requires only a single logic cell. XOR2i0 A B , -input AND gates triple 3-input NOR gates 4-to-10 decoder dual D FFs with preset & clear 4-bit D latch , 4-bit D latches with clear 3-to-8 decoder dual 2-to-4 decoders BCD to decimal decoder 8-to-3 priority encoder 16-to-1 multiplexer 8-to-1 multiplexer dual 4-to-1 multiplexers 4-to-16 decoder quad
QuickLogic
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7474 D flip-flop vhdl code for 74154 4-to-16 decoder 7478 J-K Flip-Flop vhdl code for 74194 74138 full subtractor shift register by using D flip-flop 7474

full subtractor circuit using xor and nand gates

Abstract: 74138 full subtractor complement. The TTL138q is a 3 to 8 bit decoder/de-multiplexer with enable, that is similar to the 74138 , library also includes a 2-to-4 decoder, DEC2t4, which requires only a single logic cell. XOR2i0 A B , triple 3-input AND gates dual 4-input AND gates triple 3-input NOR gates 4-to-10 decoder dual D FFs , clear dual J-K FFs with preset & clear dual 4-bit D latches with clear 3-to-8 decoder dual 2-to-4 decoders BCD to decimal decoder 8-to-3 priority encoder 16-to-1 multiplexer 8-to-1 multiplexer dual 4
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full subtractor circuit using xor and nand gates 3-input-XOR vhdl code for 8-bit BCD adder data sheet 74139 vhdl code for 8 bit ODD parity generator 74171

up down counter using IC 7476

Abstract: full adder using Multiplexer IC 74151 multiple from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder and address register logic , -blt with Asyno Load - 34 - DECODER FAMILY COUNTER FAMILY DE2 C11 C41 C42 2:4 Decoder Flip-Flop for Counter 4-blt Asyno 4-blt Syno 5 1 1 24 32 | DE3 C43 C45 C471 3:8 Decoder 4-blt Syno , 74135 74137 74138 74139 74147 74148 74150 74151 74152 74153 74154 74155 74157 74158 74160 74161 74162
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up down counter using IC 7476 74154 shift register IC full adder circuit using ic 74153 multiplexer sk 7443 DN 74352 full adder using ic 74138 0010S MB65XXXX MB66XXXX MB67XXXX

7408, 7404, 7486, 7432 use NAND gate

Abstract: JLCC-68 multiple from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder and address register logic , DECODER FAMILY DE2 2:4 Decoder 5 I DE3 3:8 Decoder 15 COUNTER FAMILY C11 Fllp-Flop for Counter 11 C43 4 , 7455 6 74138 28 74261 107 7456 74139 26 74273 7457 74147 49 74278 46 7464 9 74148 53 74279 18
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LCC-64 JLCC-68 7408, 7404, 7486, 7432 use NAND gate ci 74386 jLCC68 74153 full adder cI 74150 C4002 C1502 CDIP-16 CDIP-18

ic 74226

Abstract: jk flip flop 74103 400 + decoder 16(with NPN Tr) 37(with NPN Tr) 14(with PNP Tr) 28,40,64 S 24,28,40,64 S 44,54,60 44,54 , -to-16 decoder. · H igh b reak d ow n v o lta g e N P N tra n s is to r ( B V ceo). in p u t/o u tp u t b u , 74116 74120 74135 74136 74138 74139 74141 74142 74143 74144 74145 74147 74148 74150 74151 74152 74153
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ic 74226 jk flip flop 74103 ic D flip flop 7474 7471 rs flip flop 4011 flip flop IC 7400 SERIES list RP3G01 3W1X879 00GG71S

V7402

Abstract: V74138 compatible with TTL 74138 Three enable inputs allow parallel expansion up to 1-of-32 decoder , gate 4 Input AND gate 3 Input NOR gate 8 Input NAND gate 2 Input OR gate BCD to Decimal decoder BCD to 7 Segment decoder Dual 2 Wide 2/3 Input AOI Gate 2 Bit Full Adder 4 Bit Full Adder 4 Bit Magnitude Comparator 2 Input XOR gate 13 Input NAND gate 3-to-8 Line Decoder 2-to-4 Line Decoder 8 , with Enable, Active Low Dual 4-to-1 Multiplexer with Enable 4-to-16 Line Decoder Quad 2
Vantis
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V7402 V7410 V7421 V7442 V74138 V74157 V74161 TTL7482 V74169 V74273 V7400 V7408 V7411 V7420

counter 7468

Abstract: umi u26 configured into any by-four multiple from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder , 7 FDR 4-bit DFF with Clear 26 FDS 4-Bit DFF 20 - - - LATCH FAMILY SHIFT REGISTER FAMILY DECODER , -blt with Async Load 34 FS2 4 bit S in -Pout with Sync Load 30 - - - DE2 2:4 Decoder « DE3 3:8 Decoder 15 C11 Flip-Flop for Counter 11 C43 4-blt Sync UP with Clear 48 C41 4-bit Async 24 C45 4 , 7455 6 74138 28 74261 107 7456 74139 26 74273 7457 74147 49 74278 46 7464 9 74148 53 74279 18
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counter 7468 umi u26 ci 7483 74154 chip configuration u26 umi D-6000 J22833 CA95054-3197

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 DECODER 2 TO 4 DECODER W ITH ENABLE 3 TO 8 LINE DECODER W ITH ADD. REGISTERS 3 TO 8 DECODER W ITH ADDRESS LATCHES 1 O F 8 DECODER/M ULTIPLEXER 10 TO 4 LINE ENCODER 8 TO 3 LINE PRIORITY ENCODER 16 BIT DATA SELECTO R W ITH ENABLE 8 INPUT M ULTIPLEXER WITH ENABLE 8 INPUT M ULTIPLEXER 4 TO 16 DECODER Q UADRUPLE 2 T O 1 MULTIPLEXER QUAD 2 INPUT MULTIPLEXER WITH STORAGE BCD TO DECIM AL DECODER (1 TO 10) EXCESS 3 TO DECIM AL DECODER EXCESS 3 TO DECIM AL DECODER BCD TO 7 SEGMENT DECODER 2 TO 1 M ULTIPLEXER W ITH ONE
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circuit diagram for IC 7483 full adder ttl ic 7485 0850R 7483 4 bit binary full adder circuit diagram for 7483 transistor KD 617 ic 7442 encoder 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT

full adder using Multiplexer IC 74151

Abstract: 74151 MUX 8-1 Outputs Active Low (74138) CLS42 BCD to Decimal Decoder (7442) Latches Gate Count DE24G 2 to 4 Decoder , 100 114 12 18 24 30 36 42 48 22 28 31 29 Macro- function Description Name DEM6JN Decoder, Modulo 6 Johnson Counter, Active Low DEM8J Decoder, Modulo 8 Johnson Counter, Active High DEM8JN Decoder, Modulo 8 Johnson Counter, Active Low DEM10J Decoder, Modulo 10 Johnson Counter, Active High DEM10JN Decoder, Modulo 10 Johnson Counter, Active Low DEM12J Decoder, Modulo 12 Johnson Counter, Active
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74151 MUX 8-1 full subtractor using ic 74138 pin configuration IC 74151 modulo 16 johnson counter MUX 74151 MUX 74157 CP20K CP20420
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