500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
LM108AJ8 Linear Technology LM108A - Operational Amplifiers; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
LT1175CDWF#MILDWF Linear Technology LT1175 - 500mA Negative Low Dropout Micropower Regulator; Pins: 5 visit Linear Technology - Now Part of Analog Devices
LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
LT1018MJ8/883 Linear Technology LT1018 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
LTC1041MJ8/883 Linear Technology LTC1041 - BANG-BANG Controller; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
LTC2905HDDB#TRPBF Linear Technology LTC2905 - Precision Dual Supply Monitor with Pin-Selectable Thresholds; Package: DFN; Pins: 8; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy

3-8 decoder 74138 pin diagram

Catalog Datasheet MFG & Type PDF Document Tags

74138 decoder

Abstract: pin diagram of ic 74138 SOJ (small outline J-Lead) package, three 74FCT244A buffers, one 74-138 decoder and forty-two 0.1 , Mega-word by 32 bit static random access memory module in a 80 pin DIP (Dual In-Line Package) pressfit , technologies in SOJ pin format. Performance specifications and electrical characteristics are determined by , buffer is desired. If the pin out configuration is the same as the 74FCT244A and the desired type is available in a standard 20 pin SOP, there should be no problem using it on the module; other equivalent
-
OCR Scan
74138 decoder pin diagram of ic 74138 application of IC 74138 IC 3-8 decoder 74138 pin diagram ic 74138 pin diagram AEPSD1M32

74169 SYNCHRONOUS 4-BIT BINARY COUNTER

Abstract: 74139 demultiplexer 74138 74139 Logic Function BCD-to-Decimal Decoder 4-Bit Magnitude Comparator 8-Bit Shift Register Divide-by-twelve Counter 4-Bit Binary Counter 4-Bit Shift Register 4-Bit Shift Register 3-Line to 8-Line Decoder / Demultiplexer 2-line to 4-line Decoder/Demultiplexer 8-line to 3-line Priority Encoder 8-line to 1-line Data , /Multiplexer Dual 2-line to 4-line Decoder/Demultiplexer Macro Block Name (0042) (0085) (0091) (0092) (0093 , individual resources. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
-
OCR Scan
74169 SYNCHRONOUS 4-BIT BINARY COUNTER 74139 demultiplexer 3-8 decoder 74138 pin diagram 3-8 decoder 74138 CI 74151 pin diagram 41 multiplexer 74153 MSM60300 MSM60700 MSM61000

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER 7 7495 4-Bit Shift Register (0095) 28 8 74138 3-Line to 8-Line Decoder / Demultiplexer (0138) 14 g 74139 2-line to 4-line Decoder/Demultiplexer (0139) 7 10 74148 8-line to 3-line Priority Encoder , BLOCK LIST No. Logic Function Macro Block Name No. of Cells Comment 1 7442 BCD-to-Decimal Decoder , ) 13 14 74155 Dual 2-line to 4-line Decoder /Demultiplexer (0155) 12 tionat blocks and the macro , 's BINALY Logic Simulation. Logic Diagram Test Vectors AC/DC Spec. LEVEL ONE Guided by the OKI CMOS Gate
-
OCR Scan
bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 74181 74175 clock 74165 block diagram 74151 demultiplexer 74169 binary counter MSMC0300

IC 3-8 decoder 74138 pin diagram

Abstract: binary to gray code conversion using ic 74157 > 4-BIT SHIFT REGISTER 7495 * 8 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER 74138 9 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER 1/2 74139 10 8-LINE TO 3-LINE PRIORITY ENCODER 74148 11 , Note: Terminal capacities are average values and include package pin capacities and chip internal pad , DECODER 7442 2 4-BIT MAGNITUDE COMPARATOR 7485 1 3 8-BIT SHIFT REGISTER 7491 * 4 , -BIT BINARY COUNTER 1/2 74393 39 EXCESS-3 TO DECIMAL DECODER 7443 40 EXCESS-3 GRAY TO
-
OCR Scan
binary to gray code conversion using ic 74157 Multiplexer IC 74151 16 bit odd even parity checker using two IC 74180 binary to gray code conversion using ic 74139 7444 series Excess-3-gray code to Decimal decoder full adder using Multiplexer IC 74151 MSM91H000

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 . 4. These inputs can be re-routed to any other I/O PAD. TMODE pin at logic HIGH enables the test mode func tion and then CKTEST pin configures it. CKTEST can also be used as a conventional input signal and , an exam ple the diagram of a DFFNR1, Macro cell (D Flip-Flop with Reset) as it appears to the routing , give n in M HS user's manual. r O PIN vi"! r o p in v p p ] K > H H > °-i I (PMOS , typical access time of 35 ns (for a 256 x 8 SRAM). The block diagram of a 256 x 8 static RAM is descri bed
-
OCR Scan
full adder using ic 74138 circuit diagram for IC 7483 full adder ttl ic 7485 0850R 7483 4 bit binary full adder circuit diagram for 7483 transistor KD 617 0850RT 1300RT 2000RT 2700RT 3200RT 4000RT

92c178

Abstract: OPTi 82C700 . 1 Pin Diagram , Preliminary 82C825 Pin Diagram 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 , operation requires the addition of a 74138 decoder. Selecting between Basic and Extended mode is discussed , .17 160-Pin Plastic Quad Flat Pack (PQFP , . 2 Numerical Pin Cross-Reference List
OPTi
Original
92c178 OPTi 82C700 Manual ttl 74138 SA21D 82C814 82C700

full 18*16 barrel shifter design

Abstract: IC 3-8 decoder 74138 pin diagram is depicted in Figure 1 wherein a simple three to eight decoder is fused into the array. The , generated at the input receivers. Hence, this diagram could be trimmed by six gates, down to eight to , whose inputs span the complete NAND gate foldback structure. 1 OF 8 DECODER/DEMULITPLEXER 8 , ); 8 EN Figure 1. Decoder Implementation in NAND Foldback Structure October 1993 27 , perform customized functions like a 5 to 27 decoder or a 14 to 4 encoder or, even an 18 to 7
Philips Semiconductors
Original
full 18*16 barrel shifter design TTL SN 7404 pn sequence generator using d flip flop 12 bit comparator images of pin configuration of IC 74138 8 bit barrel shifter PLHS501 AN049

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 48mA per pin by means of parallel bond wires within the package. It should be remembered that an I/O , tristate buffer 3 1.01 D24L 2 to 4 decoder 5 0.67 MUX21H 2 to 1 Mux 4 0.80 MUX41 4 to 1 Mux 6 1.12 , multiplexed inputs 37 MR81 8 bit register with 2 bit multiplexed inputs 73 D24H 2 to 4 decoder (outputs active high) 6 D38H 3 to 8 decoder (outputs active high) 19 D38L 3 to 8 decoder (outputs active low) 19 D410H 4 to 10 decoder (outputs active high) 24 MUX41H 4 to 1 multiplexer 8 M150C 16 to 1 gated
-
OCR Scan
74ls82 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 TC140G SC12D4

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC for most requirements. Output drive may be increased from the basic 1mA to a maximum of 48mA per pin , 2 to 4 decoder 2 to 1 Mux 4 to 1 Mux 8 to 1 Mux SR latch with separate gate SR latch with common , 2 to 4 decoder (outputs active high) 3 to 8 decoder (outputs active high) 3 to 8 decoder (outputs active low) 4 to 10 decoder (outputs active high) 4 to 1 multiplexer 16 to 1 gated multiplexer (74LS150 , 0.6, then use 1 Vss2 pin. These pins should be distributed as evenly as possible around the chip
-
OCR Scan
ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 la 4508 ic schematic diagram advantages for ic 7473 4 BIT COUNTER 74669 XF107 SC18D4 SC27D4 SC37D4 SC44D4 SC54D4 SC68D4
Abstract: available in 155-lead Ceramic Pin Grid Array Package. The processor is ideally suited for real-time , Pin Grid Array) package The L64240 performs convolution/correlation operations of the type: L -1 , L64240 M ulti-Bit Filter (MFIR) Block Diagram WE 100 REGADR.O to REGAR.5 _ COEFF , . Pin Listing and Description Note: For all buses, SIGNALY.X denotes the Xth bit of SIGNALY. The , ulti-Bit Filter (MFIR) Pin Listing and Description (Continued) CI.O to CI.7 Coefficient/control -
OCR Scan
L64210/L64211 155-P MIL-STD-883C

images of pin configuration of IC 74138

Abstract: L64240 power HCMOS technology, the L64240 is available in 155-lead Ceramic Pin Grid Array Package. L64240 Chip , Ability to perform Sobel edge extraction Available in 155-lead CPGA (Ceramic Pin Grid Array) package , 2003 lsi logic L64240 M U Iti-Bit Fi Iter (MFIR) Block Diagram ci.o to O CI.7 REGAOR.O _to _ WE REGAR , register length. Pin Listing and Description Note: For all buses, SI6NALY.X denotes the Xth bit of SIGNALY , ) lsi logic Pin Listing and Description (Continued) CI.0toCI.7 Coefficient/control input pins. An 8
-
OCR Scan
DI-74 L64240-15IWCCOM 18 x 16 barrel shifter 4 bit barrel shifter circuit for left shift opera

IC 3-8 decoder 74138 pin diagram

Abstract: full adder using ic 74138 configured into any by-four multiple from 256-by-4 to 32-by-32. The AVM memories contain duplicate decoder , I/O Pin Capacitance S ym b o l C IN CoUT C I/O M in im u m T yp ica l M a x im u m 9 9 11 U nit pF , Capacitance Output Capacitance I/O Pin Capacitance S ym b o l O IN CoUT `-i/o M in im u m T yp ica l M a x im , determined by the location on the chip of the associated circuitry and any pin location requirements that may , 18 30 FS3 - 4 -b lt with Async Load - 34 - DECODER FAMILY COUNTER FAMILY DE2 2:4
-
OCR Scan
pin diagram for IC 7483 for 4 bit adder chip and pin diagram of IC 7491 DN 74352 IC 74195 application of ic 74153 74171 MB65XXXX MB66XXXX MB67XXXX C4002

74194 ring counter

Abstract: grid tie inverter schematic diagram support schematic capture and simulation on popular CAE workstations. BLOCK DIAGRAM /OD OO OO DQQ I/O , Industrial (-40°C to +85°C) c. PACKAGE TYPE J - Plastic Leaded Chip Carrier G = Pin Grid Array - b , 68-pin PLCC 68-pln PGA 84-pin PLCC 84-Dln PGA 175-pin PGA 3020 X X X X 3030 X X 3042 X X , FINISH C = Gold d. PACKAGE TYPE Z = 84-pin PGA (Am3020) Z = 84-pin PGA (Am3030) Z = 132-pin PGA (Am3042)* Z = 132-pin PGA (Am3064)* Z = 175-pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED
-
OCR Scan
74194 ring counter grid tie inverter schematic diagram 74299 universal shift register CI 74241 grid tie inverter schematics 7483 parallel adder pin diagram

AMD K6

Abstract: 74147 decimal to binary encoder easily BLOCK DIAGRAM g /E x u j u u u u u E I/O Blocks / + , Plastic Leaded Chip Carrier G = Pin Grid Array b. SPEED OPTION -50 (50 MHz toggle rate) -70 (70 MHz , TYPE Z = 84-pin PGA (Am3020) Z = 84-pin PGA (Am3030) Z = 132-pin PGA (Am3042)* Z = 132-pin PGA (Am3064)* Z = 175-pin PGA (Am3090) c. DEVICE CLASS /B = Class B b. SPEED/POWER OPTION -50 = 50 MHz , interface between the deviceâ'™s external package pin and the internal user logic. Each IOB includes both
-
OCR Scan
AMD K6 74147 decimal to binary encoder C10BCPRD C10BCRD C10BPRD C10JCR C12JCR C16BARD

IC TTL 7432

Abstract: ic 74138 previously treated lightly. PLHS501 REVIEW The PLHS501 is a 52-Pin, bipolar programmable logic device , x4 X1, X3, X5, X7 x2 O0, O2 x2 x2 x2 Figure 1. PLHS501 Logic Diagram April 1989 , LATCHED D E tPD1 HOLD TIME NAND Gate Diagram OPERATING MODE 21 E tPD0 SETUP , Gate Diagram ns MIN 21 Timing Waveforms: CL G3 G4 G5 CLOCK WIDTH SETUP HOLD , the 74LS74. R ­>Q NAND Gate Diagram 4 (R) G3 G4 G2 G7 2 (D) 1 (C) 5 (Q
Philips Semiconductors
Original
IC TTL 7432 ic 74138 IC 7400 TTL S20 IC 7400 truth table 74521 comparator free 74ls74 pin configurations ODAT15

F9444

Abstract: power control F9444 to 24 MHz â'¢ LS TTL Input/Output Structure with l3L Internal Circuits â'¢ 40-Pin DIP Needing a , Technology â'¢ Comprehensive Family of Support Circuits Pin Functions MULTIPROCESSOR I SIGNALS ] EXTERNAL , Ambient Temperature Under Bias -55 to + 125°C Vcc Pin Potential to Ground Pin -0.5 to +6.0 V Input , Diagram INFORMATION BUS DATA PATHS CONTROL LINES Architecture The F9445 microprocessor comprises three , Status SYN, Pin 7 â'" Synchronize Output â'" Active every cycle; may be used for external
-
OCR Scan
F9444 F9447 F9448 power control F9444 pin diagram priority decoder 74138 MC 74138 pin out diagram of 74138 ic F9444 power control F9446 F9449 F9470

p54c

Abstract: SiS 85C503 shows the system block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC , Address Data Figure 1.1 System Block Diagram Preliminary V2.0 January 9, 1995 1 Silicon , Snoop Frequency · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 January 9, 1995 , Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA HITM# A20M , # TURBO# OSC ACLK CLK PWRGD SiS85C501 Functional Block Diagram Preliminary V2.0 January 9, 1995
Silicon Integrated Systems
Original
p54c SiS 85C503 85c501 85c503 9ROM SiS chipset 85C501/502/503 S85C501 S85C502 S85C503 85C502

IC 3-8 decoder 74138 pin diagram

Abstract: F9444 24 MHz â'¢ LS TTL Input/Output Structure with l3L Internal Circuits â'¢ 40-Pin DIP Needing a Single , Pin Functions MULTIPROCESSOR SIGNALS EXTERNAL REQUESTS bus i CONTROL) CLK _F9445 MR 16 , -65to+150°C Ambient Temperature Under Bias -55 to + 125°C Vcc Pin Potential to Ground Pin -0.5 to +6.0 V , |JU1-nunvc cvciy ojoic, may be used for external synchronization of memory and I/O control. STRBD, Pin 6 â , ; STRBA, Pin 5 â'" Strobe Memory Address Register â'" Active LOW output; active only during normal memory
-
OCR Scan
MSI IC 74138 decoder F9445 self-test 74138 FAIRCHILD 74ls240 bus transfer switch Fairchild 9445 F9445-16DM M38510 F9445-24 F9445-20 F9445-16

IC 3-8 decoder 74138 pin diagram

Abstract: f9444 with Single Clock up to 24 MHz LS TTL Input/Output Structure with l3L Internal Circuits 40-Pin DIP , Technology Comprehensive Family of Support Circuits Pin Functions CLK fOi M ULTIPROCESSOR I , perature Am bient Tem perature Under Bias Vcc Pin Potential to Ground Pin Input Voltage (dc) Input Current , . Timing and Status SYN, Pin 7 - Synchronize O utput - Active every cycle; may be used fo r external synchronization of memory and I/O control. STRBD, Pin 6 - Data Strobe - Active LOW output; active only d u ring
-
OCR Scan
74874 74164 counter pin diagram of ic 74164 74164 with ic PIN DIAGRAM decoder 74138 have three enabled pin

smi 5502

Abstract: T54B block diagram. SRAM CPU Pentium , P54C 373 HOST BUS Address Data PCMC DRAM 244 , * * * 245 ISA BUS Address Data Figure 1.1 System Block Diagram Preliminary V2.0 April 2, 1995 , Buffer Strength · 208-Pin PQFP Package · 0.6µm CMOS Technology Preliminary V2.0 April 2, 1995 , Functional Block Diagram HA[31:3] HBE[7:0]# ADS# M/IO# W/R# D/C# CACHE# BRDY# CPUHOLD CPUHLDA , # SIOREQ# SIOGNT# KBRST#/BREAK# TURBO# OSC ACLK CLK PWRGD SiS5501 Functional Block Diagram
Silicon Integrated Systems
Original
smi 5502 T54B ha 501 4DWS_V20 73 5503 74138 S5501 S5502 S5503
Showing first 20 results.