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Part Manufacturer Description Datasheet BUY
CD74ACT139-W Texas Instruments Dual 2-to-4 Line Decoder/Demultiplexer 0-WAFERSALE visit Texas Instruments
M38510/30702BEA Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 16-CDIP -55 to 125 visit Texas Instruments
M38510/30701BEA Texas Instruments 3-Line To 8-Line Decoders/Demultiplexers 16-CDIP -55 to 125 visit Texas Instruments
M38510/30702B2A Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 20-LCCC -55 to 125 visit Texas Instruments
74AC11139D Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 16-SOIC -40 to 85 visit Texas Instruments
74AC11239N Texas Instruments Dual 2-Line To 4-Line Decoders/Demultiplexers 16-PDIP -40 to 85 visit Texas Instruments

3 to 8 line decoder using 8051

Catalog Datasheet MFG & Type PDF Document Tags

8051 microcontroller based Digital clock with alarm

Abstract: Digital Alarm Clock using 8051 Figure 2: Overview of the microMODUL-8051 Low Power . 5 Figure 3: Pin Layout of the , .10 Table 3: J1 Access to External or Internal Program Memory .11 Table 4: J2 RAM , operated without protection circuitry if connections to the product's pin header rows are longer than 3 m , . © PHYTEC Meßtechnik GmbH 2003 L-305e_3 3 microMODUL-8051 Low Power The microMODUL-8051 Low Power , overloading through connected peripherals. As Figure 3 indicates, all controller signals extend to
PHYTEC
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8051 microcontroller based Digital clock with alarm

Abstract: digital clock with alarm using 8051 , the microMODUL-8051 Low Power has 8 solder jumpers, some of which have been configured prior to , Figure 2: Overview of the microMODUL-8051 Low Power . 5 Figure 3: Pin Layout of the , .10 Table 3: J1 Access to External or Internal Program Memory .11 Table 4: J2 RAM , longer than 3 m. © PHYTEC Meßtechnik GmbH 2001 L-305e_2 1 microMODUL-8051 Low Power PHYTEC , typically draws power via 3 - 4 mignon cells. It can be populated with various 8051
PHYTEC
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74LS00

Abstract: 74LS00 TTL such chip is the 74LS138 3-to-8 decoder which is capable of handling four HCTL-1100s. Read , OSC Figure 1. Interfacing the HCTL-1100 to the 8051 Using I/O Ports , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2.3 P2.3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 2-243 1 2 3 4 5 6 7 8 9 AD0 , \ CS CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32
Hewlett-Packard
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HCTL1100 CS1100 WR1100 74LS00 TTL TTL 74ls00 3 to 8 line decoder using 8051 8051s 74LS00 DATA M-015 HCTL-1100/8051 OE1100 6000H

3 to 8 line decoder using 8051

Abstract: 74LS00 chip could be used. One such chip is the 74LS138 3-to-8 decoder which is capable of handling four , ;* RD1100: SETB P2.0 ; SET R/W LINE TO READ MOV CLR SETB MOV P1,B P2.3 P2.3 P1,#0FFH ; LATCH , HCTL-1100 P2.4 ; BRING RESET LINE HIGH RET 3 1 2 3 4 5 6 7 8 9 AD0 AD1 , CHIP3\ OE CHIP4\ CS CHIP4\ 74LS138 10 9 8 74LS00 RESET 1 µF TO 8051 BUS 10 32 7 , Figure 2. Interfacing the HCTL-1100 to the 8051 Using the Address/Data Bus. 4 R/W OE CS ALE
Avago Technologies
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74LS138 DATASHEET HCTL-1100 M-015 HCTL-1100s LOGIC OF 74LS138 74LS00 application 8051 reset circuit 5964-3776E
Abstract: decoder, all 8 bits are transferred without modification from the input to both the serial and parallel , input is a multi­ plexed encoder/decoder input to provide interleaved signals. The transfer rate of , mode; then the decoder path PSIG[0] must be left open or connected to ground. Embedded Coding The B , always provides the maximum number of bits (up to 5) defined by the code selected. The decoder requires , decoder input. This input signal is applied to bits 1 and 2 o f the parallel input bus. If embedded -
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MIL-STD-883C JC-40
Abstract: E N high. The serial input is a multiplexed encoder/decoder input to provide interleaved signals , given channel for either an encoder or a decoder, all 8 bits are transferred without modification from , 5) defined by the code selected. The decoder requires up to 5 A D PC M bits and a 2-bit encoded input that indicates how many bits are present at the decoder input. This input signal is applied to , ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] A[3] A[4] A[5] D[0] D[1] D[2] D[3] VCC GND D[4] D[5] D[6] D[7] A[6] A[7] A[8] GND -
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8110/8110B 8110B L8110B

tl3101

Abstract: 68HCll decoder, all 8 bits are transferred without modification from the input to both the serial and parallel , Pin Description. 3 Functional class="hl">8 , serial input is a multiplexed encoder/decoder input to provide interleaved signals. The transfer rate of , mode; then the decoder path PSIG[0] must be left open or connected to ground. Embedded Coding The , number of bits (up to 5) defined by the code selected. The decoder requires up to 5 ADPCM bits and a 2
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tl3101 68HCll PCM-123 68hc11 l6 68HC11

80C51

Abstract: APEX20K 8051 Pipelined RISC architecture enables to execute instructions up to 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up , line Read/write of single line and 8-bit group Two 16-bit timer/counters Timers clocked by , control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller , connected to appropriate pins of P3 port. Ports - Block contains 8051's general purpose I/O ports. Each
Digital Core Design
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DP80C51 80C51 APEX20K APEX20KC APEX20KE FLEX10KE DP80390CPU DP80390 DP80390XP

3 to 8 line decoder using 8051

Abstract: 1-wire 8051 code "steals" least 60 s to provide a timing margin power from the data line allows a verfor worst-case , half-wave rectifier to proshown in Figure 1, when the data line vide parasitic power for a line of prodis , pulls the bus low to signal a a unique individual identification code and each 1-wire bit, using short , the MicroLAN and describes its fea- 14.4 kbps data rate (115.2 / 8 = 14.4 kbps), the data line again , a logic level zero any slave connected to the line. The master A clever circuit technique that
Dallas Semiconductor
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1-wire 8051 code DS9097 RS-232

microcontroller 8051 dallas semi datasheet

Abstract: 1-wire 8051 code power from the data line allows a verleast 60 s to provide a timing margin satile new communication , half-wave rectifier to proshown in Figure 1, when the data line vide parasitic power for a line of prodis , pulls the bus low to signal a a unique individual identification code and each 1-wire bit, using short , the MicroLAN and describes its fea- 14.4 kbps data rate (115.2 / 8 = 14.4 kbps), the data line again , indicating a logic level zero any slave connected to the line. The master S DS9097 COM PORT ADAPTER
Dallas Semiconductor
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microcontroller 8051 dallas semi datasheet DS2401 DS0621-SDK DS1986 DS1990A DS2502

E1 PCM encoder

Abstract: PCM61 the input PSIGEN high. The serial input is a multiplexed encoder/decoder input to provide interleaved , channel for either an encoder or a decoder, all 8 bits are transferred without modification from the , encoder always provides the maximum number of bits (up to 5) defined by the code selected. The decoder , decoder input. This input signal is applied to bits 1 and 2 of the parallel input bus. If embedded coding , are detailed in Table 1-2. 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VCC PSIGEN
Conexant Systems
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E1 PCM encoder PCM61 PCM-59 circuit diagram of speech to text with 8051 Bt8110B tellabs

verilog code for 32 bit risc processor

Abstract: verilog code for 16 bit risc processor architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster , module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. All , High Performance Configurable 8-bit Microcontroller ver 3.01 OVERVIEW CPU FEATURES DR8051CPU is a high performance, area optimized soft core of a single-chip 8-bit embedded controller , . DR8051CPU soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are
Digital Core Design
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verilog code for 32 bit risc processor verilog code for 16 bit risc processor 8051 16bit addition, subtraction verilog code for TCON verilog code for 32-bit alu with test bench 8 BIT ALU design with vhdl code DR8051 DR8051XP

PCM-59

Abstract: PCM58 ] PSIG[0] Encoder In Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Decoder In 1 1 I2 13 14 , ] Bt8110 Decoder Out Sign Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Encoder Out 1 1 I2 I3 I4 I5 , Registers B t 8 110 EN_TRPT CODE[3:0] Enable Transparent O peration- Uses the B t8 110 to transfer the 8-bit input to the output w ith out any m odifications for both encoder and decoder channels , /decoder input to provide interleaved signals. The transfer rate of the serial input is one-half the input
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PCM58 L811001

vhdl code mips code

Abstract: standard 8051 Pipelined RISC architecture enables to execute instructions 10 times faster compared to standard 8051 24 times faster multiplication 12 times faster addition Up to 256 bytes of internal (on-chip , Four 8-bit I/O Ports Bit addressable data direction for each line Read/write of single line and 8 , connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface ­ , DP8051 Pipelined High Performance 8-bit Microcontroller ver 4.05 OVERVIEW DP8051 is an ultra
Digital Core Design
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vhdl code mips code

DVB-T Schematic set top box

Abstract: CE6353 IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY , IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR , , life sustaining applications. Intel may make changes to specifications and product descriptions at any , responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This manual
Intel
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CE6231 DVB-T Schematic set top box CE6353 ce6353 design manual ce6230 tuner sd 1228 ce6353 registers D73701-003 ITU-656

PCM-59

Abstract: /decoder input to provide interleaved signals. The transfer rate of the serial input and output is one-half , operation is selected for a given channel for either an encoder or a decoder, all 8 bits are transferred , code selected. The decoder requires up to 5 ADPCM bits and a 2-bit encoded input that indicates how many bits are present at the decoder input. This input signal is applied to bits 1 and 2 of the , AD[0] AD[1] AD[2] SERIAL_IN CLOCK SERIAL_OUT VCC GND AD[3] RESET SYNC CS MICREN AD[4] AD[5] VCC 9 8 7
Rockwell Semiconductor Systems
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8110/B

PCM-59

Abstract: syn 7580 Estimate DECODER Adaptive Predictor Brooktree ® Convert to PCM Synchronous Coding , expected to result in personal injury or death. Brooktree customers using or selling Brooktree products , the input PSIGEN high. The serial input is a multiplexed encoder/decoder input to provide interleaved , channel for either an encoder or a decoder, all 8 bits are transferred without modification from the , always provides the maximum number of bits (up to 5) defined by the code selected. The decoder requires
Brooktree
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syn 7580 Bt8200EVM-T1 circuit diagram of traffic 3 led only tellabs transcoder PCM-122 PCM63

NX5850

Abstract: LCD 128x64 . 8051 Port 2 P2 is an 8-bit bidirectional I/O port. 8051 Port 3 P3 is an 8-bit bidirectional I/O port , i 8051 8-bit CPU General IO ports (Port 1, 2, 3) 64Kbyte external RAM on the chip (Compatible , 8. SYSTEM CONTROL BLOCK . 3 , encoder MP3 Encoder for MPEG1/2 Audio Layer 3 and MP3 Decoder for MPEG1/2/2.5 Audio Layer 3 Includes , of NX5850 8 RTC NX5850 Preliminary Digital Audio SoC 3. Signal Descriptions 9
Nexia Device
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LCD 128x64 8051 mp3 player circuit diagram 0xFF03 NX5855 graphical lcd 128X64 AGND112 FWEN/GPIO10 FREN/GPIO10

object counter circuit using 8051 microcontroller

Abstract: 8051-derivative microMODUL-8051 QuickStart Instructions Using PHYTEC FlashTools98 for Windows and the Keil EK51 , FlashTools98 for Windows .16 2.3 Interfacing the microMODUL-8051 to a Host-PC , .50 4.3 Loading the Example File to the Debugger Environment .53 4.4 Using the Keil tScope , how to run example programs on the microMODUL-8051, mounted on the PHYTEC Development Board, in conjunction with Keil tools. Please refer to the microMODUL-8051 Hardware Manual for specific information on
PHYTEC
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object counter circuit using 8051 microcontroller 8051-derivative Full project report on object counter using seven segment display MSM80C154 80c32 code manual 80C320 MODUL-8051 L-381 D-55135

PCM-59

Abstract: the input P SIG E N high. The serial input is a multiplexed encoder/decoder input to provide , is selected for a given channel for either an encoder or a decoder, all 8 bits are transferred , the maximum number o f bits (up to 5) defined by the code selected. The decoder requires up to 5 A D , ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] A[3] A[4] A[5] D[0] D[1] D[2] D[3] VCC GND D[4] D[5] D[6] D[7] A[6] A[7] A[8] GND , Pin Label I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
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