2C-42 Datasheet, Circuit, PDF, Cross Reference, & Application Note Results |
| Fulltext Datasheet Results |
1 - 37 of about 37 for 2C-42 |
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First line: 2C-45 WATT DC-DC CONVERTERS Abstract: .. 2C-42. 2C-43 2C-43 . 2C-44 2C-44 . 2C-45 2C-45 . 5 VDC. 12 VDC. 24 VDC. 28 VDC. 48 VDC. 5 VDC. 12 VDC. 15 VDC. ±12 VDC. ±15 VDC. 5 VDC. 12 VDC .. Tags: 2C-45 datasheet abstract.. |
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First line: Abstract: .. 2C-42. 2C-43 2C-43 . 2C-44 2C-44 . 2C-45 2C-45 . 5 VDC. 12 VDC. 24 VDC. 28 VDC. 48 VDC. 5 VDC. 12 VDC. 15 VDC. ±12 VDC. ±15 VDC. 5 VDC. 12 VDC .. Tags: datasheet abstract.. |
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First line: wl1271 wl1273* WiLink 7.0 WL1273 wl1271* WL1271 WLAN Bluetooth Coexistence Application Note Literature Number: SPRAB96 January 2010 Contents Revision History. Reference Documents. About This Document Chapter Introduction Abstract: .. 00.1d.46.7c.2c.42 0 -45 Infra 1 B. 00.16.47.93.66.20 1 -45 Infra 1 * 00.1d.46.7c.2c.40 1 -45 Infra 1 test. 00.16.47.93.66.21 0 -45 Infra 1 * 00.16.46.b8.bf.e0 1 -49 Infra 6 Rachel_11g_wep .. Tags: wl1271* WiLink 7.0 WL1273 datasheet wl1273* Wl1271 specification WL1271 SOLUTION PDF WL1271 SOLUTION HARDWARE PDF Wl1271 Solution wl1271 SDIO WL1271 RSSI wl1271 registers WL1271 Hardware design WL1271 datasheet WL1271 |
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First line: Technology PCI9060/68040 DEMO Memory 06/24/96 Configuration Registers Offset 0x00000000 0-15 0x00000002 0-15 0x00000004 0-15 10-15 0-15 9,10 Function Vendor Allocated (Read-only) (Default 10B5) Device Allocated (Read-only) (Default 9060) Command Register, Defined Below (Default each bit) Space, resp Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG -- 44-7F 44-7F xxxx Available for .. Tags: 68040* 4903 PCI9060 68040 |
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First line: PCI9060/68040 July 1995 PCI9060/68040 Application Note VERSION Features_ General Description_ Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/C FG -- 44-7F 44-7F xxxx Available for .. Tags: 68040* PCI9060 68040 |
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First line: Technology MPEG Board 07/15/96 Configuration Registers Offset 0x00000000 0x00000002 0x00000004 0-15 0-15 0-15 10-15 0-15 9,10 Function Vendor Allocated (Read-only) (Default 10B5) Device Allocated (Read-only) (Default 9060) Command Register, Defined Below (Default each bit) Space, response, response Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG -- 44-7F 44-7F xxxx Available for .. Tags: 0x00000000 0x00000002 0x00000004 |
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First line: 82C596 'HOLYHULQJ 9DOXH Abstract: .. ,D2,PMUIORx0,20, 22,24,28/2A,2C,38,40,42,44-5,HWMIORx28-29 HWMIORx28-29 ,35-38,Fn5Rx6,2C,42,48. DH. Revision 1.24 6/18/99 Changed DRVEN to DRVDEN, moved PME# from W11 to T11 MCCS# on U5, SCIOUT# on .. Tags: VT8601* VT8501 North Bridge VT8501 VT82C693* VT82C686A superio flowchart of dc-ac inverter Floppy Disk Subsystem Controller floppy controller pinout AC97 specification 2.3 82C596 datasheet abstract.. |
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First line: Advanced Power Technology Technology Beginning with introduction Power IV®, maintained position forefront power semiconductor technology. focus high voltage, high power high performance segments this market. commitment maintain enhance this position technological leader controlled devices Diodes Abstract: .. // /2C/ - > @ 42 B B / >@/ ," /2C= * />B/ > 2// @ >@ >/ >@/ ," />B= * />@/ >4 2>@ 2 >C 2// >@/ ," />@= * />/ >B 4// - 24 2// >@/ ," />= * @// />4/ >> > @ 4C >> B / >@/ ,"@/>4= * /C/ >- 2// 2 >- >/ >@/ ,"@/C .. Tags: ARF1500 442L 2a37 1hq165 datasheet abstract.. |
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First line: 557: Stratix III-to-Stratix Cross-Family Migration Guidelines September 2009 AN-557-2.0 This application note provides guidelines cross-family migration designs between Altera® Stratix® Stratix device family variant using Quartus® software. these guidelines drop-in replacement either dev Abstract: .. I/O 2C 50 2C 42. I/O 3A 48 3A 48. I/O 3B 48 3B 48. I/O 3C 48 3C 32. I/O 4A 48 4A 48. I/O 4B 48 4B 48. I/O 4C 48 4C 32. I/O .. Tags: EP4SE530 AN-557-2 |
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First line: Mapping Stratix Device Resources HardCopy Devices HIII53003-3.1 This chapter discusses available options mapping from Stratix® device HardCopy device. Quartus software limits resources those available both Stratix FPGA HardCopy ASIC. also ensures that design revision targeting HardCopy device re Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: H1152 HIII53003-3 |
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First line: 68040* part numbering next Section: Designing Memory Board Return Table Contents Using Motorola 68040 with 9060 (Schematics etc.) PCI9060/68040 Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/C FG -- 44-7F 44-7F xxxx Available for .. Tags: 68040* part numbering SR96* tci sig SIG TCI rn0805 68040* PCI9060 68040 |
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First line: External Memory Interfaces Stratix Devices SIII51008-1.1 Stratix® structure been completely redesigned from ground provide flexible high-performance support existing emerging external memory standards. These include high-performance double data rate (DDR) memory standards such DDR3, DDR2, SDRAM; Abstract: .. I/O Bank 2C 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 4 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 3 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: datasheet of BGA Staggered pins SIII51008-1 |
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First line: External Memory Interfaces HardCopy Devices HIII51007-3.0 This chapter describes hardware features that support high-speed memory interfacing each double data rate (DDR) memory standard HardCopy® devices. HardCopy devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-c Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–12 Chapter 7: External .. Tags: HIII51007-3 |
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First line: EP4SE820 EP4SGX180* Mapping Stratix Device Resources HardCopy Devices HIV52003-2.1 This chapter discusses available options mapping from Stratix device HardCopy device. Quartus software limits resources those available both Stratix FPGA HardCopy ASIC. also ensures that design revision targeting Hard Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: EP4SGX180* EP4SGX290 EP4SGX180 EP4SE820H35 EP4SE530* EP4SE* 1152 HIV52003-2 |
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First line: External Memory Interfaces Stratix Devices SIII51008-1.9 Stratix structure been completely redesigned provide flexible, high-performance support existing emerging external memory standards. These include high-performance double data rate (DDR) memory standards such DDR3, DDR2, SDRAM, II+, SRAM, RLDR Abstract: .. I/O Bank 2C 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 3 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 2 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: SIII51008-1 |
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First line: External Memory Interfaces HardCopy Devices HIV51007-2.1 This chapter describes hardware features that support high-speed memory interfacing each double data rate (DDR) memory standard HardCopy® devices. HardCopy devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-ch Abstract: .. I/O Bank 2C 42 User I/Os 3 â—Š4=6 â—Š8/â—Š9=3. â—Š16/â—Š18=1. I/O Bank 1C 42 User I/Os 3 â—Š4=6 â—Š8/â—Š9=3. â—Š16/â—Š18=1. I/O Bank 1A 2 48 User I/Os â—Š4=7 â—Š8/â—Š9=3 â—Š16/â—Š18=1. 1152-pin 1152-pin FineLine BGA. 7–14 Chapter 7: External .. Tags: EP4SGX290 HIV51007-2 |
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First line: L2904 l0312 L9804* la2 d2 timer PIN DIAGRAM OF IC LM7805 next Section: Local Bridge Performance Study Return Table Contents Using 9060 without (SGS Thomson MPEG with 9060) Technology MPEG Board Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG -- 44-7F 44-7F xxxx Available for .. Tags: la2 d2 timer L9804* L2904 vesa local bus TDA1311T R0605 plx9060 pin diagram of IC LM7805 lm7805 12v to 5v 3a L4984* L342* L1032* l0624* l0312 datasheet abstract.. |
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First line: L3580 L2904 l0312 TDA1311T L11616 next Section: Local Bridge Performance Study Return Table Contents Using 9060 without (SGS Thomson MPEG with 9060) 9060/MPEG Abstract: .. 2E 40 0000 MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG 2C 42 0000 LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG -- 44-7F 44-7F xxxx Available for .. Tags: L11616 TDA1311T L2904 L3580 vesa local bus R0605 lm7805 12v to 5v 3a la2 d2 timer l4360* L342* L149* L14728 L1456 L1032* l0312 datasheet abstract.. |
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First line: EP4SGX180* Section HardCopy Design Flow Prototyping with Stratix Devices This section provides description design flow implementation process used HardCopy Design Center. also provides information about mapping Stratix devices HardCopy® devices associated power configuration requirements. This s Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: EP4SGX180* datasheet abstract.. |
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First line: HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC4_H5V2-2.1 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: datasheet abstract.. |
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First line: Section Interfaces This section includes following chapters: Chapter HardCopy Device Features Chapter External Memory Interfaces HardCopy Devices Chapter High-Speed Differential Interfaces HardCopy Devices Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–12 Chapter 7: External .. Tags: datasheet abstract.. |
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First line: HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC3_H5V2-3.1 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: datasheet abstract.. |
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First line: Section HardCopy Design Flow Prototyping with Stratix Devices This section provides description design flow implementation process used HardCopy Design Center. also provides information about mapping Stratix devices HardCopy® devices associated power configuration requirements. This section incl Abstract: .. 2C 42 26 26 26 42 42 42 42. 3A — 40 40 40 40 40 48 48. 3B — — — — 24 24 48 48. 3C 32 24 24 24 32 32 32 32. 4A — 40 40 40 40 40 48 48. 4B — — — — 24 24 48 48. 4C 32 24 24 24 32 32 32 32. 5A 24 32 32 32 48 48 50 50. 5B — — — — — — — 24. 5C 42 26 26 26 42 42 42 .. Tags: datasheet abstract.. |
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First line: 29450 SCHNEIDER telemecanique contactor catalogue NS800N Ready install Distribution boards, rail mounted equipment, enclosures connection systems Isobar distribution boards protective devices Section Modular control products Abstract: .. IHP 2c 42 2 2.5 15722. IHP+ 2c 42 2 2.5 15723. 57. ITM multifunction time switch 60 minute - 7 days plus specified days. Application Weekly or annual programming distributed over 4 output channels from .. Tags: NS800N telemecanique contactor catalogue 29450 SCHNEIDER merlin gerin multi 9 ihp 1c manual schneider pm710 vigi C60 vigi type d mc tripping curves type b mcb tt 104 n 12 transistor ballast 1000W TRANSISTOR 7812 transformers 2507 tr 18650 battery toroidal transformer 20VA TLC 1050 datasheet abstract.. |
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First line: SSTL-15 interlaken higig Section Interfaces This section includes following chapters: Chapter HardCopy Device Features Chapter External Memory Interfaces HardCopy Devices Chapter High-Speed Differential Interfaces HardCopy Devices Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–14 Chapter 7: External .. Tags: interlaken higig SSTL-15 datasheet abstract.. |
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First line: Section Interfaces This section provides information Stratix® device features, external memory interfaces, high-speed differential interfaces with DPA. This section includes following chapters: Chapter Stratix Device Features Chapter External Memory Interfaces Stratix Devices Chapter High-Speed Abstract: .. I/O Bank 2C 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 3 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 2 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: datasheet abstract.. |
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First line: Section Interfaces This section provides information Stratix® device features, external memory interfaces, high-speed differential interfaces with DPA. This section includes following chapters: Chapter Stratix Device Features Chapter External Memory Interfaces Stratix Devices Chapter High-Speed Abstract: .. I/O Bank 2C 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 4 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 3 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: "DDR3 SDRAM" datasheet abstract.. |
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First line: HC335FF1152* HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC3_H5V1-3.2 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or s Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–12 Chapter 7: External .. Tags: HC335FF1152* datasheet abstract.. |
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First line: VT82C693 RX2C VT82C598 VT8601 VIA Apollo mvp4 'HOLYHULQJ 9DOXH Abstract: .. , 22,24,28/2A,2C,38,40,42,44-5,HWMIORx28-29 HWMIORx28-29 ,35-38,Fn5Rx6,2C,42,48. DH. 1.24 6/18/99 Fixed DRVDEN pin name, moved PME#, added MCCS# on U5, SCIOUT# on U8 for CF, Fixed F0Rx42 F0Rx42 ,74,76, F1Rx43 F1Rx43 .. Tags: VIA Apollo mvp4 VT82C598 VT8601* VT8501 VT82C693 vt82c686 VIA Apollo Master SMBus Specification V2.0 SMB T03 RX2C 1010B-3 -"audio and modem functionality" -"Audio-Modem-on datasheet abstract.. |
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First line: HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC3_H5V1-3.2 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–12 Chapter 7: External .. Tags: datasheet abstract.. |
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First line: HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC4_H5V1-2.2 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–14 Chapter 7: External .. Tags: datasheet abstract.. |
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First line: 'HOLYHULQJ 9DOXH Abstract: .. ,D2,PMUIORx0,20, 22,24,28/2A,2C,38,40,42,44-5,HWMIORx28-29 HWMIORx28-29 ,35-38,Fn5Rx6,2C,42,48. DH. Revision 1.24 6/18/99 Changed DRVEN to DRVDEN, moved PME# from W11 to T11 MCCS# on U5, SCIOUT# on .. Tags: VT8601* VT8501 VT82C693 VT82C686A vt82c686 VIA Apollo mvp4 System Management Bus (SMBus) Specification, V2.0 soundblaster SMB T03 RX2C floppy controller pinout datasheet abstract.. |
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First line: advantages and disadvantage of modem CL-CD180 CL-CD180* SMR 53-7 CL-CD1865 Eight full-duplex asynchronous channels supporting data rates 115.2 kbps* Register-based interrupt acknowledges eliminate need separate interrupt acknowledge signals Automatic prioritizing scheme allows device respond interru Abstract: .. D daisy chaining is, 2C, 42, 51 device selection considerations 1 I. E electrical characteristics AC teL c cascading service 42 Channel registers Channel Command 116 Channel Control Status .. Tags: SMR 53-7 CL-CD180* CL-CD180 advantages and disadvantage of modem datasheet abstract.. |
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First line: Altera DDR3 FPGA sampling oscilloscope HardCopy Device Handbook, Volume Innovation Drive Jose, 95134 www.altera.com HC4_H5V1-2.2 Copyright 2010 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that iden Abstract: .. I/O Bank 2C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1C 42 User I/Os 3 ×4=6 ×8/×9=3. ×16/×18=1. I/O Bank 1A 2 48 User I/Os ×4=7 ×8/×9=3 ×16/×18=1. 1152-pin 1152-pin FineLine BGA. 7–14 Chapter 7: External .. Tags: Altera DDR3 FPGA sampling oscilloscope xaui marker beacon antenna interlaken* HD-SDI over sdh h.264 ep4sgx530kh40 EP4SE820H35 DDR3 pcb layout CEI 23-16 3G-SDI serializer datasheet abstract.. |
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First line: vhdl code for carry select adder using ROM 2-bit half adder Stratix Device Handbook, Volume Software Version: Document Version: Document Date: 10.0 July 2010 Abstract: .. I/O Bank 2C 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 3 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 2 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: 2-bit half adder vhdl code for carry select adder using ROM datasheet abstract.. |
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First line: RSEL* "cross reference" add round key for aes algorithm Stratix Device Handbook, Volume SIII5V1-1.1 Copyright 2007 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or serv Abstract: .. I/O Bank 2C 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 4 42 User I/Os 5 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 3 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: add round key for aes algorithm RSEL* "cross reference" vhdl program for SECDED in IC -29C516E Sensors handbook EP3SL EP3SGX BR2477a 102k 400 capacitor SIII5V1-1 |
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First line: HPC 932 verilog code for twiddle factor ROM verilog for Twiddle factor Stratix Device Handbook, Volume Software Version: Document Version: Document Date: 10.0 July 2010 Abstract: .. I/O Bank 2C 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1C 3 42 User I/Os 4 x4=6 x8/x9=3. x16/x18=1. I/O Bank 1A 2 48 User I/Os x4=7 x8/x9=3 x16/x18=1. EP3SE80 EP3SE80 , EP3SE110 EP3SE110 , EP3SL110 EP3SL110 , EP3SL150 EP3SL150 .. Tags: verilog for Twiddle factor verilog code for twiddle factor ROM HPC 932 datasheet abstract.. |
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