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256x32

Catalog Datasheet MFG & Type PDF Document Tags

256x32

Abstract: ATA100 (Receiver Block) SATA RX+/- 256x32 Receiver FIFO (1Kbyte) 16x16 UDMA FIFO Parallel ATA Host , Block) 256x32 Transmitter FIFO (1Kbyte) ATA Bus 16x16 UDMA FIFO Version 1.0 LDIC
LDIC
Original
LDS7011 ATA100 256x32 8B/10B

256X32

Abstract: Mercator ,_^_ | MEPCATOR VFD MODULES_GMW25632CA GMW25632CA Static Active Matrix VFD Module â'¢ 256x32 Fine Dot Matrix â'¢ 135mm x 27mm PCB Dimension â'¢ Low Operating Voltage 15VDC â'¢ Ultra High Brightness Display â'¢ Low RFI Static Drive â'¢ Operating Temperature -40 to +85°C This is a compact and high brightness active matrix vacuum fluorescent display with built in shift registers and latches. It , delivery quotation._ FM Doc No:UNISSUE-DOC-l 1/07/97. MERCATOR VFD MODULES 256x32 Dot ! ACTÌYE MATRIX
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Mercator vfd -driver iee vfd clb-1 failure report clb25 UNISSUE-DOC-08/04/97

16J3

Abstract: A273D 8 M egabit 512x16, 1M x8 70 ,8 5 , 100, 120, 150 449 256x32, 512x16, 1 M x8 256x32, 5 12x16 256x32, 512x16, 1M x8 256x32, 512x16, 1M x 8 256x32. 512x16, 1M x8 20, 25, 35, 45 20, 25, 35
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16J3 A273D 48pin 512X32 168-P DPD16M X32PKW L36PW X36PKW PD32M
Abstract: VFD Module GU-800 series GU256X32-800A 256x32 dot VFD module. Non built-in font type. Specifications Parameter Power Supply Voltage Symbol VCC Min. 4.75 Typ. 5.00 Max. 5.25 Unit VDC Condition - Parameter Logic Input Voltage H L Logic Output Voltage H L Reset Input Voltage H L Symbol Min. Typ. Max. Unit Condition VIH VIL 4.0 - - 1.0 VDC VOH VOL 4.7 - - 0.3 VDC VRH VRL Power Supply Current ICC 4.0 Noritake Itron
Original
10-55-10H

HDMP-1022

Abstract: block diagram simplex has a total of 11,520 RAM bits. Eight of these RAM blocks can be configured as a single 256x32 , bits. Eight RAM blocks were configured as a 256x32 FIFO. This leaves 2 RAM blocks (2,304 bits
QuickLogic
Original
HDMP-1022/1024 QL5030 HDMP-1022 block diagram simplex QL5032 QL5064 125MH

99Q3P0

Abstract: d010000 d010000 256X32, Mux 4, Drive 3, Non-Pipelined High-Speed Single-Port Synchronous SRAM Features Memory Description · Precise Optimization for Infineon's C9DD1 0.20µm The 256X32 SRAM is a high-performance, synchronous single-port, 256-word by 32-bit memory designed to take full advantage of Infineon's C9DD1 0.20µm embedded DRAM process. Embedded DRAM Process · · · · · · · · · Fast Access Time (1.90ns at typical process, 2.50V, 25°C) Fast Cycle Time (1.54ns at typical process, 2.50V
Artisan Components
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99Q3P0 d010000 TAH 190 SRAM timing HS300-SS

a8508

Abstract: XC1702L are four receive data FIFOs (RDFIFO), each 256x32. There are four receive tag FIFOs (RTFIFO), each , UTOPIA bus. Support for up to four ports. - Each port has two 256x32 FIFOs: one for receive and one , other. · Support for up to four ports. Each port has two 256x32 FIFOs, one for receive and one for , UCLK Clock Domain UCLK23 TX_FCLK 32 TX_FDATA-31:0] 32 32 32 Data FIFO 0/256x32 Data FIFO 1/256x32 Data FIFO 2/256x32 Data FIFO 3/256x32 32 8 32 32 8 Data MUX
Intel
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IXB8055 a8508 XC1702L IXF1002 IXF440 IXP1200

8 BIT ALU design by cmos

Abstract: SMQ320C32PCMM50 SMJ320C30 and SMJ320C31 Object Code Compatible · Two 256x32-Bit Single-Cycle, Dual-Access On-Chip RAM
Texas Instruments
Original
SMQ320C50 SMQ320C32 SMQ320C50PQM66 SMQ320C32PCMM50 8 BIT ALU design by cmos texas instruments qfp SGYN128 5962-9455804NZD

architecture of tms320c3x

Abstract: SMQ320C32PCMM50 MEMORY. Two blocks of 256x32 dual access RAM. Each block can provide two accesses to the
Texas Instruments
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TMS320C3X SPRU031 architecture of tms320c3x XDS510XL SPRA020 spru132 5962-9679001NXB SGYV008B SMJ320C3 320C3 TMS320C3 SPRS044

college website design

Abstract: 10671g interfaces. It is capable of supporting up to four ports and has two 256x32 data FIFO's, one for receive
Intel
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college website design 10671g XCV300E 10671G USA/0501/5K/IL10671G
Abstract: (256x32 byte) â'¢ Support for 34b, 50b, 66b addressing â'¢ Support for 8b, 16b S-RIO Transport ids â Integrated Device Technology
Original
TSI721 REVD0711

Intel IXP1200 Network Processor Documentation

Abstract: 110C data FIFOs (RDFIFO), each 256x32. There are four receive tag FIFOs (RTFIFO), each 16x11. If UTO2IX is , two 256x32 FIFOs, one for receive and one for transmit; each FIFO is capable of holding up to sixteen , Data FIFO 0/256x32 32 8 Data Mux / Steering TXCTL_ FRDY[3:0] D D Q Q Q , 32 TXFA_0 TXPADL[1:0] Q Data FIFO 3/256x32 32 Parity Gen D D Data FIFO 2/256x32 8 TXDATA[31:0] TXPRTY_0 TXPRTY_1 TXPRTY_2 TXPRTY_3 D 32 TX_SOP TX_EOP TXSEL
RadiSys
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Intel IXP1200 Network Processor Documentation 110C MXT4400 DATA10 DATA13 DATA12 DATA11 DATA29 DATA30

font ram 16x8

Abstract: yh 4100 ", 5="32X32", 6="12X24") (m=1,2,4 / 1="6X8", 2="8X16", 4="16X32" - 256x32, 256x64, 256x128, 320x32) P(80-1) P , 128x128 256x16 256x32 256x64 256x128 320x32 384x32 512x32 Timing unit +/5% 3900 3900B N/A 14 ms 14 ms
Noritake Itron
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GU256X128C-3900 GU256X128C-3900B GU-3900B GU256 font ram 16x8 yh 4100 GU256X32 Font 16x32 dot font E-M-0044-00 GU320

A12C

Abstract: SPM27C64H20 256x32 8 Vpp 1 28 ]Vdd A12C 2 27 1 PGM A7 3 26 INC A6 4 25 JA8 A5 I 5 (/> 24 1A9 A4 I 6 X 23 3
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SPM27C64H20 A12C PGMH SPM27C64H PF216-02 64K-BIT SPM27C64C H28-9

vram dual port

Abstract: "micro channel" (256x32). · · · XGA software support Drivers XGA driver software for a range of GUI
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vram dual port ims g200 8514/A
Abstract: -STA C K VERY HIGH SPEED CMOS SRAM 256X32 NOTES: 1. All voltages we with respect to Vss. 2. -2.0V -
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DPS256X32BV3 1024K S256X32B 30A04402

mini project using ARM processor

Abstract: FT2232H with the USBee EX 2.0 module. The interface logic consists of AHB master interface and a 256x32 FIFO
Actel
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FT2232H mini project using ARM processor mini project using microcontroller ft2232h spi mini project using ARM microcontroller laptop usb connector pins details AC356

DS08

Abstract: MG802C512 ] Column Address A[7:0] A[7:0] Auto Precharge A8 A8 Page Size 256x32 256x32 Bank, Row and Column
MoSys
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DS08 MG802C512 qfp 64 0.4 mm pitch land pattern MOSYS 100MH A10/BA1 5M-1982 IPC-SM-782

256x32 sgram

Abstract: register with truth table :0] Column Address A[7:0] A[7:0] Auto-Precharge A8 A9 256x32 256x32 Page
Intel
Original
256x32 sgram register with truth table

XC6SL

Abstract: RAMB18 8 M egabit 512x16, 1M x8 70 ,8 5 , 100, 120, 150 449 256x32, 512x16, 1 M x8 256x32, 5 12x16 256x32, 512x16, 1M x8 256x32, 512x16, 1M x 8 256x32. 512x16, 1M x8 20, 25, 35, 45 20, 25, 35
Xilinx
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DS512 XC6SL RAMB18 RAMB36 verilog code hamming 2k bytes hamming decoder vhdl code

GU256X32

Abstract: GU256X32-800A (Receiver Block) SATA RX+/- 256x32 Receiver FIFO (1Kbyte) 16x16 UDMA FIFO Parallel ATA Host , Block) 256x32 Transmitter FIFO (1Kbyte) ATA Bus 16x16 UDMA FIFO Version 1.0 LDIC
Noritake Itron
Original
IMSA-9032B-26P ITRON VFD dc NORITAKE ITRON VFD MODULES 256 x 32 idc connector 10 pin noritake 256 x 32 vfd display japan 80/M68

GU256X32

Abstract: noritake 256 x 32 ,_^_ | MEPCATOR VFD MODULES_GMW25632CA GMW25632CA Static Active Matrix VFD Module â'¢ 256x32 Fine Dot Matrix â'¢ 135mm x 27mm PCB Dimension â'¢ Low Operating Voltage 15VDC â'¢ Ultra High Brightness Display â'¢ Low RFI Static Drive â'¢ Operating Temperature -40 to +85°C This is a compact and high brightness active matrix vacuum fluorescent display with built in shift registers and latches. It , delivery quotation._ FM Doc No:UNISSUE-DOC-l 1/07/97. MERCATOR VFD MODULES 256x32 Dot ! ACTÌYE MATRIX
Noritake Itron
Original
GU256X32-800 imsa-9032 JST-B3B-XH-A BLOCK DIAGRAM OF AC VFD graphic controller scroll 8JAN01

256X32

Abstract: LG256641 has a total of 11,520 RAM bits. Eight of these RAM blocks can be configured as a single 256x32 , bits. Eight RAM blocks were configured as a 256x32 FIFO. This leaves 2 RAM blocks (2,304 bits
Laurel Electronics
Original
LG256641 ST7921 ST7920 LG256

LG256641

Abstract: 256x64 d010000 256X32, Mux 4, Drive 3, Non-Pipelined High-Speed Single-Port Synchronous SRAM Features Memory Description · Precise Optimization for Infineon's C9DD1 0.20µm The 256X32 SRAM is a high-performance, synchronous single-port, 256-word by 32-bit memory designed to take full advantage of Infineon's C9DD1 0.20µm embedded DRAM process. Embedded DRAM Process · · · · · · · · · Fast Access Time (1.90ns at typical process, 2.50V, 25°C) Fast Cycle Time (1.54ns at typical process, 2.50V
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256x64

324-Pin

Abstract: RQFP two 256x32 FIFOs, one for receive and one for transmit; each FIFO is capable of holding up to sixteen , Data FIFO 0/256x32 32 8 Data Mux / Steering TXCTL_ FRDY[3:0] D D Q Q Q , 32 TXFA_0 TXPADL[1:0] Q Data FIFO 3/256x32 32 Parity Gen D D Data FIFO 2/256x32 8 TXDATA[31:0] TXPRTY_0 TXPRTY_1 TXPRTY_2 TXPRTY_3 D 32 TX_SOP TX_EOP TXSEL_ TX_FBE_[3:0] TX_FPS[1:0] TXASIS/TXERR 32 Q Q TX_FDATA[31:0] Data FIFO 1/256x32 Q D
Altera
Original
EP20K400E 324-Pin RQFP 400-pin pga 416 EP20K100 EP20K100E 000PLL LAB16 6466MH 20KESB2 10KFLEX 6000LUT
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