NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| MLH250PSB01B | Honeywell Sensing and Control | Pressure Sensor, GAGE, STRAIN GUAGE PRESSURE SENSOR, 0.25%, 4-20mA, CYLINDRICAL | 
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| MLH250PSB01D | Honeywell Sensing and Control | Pressure Sensor, GAGE, STRAIN GUAGE PRESSURE SENSOR, 0.25%, 0.25-10.25V, CYLINDRICAL |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: : 250ps (maximum) � Bank skew: 200ps (maximum) � Multiple frequency skew: 300ps (maximum) � 3.3V or ... | Original |
14 pages, |
MS-026 ICS8701CYT ICS8701CY ICS8701 datasheet abstract |
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| Abstract: SN65LVDS18 SN65LVDS18, SN65LVP18 SN65LVP18 SN65LVDS19 SN65LVDS19, SN65LVP19 SN65LVP19 www.ti.com SLLS624 SLLS624 SEPTEMBER 2004 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS · FEATURES · · · Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Clock Rates to 1 GHz 250-ps Output Transition Times 0.12 ps Typical Intrinsic Phase Jitter Less than 630 ps Propagation Delay Times 2.5-V or 3.3-V Supply Operation 2-mm x 2-mm Small-Outline No-Lead Package APPLICATIONS · · PECL-to-LVDS Translation Clock ... | Original |
12 pages, |
SN65LVP19 SN65LVP18DRFT SN65LVP18DRFR SN65LVP18 SN65LVDS19DRFT SN65LVDS19 SN65LVDS18DRFT SN65LVDS18DRFR SN65LVDS18 SLLS624 SN65LVDS18 abstract |
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| Abstract: , PCI_F +/- 250pS n/a 48 MHz +/- 500pS 3.3V 1.5V Offset Requirements Characteristic ... | Original |
13 pages, |
C9716J C9716J abstract |
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| Abstract: PI6C3Q991E PI6C3Q991E, PI6C3Q993E PI6C3Q993E 3.3V Programmable Skew PLL Clock Driver SuperClockTM Features Description PI6C3Q99X PI6C3Q99X family provides following products: PI6C3Q991E PI6C3Q991E: 32-pin PLCC version PI6C3Q993E PI6C3Q993E: 28-pin QSOP version Inputs are 5V Tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all ... | Original |
9 pages, |
QS5V993 QS5V991 PS8555 PI6C3Q993E PI6C3Q991E PI6C3Q991E abstract |
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| Abstract: · MREF Output jitter ... | Original |
10 pages, |
ICS9250-33 CRYSTAL 14.318MHZ ICS9250-33 abstract |
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| Abstract: (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input · Part-to-part skew: 250ps ... | Original |
13 pages, |
MS-026 ICS8531AY-01T ICS8531AY-01 ICS8531-01 ICS8531-01 abstract |
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| Abstract: APPROVED PRODUCT SG556 SG556 Mobile Pentium® Processor Application Clock Generator with SSCG, USB and Power Management Support Product Features Frequency Table n n n n n n n n ® Supports clock requirements for Mobile Pentium Processor 2 Host and 5 PCI clocks Separate supply pins for mixed (3.3/2.5V) voltage application. ... | Original |
10 pages, |
SG556BYB SG556 SG556 abstract |
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| Abstract: signal to 2.5V LVPECL levels with a resistor bias on nCLK input · Part-to-part skew: 250ps (maximum ... | Original |
12 pages, |
MS-026 ICS8530DYT ICS8530DY ICS8530 1-TO-16 ICS8530 abstract |
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| Abstract: ) Output Swing (100mV/div.) 800MHz Output TIME (50ps/div.) TIME (250ps/div.) 7GHz Output ... | Original |
11 pages, |
SY58036UMITR SY58036UMI SY58036U SY58035U SY58034U SY58036U abstract |
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| Abstract: Part-to-part skew: 250ps (maximum) · 3.3V output operating supply · 0°C to 70°C ambient operating temperature ... | Original |
12 pages, |
MS-026 ICS8530DY-01T ICS8530DY-01 ICS8530-01 1-TO-16 ICS8530-01 abstract |
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| Abstract: IDT74ALVCH16524 IDT74ALVCH16524 3.3V CMOS 18-BIT 18-BIT REGISTERED BUS TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVCH16524 IDT74ALVCH16524 3.3V CMOS 18-BIT 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883 MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages Extended commercial range of ... | Original |
7 pages, |
SO56-2 IDT74ALVCH16524 18-BIT IDT74ALVCH16524 abstract |
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| Abstract: 0 0 Key Specifications: · CPU Output Jitter , 250ps - 1 500ps 750ps - MSB - - - 2 I C Table: Group Skew Control ... | Original |
24 pages, |
ICS950223 7400 series CMOS Logic ICs XTAL OSC 8.100 20.000 MHZ ICS950223 abstract |
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| Abstract: high-impedance state. 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V ... | Original |
6 pages, |
SO56-2 IDT74ALVC16835A 18-BIT IDT74ALVC16835A abstract |
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| Abstract: fax id: 7057 1CY 74FCT1 74FCT1 635 43 CY74FCT163543 CY74FCT163543 16-Bit Latched Transceiver Features Functional Description · 5V tolerant Inputs and Outputs · 24 mA balanced drive outputs · Low power, pin-compatible replacement for LCX, LPT, LVC, LVCH & LVT families · FCT-C speed at 5.1 ns · Power-off disable outputs permits live insertion · Edge-rate control circuitry for significantly improved noise characteristics · Typical output skew < 250 ps · ESD > 2000V · TSSOP (19.6-mil pitch) and ... | Original |
5 pages, |
CY74FCT163543CPVC CY74FCT163543CPAC CY74FCT163543C CY74FCT163543APVC CY74FCT163543APAC CY74FCT163543A CY74FCT163543 74FCT1 74FCT1 abstract |
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| Abstract: clocked modes. Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883 MIL-STD-883, Method 3015; > 200V ... | Original |
6 pages, |
SO56-2 LVC16601A IDT74LVC16601A 18-BIT IDT74LVC16601A abstract |
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| Abstract: IDT74LVCH162952A IDT74LVCH162952A 3.3V CMOS 16-BIT 16-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVCH162952A IDT74LVCH162952A 3.3V CMOS 16-BIT 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O, BUS-HOLD DESCRIPTION: FEATURES: Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883 MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40°C to ... | Original |
6 pages, |
SO56-2 LVCH162952A IDT74LVCH162952A 16-BIT IDT74LVCH162952A abstract |
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| Abstract: fax id: 7053 1CY 74FCT1 74FCT1 636 52 CY74FCT163652 CY74FCT163652 16-Bit Registered Transceiver Features Functional Description · 5V tolerant Inputs and Outputs · 24 mA balanced drive outputs · Low power, pin-compatible replacement for LCX, LPT, LVC, LVCH & LVT families · FCT-C speed at 5.4 ns · Power-off disable outputs permits live insertion · Edge-rate control circuitry for significantly improved noise characteristics · Typical output skew < 250 ps · ESD > 2000V · TSSOP (19.6-mil pitch) ... | Original |
8 pages, |
CY74FCT163652CPVC CY74FCT163652CPAC CY74FCT163652C CY74FCT163652APVC CY74FCT163652APAC CY74FCT163652A CY74FCT163652 74FCT1 74FCT1 abstract |
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| Abstract: ICS8302I-01 ICS8302I-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT GENERAL DESCRIPTION FEATURES T h e I C S 8 3 0 2I-01 2I-01 i s a l ow s kew, 1 - t o - 2 LVCMOS/LVTTL Fanout Buffer w/ComplemenHiPerClockSTM tary Output a n d a m e m b e r o f t h e HiPerClock S TMfamily of High Performance Clock Solutions from ICS. The ICS8302I-01 ICS8302I-01 has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels. T ... | Original |
8 pages, |
ICS8302I-01 ICS8302AMI-01T ICS8302AMI-01LFT ICS8302AMI-01LF ICS8302AMI-01 ICS8302I-01 abstract |
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| Abstract: MC100LVEL38 MC100LVEL38 3.3V ECL � �6 Clock Generation Chip The MC100LVEL38 MC100LVEL38 is a low skew � �6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is al ... | Original |
8 pages, |
SOIC-20 MC100LVEL38DWR2 MC100LVEL38DW MC100LVEL38 MC100LVEL LVEL38 MC100LVEL38 abstract |
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| Abstract: fax id: 7055 1CY 74FCT1 74FCT1 63H9 52 CY74FCT163952 CY74FCT163952 CY74FCT163H952 CY74FCT163H952 16-Bit Registered Transceiver Features Functional Description · 5V tolerant Inputs and Outputs · 24 mA balanced drive outputs · Low power, pin-compatible replacement for LCX, LPT, LVC, LVCH & LVT families · FCT-C speed at 6.3 ns · Power-off disable outputs permits live insertion · Edge-rate control circuitry for significantly improved noise characteristics · Typical output skew < 250 ps · ESD > 2000V · TSSOP ... | Original |
6 pages, |
CY74FCT163H952C CY74FCT163H952 CY74FCT163952CPVC CY74FCT163952CPAC CY74FCT163952C CY74FCT163952 74FCT1 74FCT1 abstract |
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