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24MHZ

Catalog Datasheet MFG & Type PDF Document Tags

UT54ACTS220

Abstract: ut69151 lxe/dxe synchronized by the falling edge of 24MHz. The SµMMIT drives inputs RCS and DMACK. 14 CLKOUT 5 10 , 24MHz 3 12 CLKIN 4 11 DTACK TEST NC The devices are characterized over full , output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle , NC 1 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 CLKIN 4 11 DTACK
Aeroflex UTMC
Original
UT54ACTS220 UT69151 ut69151 lxe/dxe SUmmit E

UT54ACTS220

Abstract: UT69151 falling edge of 24MHz. The S MMIT drives inputs RCS and DMACK. 14 CLKOUT 5 10 MRST , processes Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View NC 13 24MHz , . The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by 20%. The UT54ACT220 generates a 24MHz clock with a 5% duty cycle variation. The , 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 CLKIN 4 11 DTACK TEST NC
UTMC Microelectronic Systems
Original

225VDD

Abstract: falling edge of 24MHz. The S µMMIT drives inputs RCS and DMACK. The devices are characterized over full , buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The , 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK 14-Lead Flatpack Top View NC CLKOUT CLKOUT CLKIN NC 48MHz VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK
Aeroflex Microelectronic Solutions
Original
225VDD
Abstract: falling edge of 24MHz. The SMMIT drives inputs RCS and DMACK. The devices are characterized over full , buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The , 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK 14-Lead Flatpack Top View NC CLKOUT CLKOUT CLKIN NC 48MHz VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK Aeroflex UTMC
Original

DF2C903P02ACNSA00

Abstract: 72MHZ +25MHz) 15 (fo-25MHz) 7.4 x 9.9 x 3.7 DF2C903P02ACNSA00 903 fo±1.0 3.5 2.0 25 (fo+24MHz) 20 (fo-24MHz) 7.4 x 8.8 x 3.7 DF2C903P02AENSA00 903 fo±1.0 3.5 2.0 35 (fo+24MHz) 15 (fo-24MHz) 7.4 x 8.8 x 3.7 DF2C903P02BCSSA00 903 fo±1.0 3.5 2.0 20 (fo+24MHz) 15 (fo-24MHz) 6.0 x 8.8 x 3.0 DF2C903P02BESSA00 903 fo±1.0 3.5 2.0 15 (fo-24MHz) 30 (fo+24MHz) 6.0 x 8.8 x 3.0 DF2C907P02ACNUA00 906.5 fo±1.0 3.0 2.0 27
Chequers Electronic
Original
DF2C914P01BCSSA00 72MHZ DF2C620P10ASNSA00 DF2C670P10ASNSA00 DF2C796P06ASNSA00 DF2C808P02AENSA00

32KHz

Abstract: ttl crystal oscillator 32khz , ±50ppm, ±100ppm or specify 0~+70, -10~+70, -40~+85 -55~+125 5.0±0.5V, 3.3±0.3V 30mA (32KHz~24MHz) 40mA (24MHz~50MHz) 60mA (50MHz~150MHz) 5.0±10%(1.4V) 15nS (32KHz~9MHz) 10nS (9MHz~32MHz) 0.4V (32KHz~32MHz) 0.5V (32MHz~140MHz) 2.4V 1~10TTL ±3ppm, ±5ppm/Year 20mA (32KHz~24MHz) 40mA (24MHz~80MHz) 20mA (32KHz~24MHz) 40mA (24MHz~80MHz) Input Current Symmetry 5.0±10%(1/2VDD) 10nS (32KHz~24MHz) 6nS (24MHz~80MHz) 0.5V(10%VDD) max 4.5V(90%VDD) min CL=15pF 5.0±10%(1/2VDD) 10nS (32KHz~24MHz) 6nS (24MHz~80MHz
Fronter Electronics
Original
32KHz ttl crystal oscillator 32khz 24MHZ 32-kHz 24-MHZ 32000K 000KH 000MH 155MH 150MH 140MH

interface 8KB ROM and 16KB RAM to 8051

Abstract: MPC89L58A ~ 5.5V 63KB 256B + 1024B 8-bit x 4 16-bit x 3 x1 x2 48MHz@12T Max O.P Frequency 24MHz@ 6T , 4.5V ~ 5.5V 32KB 256B + 1024B 8-bit x 4 16-bit x 3 x1 x2 48MHz@12T 24MHz@ 6T UART MPC89E54A 4.5V ~ 5.5V 16KB 256B + 1024B 8-bit x 4 16-bit x 3 x1 x2 48MHz@12T 24MHz@ 6T UART MPC89E53A 4.5V ~ 5.5V 15KB 256B + 256B 8-bit x 4 16-bit x 3 x1 x2 48MHz@12T 24MHz@ 6T UART MPC89E52A 4.5V ~ 5.5V 8KB 256B + 256B 8-bit x 4 16-bit x 3 x1 x2 48MHz@12T 24MHz@ 6T UART MPC89E51A
Megawin Technology
Original
MEGA51 PQFP44 MPC89L52A MPC89L58A MPC89L556 MPC89L516 interface 8KB ROM and 16KB RAM to 8051 interface 4KB ROM and 8KB RAM to 8051 Leaper-48 MPC82E52 MPC89E52 80C51 6T/12 MPC89E515A MPC89E58A PDIP40

UT54ACTS220

Abstract: ACTS220 24MHz. The SMMIT drives inputs RCS and DMACK. 14-Lead Flatpack Top View NC MRST 48MHz RCS , SMD 5962-96753 PINOUTS 14-Pin DIP Top View NC 1 14 VDD CLKOUT 2 13 24MHz , 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit , 24MHz (4) (3) TEST CLKOUT CLKOUT Note: 1. Logic symbol in accordance with ANSI/IEEE Std
Aeroflex UTMC
Original
ACTS220 MIL-STD-883

silego greenclk

Abstract: SLG3NB Pin Configuration 16 General Description The SLG3NB135 uses a 24MHz quartz crystal to provide one 12MHz clock output and one 24MHz clock output at 2.5mA (typ), and two 32.768kHz clock outputs at , , 0.5mm pitch 2 SLG3NB135 11 3 10 4 9 32.768kHz_A VDDIO_24MHz GND 24MHz 7 8 , single-ended 32.768kHz clock output @ VDDIO_32k · 1 - single-ended 24MHz clock output @ VDDIO_24 · , VDD See Battery Specification 1uF GreenPowerTM VDD & VBAT Switch 24MHz X1 X2 OSC
Silego Technology
Original
NX2016AA silego greenclk SLG3NB crystal quartz 24mhz slg3an001 SILEGO Quartz Crystal 32.768KHz low profile 768KH 000-003NB135-06 SLG3NB135V SLG3NB135VTR 16TQFN

DFC915B26A

Abstract: 24mhz 7*5 24MHz) 8.7 X 7.3 X 3.65 c DFC903B02A 903.00 ±1.0 S 4.0 £0.5 £2.0 £35 (fo + 24MHz) 8.4x5.8x2.8 c S18 (fo - 24MHz) DFC903K02A 903.00 ±1.0 S 4.0 £0.5 £2.0 S 35 (fo + 24MHz) 8.8x5.8x2.8 c DFC903P02A 903.00 ±1.0 S 4.0 £0.5 £2.0 £25 (fo + 24MHz) 8.7x7.3x3.65 c DFC914D01A 914.50 ±0.5 S 3.0  , 927.00 ±1.0 S 3.5 £0.5 £ 2.0 £35 (fo - 24MHz) 8.5 x 7.3 x 3.65 c DFC927B02A 927.00 ±1.0 Sa 4.0 £0.5 £ 2.0 £18(fo + 24MHz) 8.3x5.8x2.8 c S 35 (in 1026MHz) DFC927K02A 927.00 ±1.0 Sa 4.0 Â
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OCR Scan
DFC915B26A DFC2475C06A 24mhz 7*5 DFC927A02A TCO-999G-19.44MHZ 68X73 DFC886P02A DFC903A02A DFC914D01AA DFC914D01AJ DFC914P01A

24mhz crystal 14pin dip

Abstract: by 02 be clock frequencies for multiple CPU clocks and various SOC. Support one CPU clock. One 24MHz clock and , 24MHz/FS 1*^ 7 P LL202-02 · · · · · PIN CONFIGURATION VDD 13 REF/FS 2*^ 12 , one end of the crystal. XOUT 3 O 14.318MHz crystal output. REF/F2* 24MHz/F1* 48MHz/F0 , (high by default). 24MHz 7 B 24MHz output for SUPER I/O after input data latched during , Output Impedance DT Z0 1 REF, 48MHz, 24MHz Measured @ 0.4V ~ 2.4V, C L =10-30pf 1
PhaseLink
Original
PLL202-02 24mhz crystal 14pin dip by 02 be LL2020 phaselink pll202 48MHZ 318MH

80C251TB24

Abstract: ns 62.5 41.7 @ 16M Hz @ 24MHz T lh ll Variable Max ALE Pulse Width @ 16M Hz @ 24MHz 55.5 34.7 Address Valid to ALE Low @ 16M Hz @ 24MHz 49.5 28.7 ns (3) (0.5+M) 2 T OSCâ'˜ 7 ns (3) (0.5+M) 2 T o s C '1 3 Address Hold after ALE Low @ 16M Hz @ 24MHz 10 10 10 ns (4) Address Hold after ALE Low @ 16M Hz @ 24MHz 20 20 20 RD# or PSEN# Pulse Width @ 16M Hz @ 24MHz 115 73.4 (1+N) 2T osc'10 RD# or PSEN# Pulse Width @ 16M Hz @ 24MHz
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OCR Scan
80C251TB24 8XC251TA/TB/TP/TQ C251TA/TB/TP/TQ A2592-02

B2976-01

Abstract: A5001 Space Static Standby to 24-MHz Operation On-chip Data RAM Options: Complete System , @ 16MHz @ 24MHz N/A N/A TLHLL ALE Pulse Width @ 16MHz @ 24MHz 55.5 34.7 (0.5+M) 2TOSC-7 TAVLL Address Valid to ALE Low @ 16MHz @ 24MHz 49.5 28.7 (0.5+M) 2TOSC -13 TLLAX Address Hold after ALE Low @ 16MHz @ 24MHz 10 10 10 TLLAXA Address Hold after ALE Low @ 16MHz @ 24MHz 20 20 20 TRLRH RD# or PSEN# Pulse Width @ 16MHz @ 24MHz
Intel
Original
B2976-01 A5001 XTAL 16Mhz XTAL OSCILLATOR 24MHz 14 PIN DIP 8XC251TA 8XC251TB C251TB/TQ C251S 24-MH 256-K 512-B A4119-01

MIL-PRF-385353

Abstract: 1D-S marking the falling edge of 24MHz. The SuMMIT drives inputs R tS and DMACK. The devices are characterized over , 24MHzis the signal that latches the bTACK outputs. 24MHz is forced high whenever M r ST is low. Properly , chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ±20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state , 9 8 ID VD O 24MHz DTACK TEST BUST H iS DMACK 14-Lead Flatpack Top View NC [ CLKOUTC
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OCR Scan
MIL-PRF-385353 1D-S marking 324MH 000SB2B MIL-PRF-38535

reset

Abstract: MIL-STD-1553 : Hold input MRST to a logic zero voltage level for at least 500ns while applying a minimum of two 24MHz clocks to input 24MHz. After two 24MHz clock periods and 500ns have passed, input MRST can transition back to a logic one voltage level. 24MHz MRST 500ns (minimum) JTAG Reset: Hold input TRST to a logical zero voltage level for at least 500ns while applying a minimum of two 24MHz clocks to input 24MHz.
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Original
MIL-STD-1553 reset MIL-STD-1553 voltage

crystal quartz 24mhz

Abstract: MARKING SMD IC CODE 8-pin Description Features The SLG3PMP122 uses a 24MHz crystal to provide one 24MHz clock output and one , @ VBAT & VDD · 1 - Single-ended 24MHz ref clock output @ VDD Block Diagram VDD VBAT Lithium Poymer ~ 4.2 to 2.8V See Battery Specification 1uF GreenPowerTM VDD & VBAT Switch 24MHz X1 Ultra Low Power PLL OSC X2 32.768kHz 24MHz Pin Configuration 0.18 0.4 Pin 1 8 , ) 7 2 3 5 1.56mm 1 6 X1 VDD 24MHz NC 2 0.18 4 0.4 (Top View
Silego Technology
Original
000-003PMP122-0993 MARKING SMD IC CODE 8-pin SILEGO 32.768 slg3 32FERRI Quartz Crystal 32.768KHz SLG3PMP122V SLG3PMP122VTR SLG3PMP122C SLG3PMP122CTR

MPC130

Abstract: MPC320 48MHz @ 12T 24MHz @ 6T 4K Max NA 3-Level 6KV MPC89E58 4.5V~5.5V 32K 256+1024 x1 x2 48MHz @ 12T 24MHz @ 6T 4K Max 30K Max 3-Level 6KV Sink Operation , 4.5V~5.5V 16K 256+1024 x1 x2 48MHz @ 12T 24MHz @ 6T 4K Max 46K Max 3-Level 6KV MPC89E53 4.5V~5.5V 15K 256+256 x1 x2 48MHz @ 12T 24MHz @ 6T 4K Max NA 3-Level 6KV MPC89E52 4.5V~5.5V 8K 256+256 x1 x2 48MHz @ 12T 24MHz @ 6T
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Original
MLC331B MLC081B MPC320 MPC130 QFN-48 infineon MPC89L556X2 DAC Combo 8X2 LCD MLC017B MLC021B MLC031B MLC041B MLC061B

USB3315

Abstract: USB3315C USB3315 Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface 24MHz Reference Clock PRODUCT , or ground 24MHz Reference Clock Operation Carkit UART mode for non-USB serial data transfers , 24MHz Reference Clock Order Number(s): USB3315C-CP-TR FOR 24 PIN, QFN LEAD-FREE ROHS COMPLIANT , USB3315 REV C Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 24MHz Reference Clock , systems architectures based on a 24MHz reference clock. It is designed to be used in both commercial and
Standard MicroSystems
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USB331X USB3315C VDD18

80C251TB24

Abstract: 273129 to 24-MHz Operation On-chip Data RAM Options: 512-Byte Complete System Development Support , 0 24 FOSC XTAL1 Frequency N/A N/A TOSC 1/FOSC @ 16MHz @ 24MHz N/A N/A TLHLL ALE Pulse Width @ 16MHz @ 24MHz 55.5 34.7 (0.5+M) 2TOSC-7 TAVLL Address Valid to ALE Low @ 16MHz @ 24MHz 49.5 28.7 (0.5+M) 2TOSC-13 TLLAX Address Hold after ALE Low @ 16MHz @ 24MHz 10 10 10 TLLAXA Address Hold after ALE Low @ 16MHz @ 24MHz 20
Intel
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273129 8XC251TP 8XC251TQ A4118-01 A4117-01

TSPF

Abstract: W48S67 Selection CPU Clock Frequency Selection 48/24MHz clock outputs can be set to 48MHz or 24MHz. Provides CPU , outputs separately selectable as 24MHz or 48MHz (default = 48MHz) · VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% · , PLL2 48/24MHZ 48/24MHZ REF1 Table 1 Pin Selectable Frequency (Note) CPU, SDRAM Clocks (MHz) 60 , VDDQ3 PCI_F PCI0 GND PCI1 PCI2 PCI3 PCI4 VDDQ3 PCI5 GND 60/66_SEL SDATA SCLOCK VDDQ3 48/24MHZ 48/24MHZ , controlled by voltage applied to VDDQ3. IOAPIC 48/24MHz 45 22, 23 O O I/O APIC Clock Output
IC Works
Original
TSPF W48S67 W48S87-72 W48S67-72 48/24MHZ

AT89C51 microcontroller

Abstract: sab8031a-p buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The , falling edge of 24MHz. The S µMMIT drives inputs RCS and DMACK. The devices are characterized over full , 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK 14-Lead Flatpack Top View NC CLKOUT CLKOUT CLKIN NC 48MHz VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK
Atmel
Original
AT89C51 microcontroller sab8031a-p SAB8051A-P P8052AH SAB8051A MICROCONTROLLER AT89C51 datasheet 80C31 87C51 80C52 87C52 MCS-51 AT89C51

at89c51

Abstract: atmel at89c52 processes Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View NC 13 24MHz , . The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by 20%. The UT54ACT220 generates a 24MHz clock with a 5% duty cycle variation. The , falling edge of 24MHz. The S MMIT drives inputs RCS and DMACK. 14 CLKOUT 5 10 MRST , 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 CLKIN 4 11 DTACK TEST NC
Atmel
Original
AT89C52 89CXX atmel at89c52 ATmel AT89C51 AT89C51-24PI data sheet of at89c51 AT89C5X atmel AT89C2051-24PI AT89C5X-XXXX-5 AT89C51-12 DM/883 S8252-24PI

80C251TB24

Abstract: A4532-02 32 Programmable I/O Lines s Static Standby to 24-MHz Operation s 64-Kbyte Extended Stack Space , FOSC XTAL1 Frequency N/A N/A TOSC 1/FOSC @ 16MHz @ 24MHz N/A N/A TLHLL ALE Pulse Width @ 16MHz @ 24MHz 55.5 34.7 (0.5+M) 2TOSC -7 TAVLL Address Valid to ALE Low @ 16MHz @ 24MHz 49.5 28.7 Units MHz (0.5+M) 2TOSC-13 ns 62.5 41.7 ns (3) ns (3) TLLAX Address Hold after ALE Low @ 16MHz @ 24MHz 10 10 10 TLLAXA Address Hold after
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OCR Scan
A4532-02

80C251TB24

Abstract: XTAL OSCILLATOR 24MHz 14 PIN DIP +25MHz) 15 (fo-25MHz) 7.4 x 9.9 x 3.7 DF2C903P02ACNSA00 903 fo±1.0 3.5 2.0 25 (fo+24MHz) 20 (fo-24MHz) 7.4 x 8.8 x 3.7 DF2C903P02AENSA00 903 fo±1.0 3.5 2.0 35 (fo+24MHz) 15 (fo-24MHz) 7.4 x 8.8 x 3.7 DF2C903P02BCSSA00 903 fo±1.0 3.5 2.0 20 (fo+24MHz) 15 (fo-24MHz) 6.0 x 8.8 x 3.0 DF2C903P02BESSA00 903 fo±1.0 3.5 2.0 15 (fo-24MHz) 30 (fo+24MHz) 6.0 x 8.8 x 3.0 DF2C907P02ACNUA00 906.5 fo±1.0 3.0 2.0 27
Intel
Original

CH9054

Abstract: Description Features The SLG3PMP122 uses a 24MHz crystal to provide one 24MHz clock output and one , @ VBAT & VDD · 1 - Single-ended 24MHz ref clock output @ VDD Block Diagram VDD VBAT Lithium Poymer ~ 4.2 to 2.8V See Battery Specification 1uF GreenPowerTM VDD & VBAT Switch 24MHz X1 Ultra Low Power PLL OSC X2 32.768kHz 24MHz Pin Configuration 0.18 0.4 Pin 1 8 , ) 7 2 3 5 1.56mm 1 6 X1 VDD 24MHz NC 2 0.18 4 0.4 (Top View
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OCR Scan
CH9054 1DD4133 CH9054A CH9054X-N CH9054X-S CH9054X-N-L

80C51FA

Abstract: 83C51FA ns 62.5 41.7 @ 16M Hz @ 24MHz T lh ll Variable Max ALE Pulse Width @ 16M Hz @ 24MHz 55.5 34.7 Address Valid to ALE Low @ 16M Hz @ 24MHz 49.5 28.7 ns (3) (0.5+M) 2 T OSCâ'˜ 7 ns (3) (0.5+M) 2 T o s C '1 3 Address Hold after ALE Low @ 16M Hz @ 24MHz 10 10 10 ns (4) Address Hold after ALE Low @ 16M Hz @ 24MHz 20 20 20 RD# or PSEN# Pulse Width @ 16M Hz @ 24MHz 115 73.4 (1+N) 2T osc'10 RD# or PSEN# Pulse Width @ 16M Hz @ 24MHz
Intel
Original
8XC51FX 83C51FA 87C51FA 80C51FA 83C51FB 87C51FB 83C51FC FA/83C5 FB/83C5 FB/87C5 FC/83C5 8K/16K/32K
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