NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Outline Dimensions All dimensions in inches. -sa 50 -I I I I fç _ 020 DIA ri SPX 1873 zmiM 5 L 500- r 30 MIN I_ 020 DIA - j020X 02C SQ \ pfsêesl. 100 M I _I I- 750-1 L- 1 00 - fi" m SPX 1874 L- 490« r 30 MIN i_ 020 ROUND -I 22ol- 100 -pp- I L- 750-J 750-J I \- 970 -J SPX1878 SPX1878 HëHffl I U 490 - H 25«| p- 30 MIN 220 !•- m - 970 -J SPX 2762 "T - 530-4 IL 3 JE» 125-J 125-J L- 245 S'il ^- 875 -J \Ll JXarr- If I r |r Q MENTATION «AB« JT If LJ » ... | OCR Scan |
1 pages, |
SPX1878 spx 2762 1L transistor 3 pin spx 1404 datasheet abstract |
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| Abstract: SPX1874 30 MIN i_ 020 ROUND -I 22ol- 100 -pp- I L- 750-J 750-J I \- 970 -J SPX1878 SPX1878 HëHffl I U 490 - H ... | OCR Scan |
2 pages, |
SPX1878 spx 1404 1879-15 optical IC 7421 photosensor phototransistor 1878 TRANSISTOR spx 2762 d 1879 TRANSISTOR D 1878 TRANSISTOR datasheet abstract |
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| Abstract: m spx 1874 L- 490« r 30 MIN i_ 020 ROUND -I 22ol- 100 -pp- I L- 750-J 750-J I \- 970 -J ... | OCR Scan |
3 pages, |
SE-5455-3 SE-5455-2 SE-2460-3 SE-1450-4 SD-5421-2 datasheet abstract |
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| Abstract: m SPX 1874 L- 490« r 30 MIN i_ 020 ROUND -I 22ol- 100 -pp- I L- 750-J 750-J I \- 970 -J ... | OCR Scan |
3 pages, |
SPX1878 sdp 8403 SD-1440-4 datasheet abstract |
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| Abstract: LQ065 hq4 8330 b17b Freescale Semiconductor, Inc. 2UGHU#WKLV#GRFXPHQW#E\ 3UHOLPLQDU\²1RW#\HW#VWRFNHG Freescale Semiconductor, Inc. $GYDQFH#,QIRUPDWLRQ $70&#(9% $70#&HOO#3URFHVVRU#(YDOXDWLRQ#%RDUG#8VHU·V# 0DQXDO 7KLV#PDQXDO#SURYLGHV#LQIRUPDWLRQ#IRU# $70&#(9%/#%RDUG#5HYLVLRQ#(1*#+72424 ... | Original |
240 pages, |
PDFK553D g 6551 80531 5.1B1 8653 p 16b3 datasheet abstract |
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| Abstract: 4 3 2 THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION 103639 , 103639 COPYRIGHT 103639By ALL RIGHTS RESERVED. LOC AD DIST 00 REVISIONS DESCRIPTION DWN APVD W4 REVISED PER ECO-1 1-00871 0 27APR11 27APR11 HMR JG 0.38[.01 5] D TYP AT POST TIPS 0.64+0.02 [.025 + .001 C 3\ 1.52 + 0.08 [.060 + .003] 3 05+0.1 3 _u -0.18 19H+.005 • -.007 1.52 + 0.08 [.060 + .003] A A A A A nlJnlJnlJnlln A A A A "irwirirT .000100 BRIGHT TIN-LEAD OVER .000050 NICKEL POINT OE MEASUREMENT EOR ... | OCR Scan |
2 pages, |
datasheet abstract |
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| Abstract: 7 6 5 THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION COPYRIGHT - By - ALL RIGHTS RESERVED. o 0.38 [.015]® TYP AT POST TIPS AAA nlJnlJnlJnU^ A A A A A ft \J 0.65 + 0.02 [.025 + .001] W TrwirwT < > 0.38 ;.oi5]® TYP AT POST TIPS CL < 13.59 + 0.20 [.535 + .008] 1.52 + 0.08 3A [.060 + .003] 3.05 .120' + 0.13 -0.18 + .005 -.007 1.52 + 0.08 [.060 + .003] 5.08 + 0.08 [.200 + .003] 6.98 .275 + 0.43 -0.30 + .017 -.012 5.08 [.200] 2.54 [.100] < > 0.38 ;.oi5]® - 0. ... | OCR Scan |
2 pages, |
32Q1 datasheet abstract |
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| Abstract: 7 6 5 THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION COPYRIGHT - BY TYCO ELECTRONICS CORPORATION. ALL RIGHTS RESERVED. o 0.38 [.015]® TYP AT POST TIPS AAA nlJnlJnlJnU^ A A A A A ft \J 0.65 + 0.02 [.025 + .001] W TrwirwT < > 0.38 ;.oi5]® TYP AT POST TIPS CL < 13.59 + 0.20 [.535 + .008] 1.52 + 0.08 3A [.060 + .003] 3.05 .120' + 0.13 -0.18 + .005 -.007 1.52 + 0.08 [.060 + .003] 5.08 + 0.08 [.200 + .003] 6.98 .275 + 0.43 -0.30 + .017 -.012 5.08 [.200] 2.54 [.100] < > 0.38 ;.oi5]® 0.64+0.05 ... | OCR Scan |
2 pages, |
datasheet abstract |
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| Abstract: LI I I- U M5L8216P M5L8216P / M5L8226P M5L8226P T-5Z-0°\ MITSUBISHI (MICMPTR/HIPRC) 4-BIT PARALLEL BIDIRECTIONAL BUS DRIVERS DESCRIPTION The M5L8216P M5L8216P and M5L8226P M5L8226P are 4-bit bidirectional bus drivers and suitable (or the 8-bit parallel CPU M5L8085AP M5L8085AP. FEATURES • Parallel 8-bit data bus buffer driver • Low input current DIEN, CS: Dl, DB: • High output current M5L8216P M5L8216P DB: Ii'l=-500/iA(max.) DO: M5L8226P M5L8226P DB: DO: lOL=55mA(max.) Ioh=-10mA(max.) l0h=-1nf)A(max.) lol=50mA(max.) lOH=."-' ... | OCR Scan |
4 pages, |
ZNR mitsubishi M5L8226P M5L8216P ZNR v M5L8085 M5L8085AP M5L8216P abstract |
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| Abstract: DESCRIPTION The 8200/8201/8202/8203 MSI Buffer Registers are arrays of ten clocked "D" flip-flops especially suited for parallel-in parallel-out register applications. They are also suitable for general purpose applications as parallelIn serial-out, serial-in parallel-out registers. The flip-flops are arranged as dual 5 arrays, (8200 and 8201) and single 10 arrays with reset, (8202 and 8203). The true output of each bit is made available to the user. The 8200 and 8202 feature true "D" inputs. ... | OCR Scan |
3 pages, |
S8202F N8200F N8200N N8201F N8201N N8202F 8201 N8203F N8203N S8200F S8201F 8203 N8202N pin diagram of 8203 datasheet abstract |
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| Abstract: 7 6 2 THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION COPYRIGHT - BY TYCO ELECTRONICS CORPORATION. ALL RIGHTS RESERVED. LOC AD DIST 00 REVISIONS p LTR DESCRIPTION DATE DWN APVD AA 0G3C-0789-04 0G3C-0789-04 24FEB05 24FEB05 MB JG AA1 REVISED PER EC0-09-021826 EC0-09-021826 8JAN10 8JAN10 KK AEG D C B A 0.64+0.02 [.025+.0P 1 ] I DETAIL Z POST DETAIL TYP 2 POST MINIMUM TYP AT POST TIPS REF 6.98 /\ SP AT 2.54 [. 1 QQ] 2.54 [. 1 QO] + 0.43 -0.30' + .017 [•275_.oi2, I- 5.08+0.08 [.200 +.PP3] 5.84+0.38 -[.230+.0 1 5] 5.08-[ . ... | OCR Scan |
2 pages, |
T2300 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| ;: res_no_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Beta-5.2.0b, Fri Jun 2 17:02:48 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet add_17/n27 GB.X HB.F4 Netdelay add_17/n27 HB.F4 1.2 Program add_17/n27 {79G418 79G418 79G418 79G418} {72G418 72G418 72G418 72G418} NProgram add_17/n27 row.H.local.2:HB.F4 row.H.local.2:GB.X Addnet add_17/n28 GB.Y LD.F1 MD.F1 Netdelay add_17/n28 LD.F1 3.2 MD.F1 3.2 Program add_17/n28 {137G204 137G204 137G204 137G204} {137G248 137G248 137G248 137G248} {137G358 137G358 137G358 137G358} {107G358 107G358 107G358 107G358} {100G365 100G365 100G365 100G365} {100G409 100G409 100G409 100G409} {100G420 100G420 100G420 100G420} {100G442 100G442 100G442 100G442} NProgram add_17/n28 col.D.long.1:MD.F1 col.D.l www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/res_shar/res_no_s.lca |
Xilinx | 02/06/1995 | 27.48 Kb | LCA | res_no_s.lca |
| ;: res_no_share.lca (4005PC84-5 4005PC84-5 4005PC84-5 4005PC84-5), xdelay Beta-5.2.0b, Fri Jun 2 17:02:48 1995 Version 2 Design 4005PC84 4005PC84 4005PC84 4005PC84 4 0 Speed -5 Addnet add_17/n27 GB.X HB.F4 Netdelay add_17/n27 HB.F4 1.2 Program add_17/n27 {79G418 79G418 79G418 79G418} {72G418 72G418 72G418 72G418} NProgram add_17/n27 row.H.local.2:HB.F4 row.H.local.2:GB.X Addnet add_17/n28 GB.Y LD.F1 MD.F1 Netdelay add_17/n28 LD.F1 3.2 MD.F1 3.2 Program add_17/n28 {137G204 137G204 137G204 137G204} {137G248 137G248 137G248 137G248} {137G358 137G358 137G358 137G358} {107G358 107G358 107G358 107G358} {100G365 100G365 100G365 100G365} {100G409 100G409 100G409 100G409} {100G420 100G420 100G420 100G420} {100G442 100G442 100G442 100G442} NProgram add_17/n28 col.D.long.1:MD.F1 col.D.l www.datasheetarchive.com/download/98542422-996536ZC/xsiverlg.tar |
Xilinx | 20/01/1997 | 8960 Kb | TAR | xsiverlg.tar |
| ;: alarm.lca (4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5), ppr Xilinx:ppr:Beta-5.2.0a:95/05/30, 1995/06/01 14:50:53 Version 2 Design 4005APC84 4005APC84 4005APC84 4005APC84 Speed -5 Addnet U1/U1/CURRENT_STATE FB.XQ GD.F4 GC.F4 GB.G4 FC.G3 NProgram U1/U1/CURRENT_STATE GD.F4:row.G.local.4 GD.24.1.9 GD.24.1.20 GC.F4:row.G.local.4 GC.24.1.9 GC.24.1.20 GB.G4:row.G.local.4 FB.XQ:row.G.local.4 NProgram U1/U1/CURRENT_STATE FC.G3:col.D.local.0 GD.24.1.18 GD.24.1.0 FB.XQ:row.G.local.6 Addnet N76 FB.K KB.K LB.K MB.K JC.K KC.K NC.K OC.K DC.K EC.K Addpin N76 www.datasheetarchive.com/files/xilinx/bbs/swhlp/synopsys/verilog/alarm/alarm.odf |
Xilinx | 01/06/1995 | 96.26 Kb | ODF | alarm.odf |
| ;: alarm.lca (4005APC84-5 4005APC84-5 4005APC84-5 4005APC84-5), ppr Xilinx:ppr:Beta-5.2.0a:95/05/30, 1995/06/01 14:50:53 Version 2 Design 4005APC84 4005APC84 4005APC84 4005APC84 Speed -5 Addnet U1/U1/CURRENT_STATE FB.XQ GD.F4 GC.F4 GB.G4 FC.G3 NProgram U1/U1/CURRENT_STATE GD.F4:row.G.local.4 GD.24.1.9 GD.24.1.20 GC.F4:row.G.local.4 GC.24.1.9 GC.24.1.20 GB.G4:row.G.local.4 FB.XQ:row.G.local.4 NProgram U1/U1/CURRENT_STATE FC.G3:col.D.local.0 GD.24.1.18 GD.24.1.0 FB.XQ:row.G.local.6 Addnet N76 FB.K KB.K LB.K MB.K JC.K KC.K NC.K OC.K DC.K EC.K Addpin N76 www.datasheetarchive.com/download/98542422-996536ZC/xsiverlg.tar |
Xilinx | 20/01/1997 | 8960 Kb | TAR | xsiverlg.tar |
| ;: plgply.lca (4005PQ160-6 4005PQ160-6 4005PQ160-6 4005PQ160-6), xdelay 5.1.0, Fri May 19 13:26:54 1995 Version 2 Design 4005PQ160 4005PQ160 4005PQ160 4005PQ160 4 0 Speed -6 Addnet $1N199 1N199 1N199 1N199 EH.X TBUF.BK.1.T TBUF.BK.2.T TBUF.CK.2.T TBUF.CK.1.T TBUF.DK.2.T TBUF.DK.1.T TBUF.EK.2.T TBUF.EK.1.T DH.F1 Netdelay $1N199 1N199 1N199 1N199 TBUF.BK.1.T 4.3 TBUF.BK.2.T 4.3 TBUF.CK.2.T 4.3 TBUF.CK.1.T 4.3 TBUF.DK.2.T 4.3 TBUF.DK.1.T 4.3 TBUF.EK.2.T 4.3 TBUF.EK.1.T 4.3 DH.F1 2.8 Program $1N199 1N199 1N199 1N199 {404G667 404G667 404G667 404G667} {404G649 404G649 404G649 404G649} {404G623 404G623 404G623 404G623} {404G605 404G605 404G605 404G605} {404G579 404G579 404G579 404G579} {404G561 404G561 404G561 404G561} {404G535 404G535 404G535 404G535} {404G517 404G517 404G517 404G517} {404G500 404G500 404G500 404G500} {376 www.datasheetarchive.com/download/24288047-960681ZC/plugplay.zip (PLGPLY.LCA) |
Xilinx | 20/05/1995 | 240.04 Kb | ZIP | plugplay.zip |