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SN74ABT620NSRE4 Texas Instruments ABT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20 pdf Buy
SN74ABT620NSR Texas Instruments Octal Bus Transceivers With 3-State Outputs 20-SO -40 to 85 pdf Buy
SN74ABT620NSRG4 Texas Instruments ABT SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20 pdf Buy

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20N Apex Tool Group Wiss; 10 1/4 in Forged Steel; Heavy Duty in.dustrial Shears; in.laid from $43.00 (Sep 2016) Allied Electronics Buy
20N03HL - - 77 (Aug 2016) Chip One Exchange Buy
20N2000 - - 3,400 (Aug 2016) America II Electronics Buy
20N40C1 Harris Semiconductor undefined 1 (Sep 2016) Rochester Electronics Buy
20N40CID Harris Semiconductor 20N40 HAR 1 (Aug 2016) Rochester Electronics Buy
20N5000 Pico Electronics - 4,000 (Aug 2016) America II Electronics Buy
20N60C3 Infineon Technologies - 148 (Sep 2016) Bristol Electronics Buy
20NEU125B Eaton OEM LC Neutral Assy, 125A, (20)# 14-4 CU/AL 120 from $64.33 (Aug 2016) Newark element14 Buy
20NEU125B-1 Eaton 125A Max #6-1/0 CU or #6-2/0 AL Main Terminal, (20) #14-4 CU from $81.88 (Aug 2016) Newark element14 Buy
20NH00AM-6 Altech Fuse; Pwr Dist; Fast Acting; 20A; Class aM; Dims 2.05x1.1x1.67"; Blade 9 from $7.19 (Sep 2016) Allied Electronics Buy
20NH00AM-6 Altech Specialty Fuses NH aM 600vac 20A 48x20x36mm(LxWxD) from $5.37 (Sep 2016) Mouser Electronics Buy
20NH00G-690 EATON Fuse NH 20A 690V Holder Flat 49 X 30 X 48mm (Aug 2016) Sager Buy
20NH00GL Altech Fuse; Pwr Dist; Slow Blow; 20A; Class gL/gG; Dims 2.05x1.1x1.67"; Blade 11 from $7.28 (Sep 2016) Allied Electronics Buy
20NH00GL Altech Specialty Fuses NH gL/gG 500vac 20A 48x20x36mm(LxWxD) from $6.20 (Sep 2016) Mouser Electronics Buy
20NH00GR-6 Altech Fuse; Pwr Dist; Super Fast Acting; 20A; Class gR; Dims 2.05x1.1x1.67" from $40.14 (Sep 2016) Allied Electronics Buy
20NH00GR-6 Altech Specialty Fuses NH gR/aR 690vac 20A 48x20x36mm(LxWxD) from $25.11 (Sep 2016) Mouser Electronics Buy
20NH1G Eaton Specialty Fuses SIZE 01 (1S)20A from $25.31 (Sep 2016) Mouser Electronics Buy
20NH1G EATON Fuse NH 20A 500V Holder Flat (Aug 2016) Sager Buy
20NHC00G EATON Fuse NH 20A 500V Holder Flat (Aug 2016) Sager Buy
20NHG000B EATON NH, 500Vac, 20A size 000 gG/gL from $3.41 (Sep 2016) Allied Electronics Buy

20ns Datasheet

Part Manufacturer Description PDF Type Ordering
20NSGG Altech Fuse 20A 415V BRITISH
ri

4 pages,
839.29 Kb

Original Buy
datasheet frame

20ns

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Device Part/SMD Number Optn Pins Pkg Flow Lead Rad 20ns/CMOS 24 DIP Mil-Temp Option None 20ns/CMOS 24 FP Mil-Temp Option None 20ns/CMOS 28 FP , FP Mil-Temp Option None 15.5ns/CMOS 28 FP Mil-Temp Option None 20ns/TTL 24 DIP Mil-Temp Option None 20ns/TTL 24 FP Mil-Temp Option None None , ://www.dscc.dla.mil/Programs/MilSpec/DocSearch.asp 20ns/TTL ... Original
datasheet

7 pages,
18.77 Kb

UT22VP10T-20WCX UT22VP10C-20UCX UT22VP10C-20WCX UT22VP10E-15PCX UT22VP10E-15UCX UT22VP10E-15WCX UT22VP10T-20PCX UT22VP10T-20UCX UT22VP10T-20UPC UT22VP10C-20PCX TEXT
datasheet frame
Abstract: JEDEC AC DDR200 DDR200 JEDEC tRCD (Row-to-Column delay ) 20ns DDR333 DDR333 , DDR266 DDR266 tRCD 20ns 3 (20ns / 7.5ns = 2.7 ) 1 (EQ 1) t RCD 22.5ns (22.5ns , tRCD DDR200 DDR200 ( tRCD = 20ns) 0ns 10ns 20ns 30ns ACT NOP READ NOP CK# CK tCK = 10ns tRCD DDR266 DDR266 ( tRCD ) = tRCD (JEDEC) = 2 × tCK = 20ns ( = 22.5ns) 0ns , DDR266 DDR266 DDR333 DDR333 DDR400 DDR400 -75 -75Z -75E -6T -5B 20ns 20ns 20ns 20ns 20ns ... Micron Technology
Original
datasheet

10 pages,
577.74 Kb

MT46V64M8 DDR400- DDR266 DDR200 DDR400 TN-46-13 micron ddr DDR333 TEXT
datasheet frame
Abstract: precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns , 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 ... Samsung Electronics
Original
datasheet

11 pages,
88.1 Kb

samsung date code k4s641632d-tc80 PC100 TEXT
datasheet frame
Abstract: , RX_DV CRS RX_CLK 20ns 52ns IDLE 2.3 DP83848 DP83848 MII 100Mb DP83849 DP83849 MII 5 , RMII 4ns IDLE tpPhyTxRMII RMII PVT 20ns 20ns 0 RMII 20ns DP83849 DP83849 4ns 0.4 11.2 RMII 10.8 PVT 1 RMII tpPhyTxRMII 3.2 RMII PVT 20ns 2 RMII , 8. Phy 100Mb 125MHz Phy 1 5 DP83849 DP83849 8ns RMII DP83848 DP83848 REF_CLK2 20ns CRS 20ns IDLE RMII RMII 7 www.national.com AN-1507 AN-1507 DP83849 DP83849 3.0 RMII AN ... National Semiconductor
Original
datasheet

13 pages,
346.6 Kb

DP83848J DP83848YB DP83848T DP83848M DP83848K DP83848C DP83848I DP83848H DP83849 100BaseF dp83848 DP83848 TEXT
datasheet frame
Abstract: 10ns 10ns 12ns 15ns 15ns 20ns 20ns PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 PDM41532 10ns 10ns 12ns 15ns 15ns 20ns 20ns 32Kx16, 3 volt 10ns PDM31516 PDM31516 10ns PDM31516 PDM31516 12ns PDM31516 PDM31516 15ns PDM31516 PDM31516 15ns PDM31516 PDM31516 20ns PDM31516 PDM31516 20ns PDM31516 PDM31516 32Kx16, 5 volt 10ns PDM41516 PDM41516 10ns PDM41516 PDM41516 12ns PDM41516 PDM41516 15ns PDM41516 PDM41516 15ns PDM41516 PDM41516 20ns PDM41516 PDM41516 20ns PDM41516 PDM41516 32KX8 32KX8, 3 volt PDM31256 PDM31256 PDM31256 PDM31256 ... IXYS
Original
datasheet

3 pages,
70.71 Kb

TMS320 RCDL56 RC336 PDM41532 PDM31516 accelerator rockwell modem AN07 AN-07 TEXT
datasheet frame
Abstract: time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns , 00h 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h ... Samsung Electronics
Original
datasheet

13 pages,
112.58 Kb

DIMM 1999 PC100 TEXT
datasheet frame
Abstract: Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time , 00h 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h ... Samsung Electronics
Original
datasheet

13 pages,
112.49 Kb

samsung dimm 128mb pc100 32mx64 K4S281632M-TC80 PC100 TEXT
datasheet frame
Abstract: 32Kx24 EDI8F2432C-15ns x32 1M 2M 256Kx8 EDIBFB257C-70ns ECH8FB259C-20ns 64Kx24 EDI8F2464C EDI8F2464C , -12na EDI8F32128C-20ns EOI8L32128C-15na Flash 32Kx16 4M 512Kx8 EDI8FB512C-20ns 256Kx16 EW8F16256C-20ns EW6F16257C-20ns EDI8F24128C-20ns EDI8F24129C-20ns 512Kx8 EDt7F8512C-100ns EEPROM ED»F3420C F3420C , EDI9F61025C-70ns 256KX32 256KX32 EDI8 F32256B-12na EDI8F32256C-20na EDI8F32257C-20ns 1Mx8 ECH8F81024C ECH8F81024C ... OCR Scan
datasheet

1 pages,
42.89 Kb

TEXT
datasheet frame
Abstract: 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate , Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS ... Samsung Electronics
Original
datasheet

28 pages,
162.84 Kb

KM416S8030BT PC100 TEXT
datasheet frame
Abstract: precharge time (=tRP) 20ns 20ns 14h 14h 28 Minimum row active to row active delay (tRRD) 20ns 20ns 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 14h 14h , (=tRP) 20ns 20ns 14h 14h 28 Minimum row active to row active delay (tRRD) 20ns 20ns 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 14h 14h 30 , (=tRP) 20ns 20ns 14h 14h 28 Minimum row active to row active delay (tRRD) 20ns ... Samsung Electronics
Original
datasheet

7 pages,
53.97 Kb

PC100 TEXT
datasheet frame
Abstract: 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate , Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS ... OCR Scan
datasheet

2 pages,
73.78 Kb

20P-M EL7104C EL7114C EL7134C EL7144C EL7202C EL7212C EL7222C EL7232C EL7242C EL7243C EL7252C EL7262C EL7272C TEXT
datasheet frame
Abstract: precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns , 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 ... Altera
Original
datasheet

18 pages,
329.49 Kb

p5ac324 EP312DC-30 EP324 half adder ic number EP312 D5AC324 D5AC312-30 EP312LI-30 EP312DC-25 D5AC32430 EP312PC-25 N5AC312 P5AC312-30 N5AC324 p5ac312 D5AC312-25 D5AC312 P5AC312-25 TEXT
datasheet frame
Abstract: time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns , 00h 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h ... OCR Scan
datasheet

8 pages,
249.61 Kb

m66212 caso 64KX1 64k*1 DRAM 256KX1 M66210P M66212P dram 64kx1 M66200AP/AFP TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
72V3614 72V3614_DS_51656.pdf DS 72V3614 72V3614_HSPICE_35451.tar HSPICE 15, 20ns PF,PQF 15, 20ns PF C,I 3.3V Bus-Matching Sample: Production: Now   15, 20ns PF C,I 3.3V Bus-Matching Sample: Production: Now   72V3644 72V3644_DS_38652.pdf DS 72V3644 72V3644_HSPICE_56020.tar HSPICE 15, 20ns PF 72V3654 72V3654_DS_83419.pdf DS 10, 15, 20ns PF C,I 3.3V Bus-Matching
/datasheets/files/idt/docs/wcd00002/wcd0022b-v1.htm
IDT 17/06/1999 30.75 Kb HTM wcd0022b-v1.htm
mosmem - mos memory cell .width in=72 .opt abstol=1u .opt acct list node .tran 20ns 2us vdd 9 0 dc 5 vs 7 0 pulse(2 0 520ns 20ns 20ns 500ns 2000ns) vw 1 0 pulse(0 2 20ns 20ns 500ns 200ns) vwb 2 0 pulse(2 0 20ns 20ns 20ns 2000ns 2000ns) m1 3 1 0 0 mod w=250u l=5u m2 4 2 0 0 mod w=250u l=5u m3 9 9 3 0 mod w=5u l=5u m4 9 9 4 0 mod w=5u l=5u m5 5 7 3 0 mod w=50u l=5u m6 6 7 4 0 mod w=50u l=5u m7 5 6 0 0 mod w=250u l=5u m8 6 5 0 0 mod w=250u l=5u
/datasheets/files/spicemodels/misc/modelos/mosmem.cir
Spice Models 18/04/2010 0.82 Kb CIR mosmem.cir
Other Available 10ns,  15ns,  20ns    PQFP_132_PQF ,  TQFP_120_PF     Temp Supp Other Available 12ns,  15ns,  20ns    PQFP_132_PQF ,  Package Temp Supp Other Available 10ns,  15ns,  20ns    Speeds Package Temp Supp Other Available 12ns,  15ns,  20ns    Speeds Package Temp Supp Other Available 10ns,  15ns,  20ns   
/datasheets/files/idt/docs/rp00014/rp01468.htm
IDT 06/10/2000 28.74 Kb HTM rp01468.htm
tphlmx=20ns + ) *$ *- * 74LS09 74LS09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *$ *- * 74LS10 74LS10 Triple tphlmx=20ns + ) *$ *- * 74LS12 74LS12 Triple 3-input Positive-Nand Gates with Open-Collector Outputs D_LS15 ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *$ * .model D_LS18 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=37ns tphlmx=55ns + ) *$
/datasheets/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/74ls.lib
Spice Models 29/07/2012 571.07 Kb LIB 74ls.lib
'BEFORE' constraint NET Din OFFSET = IN 20nS BEFORE CLK CLK UPSTREAM DEVICE FPGA This says, Data will be valid here, 20nS BEFORE the clock arrives here. In other words: "The Data to be registered in the FPGA will be available on the FPGA's input Pad 20ns BEFORE the internal data and clock delays to meet TsuFF TsuFF Tbufg 20ns Data T(clock_period) - 20ns = ext-delay Previous slide Next slide Back to first
/datasheets/files/xilinx/docs/rp0006b/rp06bbb.htm
Xilinx 29/02/2000 2.25 Kb HTM rp06bbb.htm
to CLB_R11C2 R11C2.Y : 2.0ns ( 6.7ns) Thru: Net FIFO/A2_1 to CLB_R7C4.F4 to CLB_R11C2 R11C2.Y : 2.0ns ( 6.7ns) Thru: Net FIFO/A2_1 to CLB_R7C4.G4 to CLB_R11C2 R11C2.Y : 2.0ns ( 6.7ns) Thru: Net FIFO/A2_1 to CLB_R11C3 R11C3.C1 : 2.0ns ( 6.7ns) Thru: Net FIFO/A2_1 to CLB_R11C3 R11C3.C1 : 1.7ns ( 8.4ns) Thru: Blk FIFO/A3 to CLB_R11C2 R11C2.Y : 2.0ns ( 6.7ns) Thru: Net FIFO/A2_1 to
/datasheets/files/xilinx/pci/xc4000e/ftops.xrp
Xilinx 12/10/1995 14.54 Kb XRP ftops.xrp
, 15, 20ns PF, TF C,I 3.3V - Now 72V255LA 72V255LA 8K x 18 SuperSync FIFO, 3.3V   10, 15, 20ns PF, TF C,I 3.3V - Now 72265 16K x 18 SuperSync FIFO   10, 15, 20ns PF, TF C,I 3.3V - Now 72V265LA 72V265LA 16K x 18 SuperSync FIFO, 3.3V   10, 15, 20ns PF, TF C,I 3.3V - Now 72V275 72V275 32K x 18 SuperSync FIFO, 3.3V   10, 15, 20ns PF, TF C,I 3.3V - Now 72V285 72V285 64K x 18 SuperSync FIFO, 3.3V
/datasheets/files/idt/docs/wcd00001/wcd0012e.htm
IDT 01/10/1998 104.47 Kb HTM wcd0012e.htm
to CLB_R11C3 R11C3.X : 2.0ns ( 7.3ns) Thru: Net FIFO/A3 to CLB_R14C5 R14C5.F3 to CLB_R11C3 R11C3.X : 2.0ns ( 7.3ns) Thru: Net FIFO/A3 to CLB_R14C5 R14C5.G3 to CLB_R11C3 R11C3.X : 2.0ns ( 7.3ns) Thru: Net FIFO/A3 to CLB_R13C5 R13C5.F3 FIFO/A3 to CLB_R11C3 R11C3.X : 2.0ns ( 7.3ns) Thru: Net FIFO/A3 to FIFO/A3 to CLB_R11C3 R11C3.X : 2.0ns ( 7.3ns) Thru: Net FIFO/A3 to
/datasheets/files/xilinx/pci/xc4000e/ftopa.xrp
Xilinx 12/10/1995 13.67 Kb XRP ftopa.xrp
15, 20ns PF C,I 3.3V Bus-Matching Sample: Production: Now   72V3636 72V3636_DS_20015.pdf DS 72V3636 72V3636_HSPICE_51057.tar HSPICE 15, 20ns PF 72V3646 72V3646_DS_96132.pdf DS 72V3646 72V3646_HSPICE_5409.tar HSPICE 15, 20ns PF 72V3656 72V3656_DS_80086.pdf DS 10, 15, 20ns PF C,I 3.3V Bus-Matching 10, 15, 20ns PF C,I 3.3V Bus-Matching Sample: June 1999 Production
/datasheets/files/idt/docs/wcd00002/wcd0022c-v1.htm
IDT 17/06/1999 28.93 Kb HTM wcd0022c-v1.htm
OFFSET Constraints in 2.1i OFFSET Constraints in 2.1i Global: All inputs/outputs are offset relative to a clock. For example, OFFSET = IN 20ns BEFORE clk1 indicates that all inputs will have data present at the pad at least 20ns before the triggering edge of clk1 clock. For example: NET DATA_IN OFFSET = IN 20ns BEFORE clk1 indicates that DATA_IN will have data present at the pad at least 20ns before the triggering edge of clk1 arrives at the pad.
/datasheets/files/xilinx/docs/rp0006b/rp06bc3.htm
Xilinx 29/02/2000 1.77 Kb HTM rp06bc3.htm