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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Power Cord Receptacle Part Number 2002G1 2002G1 2002G2 2002G2 2002G3 2005G1 2005G1 2005G3 2005G3 2003G1 2003G1 2003G1-LPBK 2003G1-LPBK 2002G1KIT 2002G1KIT 2002G2KIT 2002G2KIT 2002G3KIT 2005G1KIT 2005G1KIT 2005G3KIT 2005G3KIT Description Standard housing for 0.8mm panel , AWG 2002G1 2002G1 with 3 contacts crimped to 12 2002G2 2002G2 with 3 contacts crimped to 12 2002G3 with 3 ... | Original |
2 pages, |
SOOW 12-4 IF 2.0mm2 2002G1KIT 354500-1 AC C14 durability Crimping micro applicator IEC -320 C14 IEC320 Rev06 2005G1KIT 2003G1-LPBK 2002G2 IEC320-C14 1309G9 IEC320 abstract |
| Abstract: VIA Technologies Incorporated VT1616 VT1616 6-Channel AC97 Codec with S/PDIF Features · · · · · · · · · · · · · · · Description AC'97 2.2 compliant codec VIA Technologies' VT1616TM VT1616TM 20-bit ¦ audio codec conforms to the AC'97 2.2 and S/PDIF 20-bit, stereo ADC and 6-channel stereo DACs Output specifications. The VT1616 VT1616 integrates 1 Hz resolution VSR on all channels Sample Rate Converters on all channels and can be Integrated IEC958 IEC958 line driver for S/PDIF output adjust ... | Original |
40 pages, |
AC97 IEC958 SR10 SR12 SR13 SR14 SR15 via vt1616 VT16 VT1616 vt1611 VT1611A VT1616 abstract |
| Abstract: VIA Technologies Incorporated VT1612A VT1612A Stereo AC`97 Codec with S/PDIF Features Description · · · · · · · · · · · · · · · VIA Technologies' VT1612ATM VT1612ATM 18-bit ¦ audio codec conforms to the AC'97 2.2 and S/PDIF specifications. The VT1612A VT1612A integrates Sample Rate Converters and can be adjusted in 1 Hz increments. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround sound effect for stereo media. Furthermore, an integrated he ... | Original |
37 pages, |
VU meter Microphone circuit IEC958 SR10 SR12 SR13 SR14 SR15 VDR5 via VT1612A ICE1230 S/PDIF specification vt1611 vt1612 VT1611A IEC958 abstract |
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| # # Delay estimator device specific data. # $Header: dydata.acd,v 1.8 1998/03/18 22:22:29 koca Exp $ # # sfctr // Short-line factor, rel to -7 speed grade. # hvll // Half vertical longline. # vlldel // Vertical long line delay # hhll // Half Horizontal longline. # hlldel // Horizontal long line delay # rthdel // Route Thrugh delay # aclkinpen // Penalty for aclkin connection. # xhfpinpen // Highfanout pin penalty. # # :SUPPORTED=3; # ############ www.datasheetarchive.com/download/84473693-986637ZC/wcd02692.zip (dydata.acd) |
Xilinx | 13/07/1998 | 548.57 Kb | ZIP | wcd02692.zip |
| # # Delay estimator device specific data. # $Header: dydata.acd,v 1.8 1998/03/18 22:22:29 koca Exp $ # # sfctr // Short-line factor, rel to -7 speed grade. # hvll // Half vertical longline. # vlldel // Vertical long line delay # hhll // Half Horizontal longline. # hlldel // Horizontal long line delay # rthdel // Route Thrugh delay # aclkinpen // Penalty for aclkin connection. # xhfpinpen // Highfanout pin penalty. # # :SUPPORTED=3; # ############ www.datasheetarchive.com/download/10446209-986636ZC/wcd02691.z |
Xilinx | 13/07/1998 | 979.41 Kb | Z | wcd02691.z |