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Part Manufacturer Description Datasheet BUY
SN54LS266W-10 Texas Instruments LS SERIES, QUAD 2-INPUT XNOR GATE, CDFP14 visit Texas Instruments
SN74LS266N-10 Texas Instruments LS SERIES, QUAD 2-INPUT XNOR GATE, PDIP14 visit Texas Instruments
SN54LS266W-00 Texas Instruments LS SERIES, QUAD 2-INPUT XNOR GATE, CDFP14 visit Texas Instruments
SN54LS266W Texas Instruments LS SERIES, QUAD 2-INPUT XNOR GATE, CDFP14 visit Texas Instruments
SN74HC266D-00 Texas Instruments HC/UH SERIES, QUAD 2-INPUT XNOR GATE, PDSO14 visit Texas Instruments
SN74HC7266N-00 Texas Instruments HC/UH SERIES, QUAD 2-INPUT XNOR GATE, PDIP14 visit Texas Instruments

2 input XNOR GATE

Catalog Datasheet MFG & Type PDF Document Tags

IC of XNOR GATE

Abstract: 2 input XNOR GATE IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT TOLERANT I/O FEATURES: ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ , : This quadruple 2-input XNOR gate is built using advanced dual metal CMOS technology. The LVC810A has , 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE , CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE
Integrated Device Technology
Original
IC of XNOR GATE 2 input XNOR GATE ic xnor MIL-STD-883 SO14-1 SO14-2 SO14-3

IC of XNOR GATE

Abstract: 2 input XNOR GATE 3.3V CMOS QUADRUPULE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O FEATURES: 0.5 MICRON CMOS Technology , ADVANCE INFORMATION DESCRIPTION: This quadruple 2-input XNOR gate is built using advanced dual metal , 1999 1 DSC-5163/- IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O , , +25°C ambient. 2 IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O , switching in the same direction. 3 IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT
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OCR Scan

IC of XNOR GATE

Abstract: ic xnor IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC810A ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT , hot insertion This quadruple 2-input XNOR gate is built using advanced dual metal CMOS technology , 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE , IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O TEST CIRCUITS AND WAVEFORMS PROPAGATION
Integrated Device Technology
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QUAD XNOR xnor cmos XNOR GATE application LSE B3 XNOR ic
Abstract: 3.3V CMOS QUADRUPULE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - 0.5 , inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion This quadruple 2-input XNOR gate , . JANUARY 1999 1 DSC-5163/- IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O , IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE , QUADRUPLE 2-INPUT XNOR GATE, 5 VOLT TOLERANT I/O EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS -
OCR Scan

QUAD XNOR

Abstract: MC74LCX810 Product Preview Low-Voltage CMOS Quad 2-Input XNOR Gate MC74LCX810 With 5V­Tolerant Inputs The MC74LCX810 is a high performance, quad 2­input XNOR gate operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL , Exceeds 500mA · ESD Performance: Human Body Model >2000V; Machine Model >200V LOW­VOLTAGE CMOS QUAD 2­INPUT XNOR GATE D SUFFIX PLASTIC SOIC CASE 751A­03 14 1 M SUFFIX PLASTIC SOIC EIAJ CASE 965­01
ON Semiconductor
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MC74LCX810/D

xnor gate motorola

Abstract: QUAD XNOR 2-Input XNOR Gate With 5V-Tolerant Inputs The MC74LCX810 is a high performance, quad 2­input XNOR gate operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise , . Current drive capability is 24mA at the outputs. · · · · · · LOW­VOLTAGE CMOS QUAD 2­INPUT XNOR GATE Designed for 2.7 to 3.6V VCC Operation 5V Tolerant Inputs - Interface Capability With 5V
Motorola
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BR1339 xnor gate motorola xnor ttl

2 input XNOR GATE

Abstract: IC of XNOR GATE IDT74LVC32A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC810A ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT TOLERANT I/O , This quadruple 2-input XNOR gate is built using advanced dual metal CMOS technology. The LVC810A has , Small Outline Package (SO14-3) 810A Quadruple 2-Input XNOR Gate, ±24mA 74 ­ 40°C to +85°C , ambient. 2 IDT74LVC32A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL
Integrated Device Technology
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Abstract: 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT TOLERANT I/O FEATURES: 0.5 MICRON CMOS , ADVANCE INFORMATION D E S C R IP TIO N : This quadruple 2-input XNOR gate is built using advanced dual , QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIALTEMPERATURE RANGE T E S T C O N D IT IO N S , 3.3V, + 2 5 ° C ambient. 2 IDT74LVC81OA 3.3V CMOS QUADRUPLE 2-INPUTXNOR GATE WITH 5V I/O , d ru p le 2 -In p u t X N O R Gate, ± 2 4 m A 74 - 4 0 ° C to + 8 5 ° C CORPORATE -
OCR Scan
L-STD-883

xnor ttl

Abstract: xnor gate ttl ; Machine Model >200V M C 74LC X 810 LCX LOW-VOLTAGE CMOS QUAD 2-INPUT XNOR GATE Pinout: 1 4 -Lea , MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview L o w -V o lta g e CMOS Quad 2 -In p u t XN O R G a te With 5V-Tolerant Inputs The MC74LCX810 is a high performance, quad 2 -in put XNOR gate operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance
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OCR Scan
xnor gate ttl B303
Abstract: 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT TOLERANT I/O D E S C R IP TIO N : FEATURES , ADVANCE INFORMATION This quadruple 2-input XNOR gate is built using advanced dual metal CMOS , 3.3V CMOS QU ADRUPLE 2-INPUT POSITIVE-OR G ATE EXTENDED COMMERCIALTEMPERATURE RANGE A B S O L U T , 3.6V Symbol VlH 2 â'" â'" Param eter Input HIGH Voltage Level V cc = 2.3V to 2.7V , â'" -0 .7 -1 .2 V 100 â'" mV 10 fjA 500 fjA Vh Input Hysteresis -
OCR Scan

A115-A

Abstract: C101 NO. 2-input AND gate 3 2-input NOR gate with both inputs inverted 3 2-input NAND gate with inverted input 4, 5 2-input OR gate with inverted input 4, 5 2-input AND gate with both inputs inverted 6 2-input NOR gate 6 2-input XNOR gate 7 Inverter 8 , . 2-Input XNOR Gate Figure 8. Inverter VCC B 6 2 Y 1 5 3 B 4 Y , 6 5 3 Y 1 2 C Y C 4 B C Y Figure 3. 2-Input AND Gate 2-Input NOR
Texas Instruments
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SN74AUP1T57 A115-A C101 SCES611 A114-B
Abstract: TABLE LOGIC FUNCTION 2-input AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate Inverter Noninverted buffer FIGURE NO. 5 5 6, 7 6, 7 8 8 9 10 11 Static-Power , 2005 www.ti.com VCC B Y C B 1 2 3 6 5 4 C Y Figure 9. 86+04: 2-Input XNOR Gate , Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 Texas Instruments
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SCES611B SC-70 SN74AUP1T58 SN74AUP1T97 SN74AUP1T98

JEDEC SC-70

Abstract: TABLE LOGIC FUNCTION 2-input AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate Inverter Noninverted buffer FIGURE NO. 5 5 6, 7 6, 7 8 8 9 10 11 Static-Power , 2005 www.ti.com VCC B Y C B 1 2 3 6 5 4 C Y Figure 9. 86+04: 2-Input XNOR Gate , Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6
Texas Instruments
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JEDEC SC-70
Abstract: , â'¢ = Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 8 2-input XNOR gate 9 Inverter 10 Noninverted buffer Static-Power Consumption (µA) 8 2-input , B 1 6 2 5 3 Y C 4 C Y Figure 9. 86+04: 2-Input XNOR Gate VCC A 1 Texas Instruments
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SCES611C
Abstract: , â'¢ = Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 8 2-input NOR gate 8 2-input XNOR gate 10 Noninverted buffer Static-Power Consumption (µA) 9 , 2 5 3 Y C 4 C Y Figure 9. 86+04: 2-Input XNOR Gate VCC A 1 A 6 2 Texas Instruments
Original
Abstract: AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate , Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With Inverted Input VCC A C 1 A C 2 Y A 3 6 5 4 Y C Y Figure 7. 14+00/14+32: 2-Input NAND Gate With Inverted Texas Instruments
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SCES611A

gate logic

Abstract: AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate , . 86+04: 2-Input XNOR Gate VCC A Y A 1 2 3 6 5 4 Y GND Figure 10. 04/14: Inverter VCC , . 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With Inverted
Texas Instruments
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gate logic
Abstract: AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate , . 86+04: 2-Input XNOR Gate VCC A Y A 1 2 3 6 5 4 Y GND Figure 10. 04/14: Inverter VCC , . 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With Inverted Texas Instruments
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Abstract: AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR gate , . 86+04: 2-Input XNOR Gate VCC A Y A 1 2 3 6 5 4 Y GND Figure 10. 04/14: Inverter VCC , . 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With Inverted Texas Instruments
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A115-A

Abstract: C101 SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 2-input NOR gate 8 2-input XNOR gate 9 , Y 5 3 4 Y GND Figure 9. 86+04: 2-Input XNOR Gate Figure 10. 04/14: Inverter , 3 Y 1 2 C Y C 4 B C Y Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR
Texas Instruments
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AUP1T98/97/58
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