NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| SN54S135W | Texas Instruments | IC S SERIES, QUAD 2-INPUT XOR/XNOR GATE, CDFP16, Gate | 
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| SN54S135W-00 | Texas Instruments | IC S SERIES, QUAD 2-INPUT XOR/XNOR GATE, CDFP16, Gate |
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| SN74S135J | Texas Instruments | IC S SERIES, QUAD 2-INPUT XOR/XNOR GATE, CDIP16, Gate |
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| SN74S135FN | Texas Instruments | IC S SERIES, QUAD 2-INPUT XOR/XNOR GATE, PQCC20, Gate |
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| SN74S135N-10 | Texas Instruments | IC S SERIES, QUAD 2-INPUT XOR/XNOR GATE, PDIP16, Gate |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: IDT74LVC810A IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC810A IDT74LVC810A ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT , hot insertion This quadruple 2-input XNOR gate is built using advanced dual metal CMOS technology. , 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE , IDT74LVC810A IDT74LVC810A 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5V I/O TEST CIRCUITS AND WAVEFORMS PROPAGATION ... | Original |
5 pages, |
LVC810A LSE B3 XNOR ic XNOR GATE application IDT74LVC810A ic xnor QUAD XNOR 2 input XNOR GATE xnor cmos IC of XNOR GATE IDT74LVC810A abstract |
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| Abstract: IDT74LVC32A IDT74LVC32A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74LVC810A IDT74LVC810A ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT XNOR GATE WITH 5 VOLT TOLERANT I/O , insertion This quadruple 2-input XNOR gate is built using advanced dual metal CMOS technology. The , Quadruple 2-Input XNOR Gate, ±24mA 74 40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way , 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE ... | Original |
5 pages, |
XNOR ic LVC810A IDT74LVC32A QUAD XNOR IC of XNOR GATE 2 input XNOR GATE IDT74LVC32A abstract |
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| Abstract: 2-Input XNOR Gate With 5V-Tolerant Inputs The MC74LCX810 MC74LCX810 is a high performance, quad 2input XNOR gate , is 24mA at the outputs. · · · · · · LOWVOLTAGE CMOS QUAD 2INPUT XNOR GATE Designed , loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI , O3 13 SD SUFFIX PLASTIC SSOP CASE 940A03 1 A2 VCC 14 8 14 1 2 3 , B2 A3 B3 1 3 2 6 FUNCTION TABLE O1 13 11 12 8 Inputs O3 Bn On L L ... | Original |
4 pages, |
2 input XNOR GATE MC74LCX810 BR1339 QUAD XNOR xnor gate motorola datasheet abstract |
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| Abstract: Product Preview Low-Voltage CMOS Quad 2-Input XNOR Gate MC74LCX810 MC74LCX810 With 5VTolerant Inputs The MC74LCX810 MC74LCX810 is a high performance, quad 2input XNOR gate operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL , 2INPUT XNOR GATE D SUFFIX PLASTIC SOIC CASE 751A03 14 1 M SUFFIX PLASTIC SOIC EIAJ CASE , O2 A3 B3 O3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A0 ... | Original |
4 pages, |
MC74LCX810 QUAD XNOR MC74LCX810 abstract |
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| Abstract: NO. 2-input AND gate 3 2-input NOR gate with both inputs inverted 3 2-input NAND gate with inverted input 4, 5 2-input OR gate with inverted input 4, 5 2-input AND gate with both inputs inverted 6 2-input NOR gate 6 2-input XNOR gate 7 Inverter 8 , GND Figure 7. 2-Input XNOR Gate Figure 8. Inverter VCC B 6 2 Y 1 5 3 , 6 5 3 Y 1 2 C Y C 4 B C Y Figure 3. 2-Input AND Gate 2-Input NOR ... | Original |
14 pages, |
SN74AUP1T57 C101 A115-A SCES611 SN74AUP1T57 abstract |
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| Abstract: SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 2-input NOR gate 8 2-input XNOR gate 9 , Y 5 3 4 Y GND Figure 9. 86+04: 2-Input XNOR Gate Figure 10. 04/14: Inverter , 3 Y 1 2 C Y C 4 B C Y Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR ... | Original |
15 pages, |
SN74AUP1T57 C101 A115-A SCES611A SN74AUP1T57 abstract |
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| Abstract: Pb-free). FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 8 2-input NOR gate 8 2-input XNOR gate 9 Inverter 10 Noninverted buffer 11 Static-Power , 5 3 Y 4 C Y Figure 9. 86+04: 2-Input XNOR Gate VCC A 1 A 6 2 Y 5 ... | Original |
26 pages, |
SN74AUP1T98 SN74AUP1T97 SN74AUP1T58 SN74AUP1T57 C101 SCES611G SN74AUP1T57 abstract |
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| Abstract: 2-input AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR , Figure 9. 86+04: 2-Input XNOR Gate VCC A Y A 1 2 3 6 5 4 Y GND Figure 10. 04/14 , Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With ... | Original |
26 pages, |
SN74AUP1T57 SCES611G SN74AUP1T57 abstract |
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| Abstract: 2-input AND gate 2-input NOR gate with both inputs inverted 2-input NAND gate with inverted input 2-input OR gate with inverted input 2-input AND gate with both inputs inverted 2-input NOR gate 2-input XNOR , Figure 9. 86+04: 2-Input XNOR Gate VCC A Y A 1 2 3 6 5 4 Y GND Figure 10. 04/14 , Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR Gate With Both Inputs Inverted VCC B C B C Y B Y 1 2 3 6 5 4 Y C Figure 6. 14+00/14+32: 2-Input NAND Gate With Inverted B Input 2-Input OR Gate With ... | Original |
26 pages, |
SN74AUP1T57 SCES611G SN74AUP1T57 abstract |
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| Abstract: SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND gate 5 2-input NOR gate with both inputs inverted 5 2-input NAND gate with inverted input 6, 7 2-input OR gate with inverted input 6, 7 2-input AND gate with both inputs inverted 8 2-input NOR gate 8 2-input XNOR gate , : 2-Input XNOR Gate VCC A 1 A 6 2 Y 5 3 4 Y GND Figure 10. 04/14 , 3 Y C 6 2 B 1 4 C Y Figure 5. 08/14+2: 2-Input AND Gate 2-Input NOR ... | Original |
19 pages, |
SN74AUP1T97 SN74AUP1T58 SN74AUP1T57 C101 A115-A SCES611E SN74AUP1T57 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| *4077 MCE Nodes: A,B,Y *MCE mixed-mode 2-input XNOR gate pkg:DIP14 DIP14 DIP14 DIP14 (A:1,2,3)(B:5,6,4)(C:8,9,10)(D:12,13,11) .SUBCKT X4077 X4077 X4077 X4077 3 4 5 BNLVs1 1 0 V=~(V(3) ! v(4) R1 1 5 1 C1 5 0 .004uF IC=0V .ENDS X4077 X4077 X4077 X4077 www.datasheetarchive.com/files/spicemodels/misc/modelos/2inxnor.sub |
Spice Models | 21/02/2008 | 0.2 Kb | SUB | 2inxnor.sub |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/53678638-996410ZC/vlogisun.tar |
Xilinx | 20/01/1997 | 3560 Kb | TAR | vlogisun.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/53678638-996410ZC/vlogisun.tar |
Xilinx | 20/01/1997 | 3560 Kb | TAR | vlogisun.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/53678638-996410ZC/vlogisun.tar |
Xilinx | 20/01/1997 | 3560 Kb | TAR | vlogisun.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/53678638-996410ZC/vlogisun.tar |
Xilinx | 20/01/1997 | 3560 Kb | TAR | vlogisun.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/40566254-996407ZC/vlogihp7.tar |
Xilinx | 20/01/1997 | 3144 Kb | TAR | vlogihp7.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/40566254-996407ZC/vlogihp7.tar |
Xilinx | 20/01/1997 | 3144 Kb | TAR | vlogihp7.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/40566254-996407ZC/vlogihp7.tar |
Xilinx | 20/01/1997 | 3144 Kb | TAR | vlogihp7.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify begin $sy_xilinx_sym ( "); end `endif endmodule `endcelldefine www.datasheetarchive.com/download/40566254-996407ZC/vlogihp7.tar |
Xilinx | 20/01/1997 | 3144 Kb | TAR | vlogihp7.tar |
| . * */ /* LIBRARY : Xilinx Unified Library - Rev 2.0 - Mar 1994. FUNCTION : 2-INPUT XNOR GATE Landen DATE GENERATED : 1st Mar 1994 VERITOOL COMPATIBILITY : Verilog2.0, Veritime1.4 */ `delay_mode_path `timescale 1 ns / 100 ps `celldefine module xnor2 (o, i0, i1); parameter size = 1; output o; input i0, i1; `protect xnor XNOR1 (o, i0, i1); specify www.datasheetarchive.com/download/12169451-958084ZC/ver9khp.tar |
Xilinx | 05/09/1996 | 1048 Kb | TAR | ver9khp.tar |