MSE908AZ32A 1L18M 908AZ32A SE17-MSCAN ID28-ID0

Mask Set Errata MSE908AZ32A_1L18M Rev. 0, 8/2004 Mask Set Errata for 908AZ32A, Mask 1L18M Introduction This mask set errata

Freescale Semiconductor Mask Set Errata MSE908AZ32A MSE908AZ32A_1L18M 1L18M Rev. 0, 8/2004 Mask Set Errata for 908AZ32A 908AZ32A, Mask 1L18M 1L18M Introduction This mask set errata applies to this 908AZ32A 908AZ32A MCU mask set: · 1L18M 1L18M MCU Device Mask Set Identification The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 1L18M 1L18M. All standard devices are marked with a mask set number and a date code. MCU Device Date Codes Device markings indicate the week of manufacture and the mask set used. The date is coded as four numerical digits where the first two digits indicate the year and the last two digits indicate the work week. For instance, the date code "0201" indicates the first week of the year 2002. © Freescale Semiconductor, Inc., 2004. All rights reserved. MCU Device Part Number Prefixes Some MCU samples and devices are marked with an SC, PC, or XC prefix. An SC prefix denotes special/custom device. A PC prefix indicates a prototype device which has undergone basic testing only. An XC prefix denotes that the device is tested but is not fully characterized or qualified over the full range of normal manufacturing process variations. After full characterization and qualification, devices will be marked with the MC or SC prefix. MSCAN Extended ID Rejected if STUFF Bit Between ID16 and ID15 SE17-MSCAN SE17-MSCAN For 32-bit and 16-bit identifier acceptance modes, an extended ID CAN frame with a stuff bit between ID16 and ID15 can be erroneously rejected, depending on IDAR0, IDAR1, and IDMR1. Extended IDs (ID28-ID0 ID28-ID0) which generate a stuff bit between ID16 and ID15: Table 4. IDAR0 IDAR1 IDAR2 IDAR3 * *1111x xxxxxxxx xxxxxxxx where x = 0 or 1 (don't care) * = pattern for ID28 to ID18 (see following). Affected extended IDs (ID28 - ID18) patterns: a) xxxxxxxxx01 exceptions: 00000000001 01111100001 xxxx1000001 except 11111000001 b) xxxxx100000 exception: 01111100000 c) xxxx0111111 exception: 00000111111 d) x0111110000 e) 10000000000 f) 11111111111 g) 10000011111 When an affected ID is received, an incorrect value is compared to the 2nd byte of the filter (IDAR1 and IDAR5, plus IDAR3 and IDAR7 in 16-bit mode). This incorrect value is the shift register contents before ID15 is shifted in (i.e. right shifted by 1). Mask Set Errata for 908AZ32A 908AZ32A, Mask 1L18M 1L18M 2 Freescale Semiconductor Workaround If the problematic IDs cannot be avoided, the workaround is to mask certain bits with IDMR1 (and IDMR5, plus IDMR3 and IDMR7 in 16-bit mode). Example 1: to receive the message IDs xxxx xxxx x011 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 111x xxx1, i.e. ID20,19,18,15 must be masked. Example 2: to receive the message IDs xxxx 0111 1111 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 1xxx xxx1, i.e. ID20 and ID15 must be masked. In general, using IDMR1 etc. 1111 xxx1, i.e. masking ID20,19,18,SRR,15, hides the problem. Mask Set Errata for 908AZ32A 908AZ32A, Mask 1L18M 1L18M Freescale Semiconductor 3 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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