NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: combinatorial paths limited to one CLB stage, the longest delay path is the carry propagation of the 13 bit , adder network where the lower input to each adder (all are parallel) is scaled down by a power of 2. Word growth continues through the adder stages. While many applications required only 8 bit output precision, a double precision data path is shown. An adder with 10 output bits indicated is essentially a 9 bit parallel adder with the carry bit passed along, and so on down the chain. Note that the ... | Original |
2 pages, |
half adder applications of half adder 13-bit adder FIR FILTER implementation xilinx HSP43881 4000E-3 HSP43881 abstract |
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| Abstract: a Stereo, Single-Supply 18-Bit Integrated DAC AD1859 AD1859 FEATURES Complete, Low Cost Stereo DAC System in a Single Die Package Variable Rate Oversampling Interpolation Filter Multibit Modulator with Triangular PDF Dither Discrete and Continuous Time Analog Reconstruction Filters Extremely Low Out-of-Band Energy 64 Step (1 dB/Step) Analog Attenuator with Mute Buffered Outputs with 2 k Output Load Drive Rejects Sample Clock Jitter 94 dB Dynamic Range, Â88 dB THD+N Performance Opt ... | Original |
16 pages, |
ZR38000 AD1859 AD1859JR AD1859JRS C-CUBE SSM2017 SSM2142P zoran burst AC-3 CL480 c-cube AES17-1991 CL480 CL480 MPEG Video Decoder C-CUBE MICROSYSTEMS CL480 SSM2142 AD1859 abstract |
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| Abstract: create an 8.5 number. Thus, you must use a 13-bit adder rather than an 11-bit adder to add the two , any carry out of the adder should be ignored. Figure 3 shows how to add two 2-bit two's complement , are the carry out of the 3-bit adder, which must be ignored. Other than the sign extension and ignoring the carry-out of the MSB of the adder, addition for two's complement numbers is identical to , binary adder. Figure 5 shows how to add 00100101.101 (37.625) to 001101110011.001 (883.125). Figure ... | Original |
16 pages, |
4bit by 3bit binary multiplier 13-bit adder 4 bit gray to binary converter circuit datasheet abstract |
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| Abstract: generator. The output of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide , of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to the , complex (I, Q) signed integer (2Ã-13 bits). In total, they output eight complex 13-bit signed integers (8Ã-2Ã-13-bits) to the rotator when non-coherent memory is enabled; otherwise they output four complex 13-bit , consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to the interpolator. 3.2.5 ... | Original |
12 pages, |
TMS320TCI6488 ovsf gold code generator GOLD CODE 4213b TCI6488 TMS320TCI6488 abstract |
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| Abstract: INPUT BIAS ADDER 1K x 13-bit LUT* LIMIT 13 13 ROUND 13 INPUT BIAS ADDER , * 13 13 1K x 13-bit LUT* 13 OUTPUT BIAS ADDER OUTPUT BIAS ADDER 13 13 13 , 13-bit LUT* 13 OUTPUT BIAS ADDER 13 13 YOUT12-0 YOUT12-0 DIN12-0 DIN12-0 CF12-0 CF12-0 LD PAUSE 13 , * LIMIT 13 INPUT BIAS ADDER 20 ROUND 13 13 SELECT 13 1K x 13-bit LUT , 13-bit LUT* 13 13 1K x 13-bit LUT* 13 OUTPUT BIAS ADDER OUTPUT BIAS ADDER 13 ... | Original |
20 pages, |
LF3312 CIN12-0 Ic 741 as I to v converter LF2242 LF3304 LF3310 LF3320 LF3330 LF3347 lf3370 LF7710 7400 functional diagram LMU08 block diagram for barrel shifter datasheet abstract |
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| Abstract: · 13-bit voice codec with dual ADC channel and both narrow and wideband sampling · Dual serial , processor applications Key Features · 13-bit stereo recording from analog input source such as FM , Voice Codec · 13-bit linear Tx and Rx mode · 8 kHz and 16 kHz supported · Additional ADC for stereo , supported) · Earpiece amplifier · Prepared for stereo loudspeakers · Mono adder for playing stereo source ... | Original |
2 pages, |
universal battery charger for mobile rgb sensor spi bus MC13783 rgb to usb circuit datasheet CEA-936A CEA-936-A MC13783 abstract |
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| Abstract: 13 20 ROUND 1K x 13-bit LUT* 13 35 SELECT 13 13 INPUT BIAS ADDER 1K x 13-bit LUT* LIMIT 13 13 ROUND 13 INPUT BIAS ADDER LIMIT 13 ROUND , 13-bit LUT* MUX SELECT 13 LIMIT INPUT BIAS ADDER ROUND 13 SELECT 13 , 13-bit LUT* 13 SELECT 20 LIMIT 13 13 INPUT BIAS ADDER 1K x 13-bit LUT , COLORSPACE CONVERTER DEMUX SELECT 13 1K x 13-bit LUT* 13 OUTPUT BIAS ADDER 13 13 ... | Original |
20 pages, |
9027 LF3304 LF3310 LF3311 LF3312 LF3320 LF3321 LF3330 LF3347 LF3370 LF7710 LT4420 picture-in-picture motion interpolation LMU217 digital video mixer - tbc datasheet abstract |
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| Abstract: INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K , 13 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER 13 2 1K x 13-bit , Capability u 13-bit Data Path, Colorspace Converter Coefficients and Key Channel Scaling Coefficients u , DE-MULTIPLEXER SECTION INPUT BIAS ADDERS 1K x 13-Bit COLORSPACE CONVERTER/ KEY SCALER 55-TAP 55-TAP , removing or adding a user-defined bias into the video signal. In addition, three programmable 1K x 13-bit ... | Original |
22 pages, |
Z12.0 The13-bit lf3370 LF3370 LF3370 abstract |
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| Abstract: INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit LUT* 13 13 13 , INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit , Capability u 13-bit Data Path, Colorspace Converter Coefficients and Key Channel Scaling Coefficients u , DE-MULTIPLEXER SECTION INPUT BIAS ADDERS 1K x 13-Bit COLORSPACE CONVERTER/ KEY SCALER 55-TAP 55-TAP , removing or adding a user-defined bias into the video signal. In addition, three programmable 1K x 13-bit ... | Original |
20 pages, |
LF3370 CF120 LF3370 abstract |
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| Abstract: BIAS ADDER 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit LUT* 13 13 13 13 , Capability u 13-bit Data Path, Colorspace Converter Coefficients and Key Channel Scaling Coefficients u , DE-MULTIPLEXER SECTION INPUT BIAS ADDERS 1K x 13-Bit COLORSPACE CONVERTER/ KEY SCALER 55-TAP 55-TAP , removing or adding a user-defined bias into the video signal. In addition, three programmable 1K x 13-bit , 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit LUT* 13 13 13 13 35 ... | Original |
24 pages, |
half adder 74 FIR Filter LUT control device lf3370 LF3370 LF3370 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Release 6.1i - xst G Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. -> TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT = * Synthesis Options Summary www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (myuart_16550_wrapper_xst.srp) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| Release 6.2i - xst G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. -> TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT = * Synthesis Options Summary www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (myuart_16550_wrapper_xst.srp) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/16741115-960346ZC/synrefs.zip (SYNREFA.DOC) |
Xilinx | 05/09/1996 | 636.77 Kb | ZIP | synrefs.zip |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/59429109-960341ZC/synrefa.doc |
Xilinx | 18/12/1995 | 1288.5 Kb | DOC | synrefa.doc |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/14498186-960383ZC/synrefs.zip (SYNREFA.DOC) |
Xilinx | 05/09/1996 | 636.77 Kb | ZIP | synrefs.zip |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/84187442-960378ZC/synrefa.doc |
Xilinx | 18/12/1995 | 1288.5 Kb | DOC | synrefa.doc |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/24952030-996551ZC/synrefs.zip (SYNREFA.DOC) |
Xilinx | 09/04/1997 | 636.77 Kb | ZIP | synrefs.zip |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/9667701-987272ZC/wcd02f50.zip (SYNREFA.DOC) |
Xilinx | 13/07/1998 | 636.77 Kb | ZIP | wcd02f50.zip |
| . For example, if you have an application where all you need is a 13-bit adder, it's something of a waste to build a 16-bit adder. #1; Figure A-39. The Basic Building Block of Any Ripple Adder - the 1-bit Full Adder The equivalent VHDL code for building block looks like: entity FULL_ADD is BEHAV; Figure A-40. VHDL for A 1-bit Full Adder In the following example seek out "WIDTH" and how it (I);#11; end generate; NCOUT www.datasheetarchive.com/download/55968320-987461ZC/wcd03085.zip (SYNREFA.DOC) |
Xilinx | 12/02/1999 | 636.77 Kb | ZIP | wcd03085.zip |
| / in Library plb_ipif_v1_00_b. Entity (Architecture / in Library plb_ipif_v1_00_b. Entity (Architecture www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (inst_plb_sdram_wrapper_xst.srp) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |