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Part Manufacturer Description Datasheet BUY
CS5351-DZZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 108dB 192kHz Multi-Bit ADC visit Digikey
CDB5340 Cirrus Logic Evaluation, Design Tools Eval Bd 101dB 192kHz Mult-Bit Aud ADC visit Digikey
CDB5361 Cirrus Logic Evaluation, Design Tools Eval Bd 24-Bit 114dB 192kHz Mult-Bit ADC visit Digikey
CDB5351 Cirrus Logic Evaluation, Design Tools Eval Bd 24-Bit 108dB 192kHz Mult-Bit ADC visit Digikey
CS5351-KZZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 108dB 192kHz Multi-Bit ADC visit Digikey
CS5361-KSZR Cirrus Logic Converters - Analog to Digital (ADC) IC 24Bit 114dB 192kHz Multi-Bit ADC visit Digikey

13-bit+adder

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 13 1 2 13 13 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit LUT* 13 13 13 , ADDER FLAG GENERATOR 2 MUX 13 13 13 HF1 HF0 ZOUT12-0 YOUT12-0 OUTPUT BIAS ADDER 13 XOUT12-0 OUTPUT BIAS ADDER DEVICES INCORPORATED DIN12-0 CIN12 , 3-5 DEMUX INPUT 13 1 2 13 13 13 13 INBIAS1-0 INPUT BIAS ADDER Logic Devices
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LF3370 CF120 A12-0 B12-0 C12-0 D12-0 55-TAP
Abstract: of 2. 3 Generic Correlation Co-Processors The GCCP data path contains: · Correlator and adder , Branches. 8 PN Multi/Adder Trees 32x2x8 2 x 13 | 2 x 13 16 2 x 16 16 Output Queues , adder trees. 3.1.3 Code Generator The code generator in PD mode is different from the common , code specification. Data going from the code generator to the adder trees is 32×2 bits wide. 3.1.4 Adder Tree/Correlator The correlation engine consists of eight parallel independent correlators. During Texas Instruments
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TMS320TCI6488 TCI6488 S1C0 4213b GCCP GOLD CODE gold code generator
Abstract: 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x , 13 OE WOUT12-0 13 1 13 13 OUTBIAS1-0 2 OUTPUT BIAS ADDER FLAG GENERATOR 2 MUX 13 13 13 HF1 HF0 ZOUT12-0 YOUT12-0 OUTPUT BIAS ADDER 13 XOUT12-0 OUTPUT BIAS ADDER FIGURE 1. SELECT HBLANK DEVICES INCORPORATED LF3370 , 13 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 Logic Devices
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ZOUT10 ZOUT11 ZOUT12 YOUT10 WOUT12 WOUT11
Abstract: 13 13 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER , ADDER FLAG GENERATOR 2 MUX 13 13 13 HF1 HF0 ZOUT12-0 YOUT12-0 OUTPUT BIAS ADDER 13 XOUT12-0 OUTPUT BIAS ADDER FIGURE 1. SELECT HBLANK DEVICES , 1 2 13 13 13 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K x 13-bit LUT* 1K x 13-bit LUT* 13 13 13 13 Logic Devices
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12 demux FIR Filter LUT control device half adder 74 WOUT10 XOUT12 XOUT11 XOUT10 YOUT12 YOUT11
Abstract: WOUT12-0 ROUND INPUT BIAS ADDER 1K x 13-bit LUT* SELECT AIN12-0 1K x 13-bit LUT* OUTPUT BIAS ADDER 13 LIMIT LIMIT 13 13 13 20 13 13 20 13 13 13 XOUT12-0 ROUND SELECT ROUND INPUT BIAS ADDER 1K x 13-bit LUT* 1K x 13-bit LUT* SELECT BIN12-0 HALF-BAND FILTER/ INTERPOLATOR OUTPUT BIAS ADDER INPUT COLORSPACE CONVERTER 13 LIMIT LIMIT OUTPUT MUX DEMUX 13 3 13 13 20 20 13 13 13 13 13 ROUND ROUND INPUT BIAS ADDER Logic Devices
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0798d CF700 RSL-10 LF3370QC12 3370-F
Abstract: -0 INPUT BIAS ADDER INPUT BIAS ADDER INPUT BIAS ADDER 2 1K x 13-bit LUT* 1K x 13 , 1 13 13 OUTBIAS1-0 2 OUTPUT BIAS ADDER FLAG GENERATOR 2 MUX 13 13 13 HF1 HF0 ZOUT12-0 YOUT12-0 OUTPUT BIAS ADDER 13 XOUT12-0 OUTPUT BIAS ADDER DEVICES INCORPORATED DIN12-0 CIN12-0 BIN12-0 AIN12-0 13 INPUT LOOK-UP-TABLE , 13 INBIAS1-0 INPUT BIAS ADDER INPUT BIAS ADDER 13 2 1K x 13-bit LUT* 1K x Logic Devices
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001481 The13-bit Z12.0 BIN10 BIN11 BIN12 AIN10 AIN11 AIN12
Abstract: INPUT BIAS ADDER 1K x 13-bit LUT* LIMIT 13 13 ROUND 13 INPUT BIAS ADDER , * 13 13 1K x 13-bit LUT* 13 OUTPUT BIAS ADDER OUTPUT BIAS ADDER 13 13 13 , * MUX SELECT 13 LIMIT INPUT BIAS ADDER ROUND 13 HALF-BAND FILTER/ INTERPOLATOR , 13-bit LUT* 13 OUTPUT BIAS ADDER 13 13 YOUT12-0 DIN12-0 CF12-0 LD PAUSE , * LIMIT 13 INPUT BIAS ADDER 20 ROUND 13 13 SELECT 13 1K x 13-bit LUT Logic Devices
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LF3310 LF3320 LF3330 LF3347 LF3304 LF3312 power supply 5 Volt LF9502 77346 LT4420 LMU08 LF7710
Abstract: 13 20 ROUND 1K x 13-bit LUT* 13 35 SELECT 13 13 INPUT BIAS ADDER 1K x 13-bit LUT* LIMIT 13 13 ROUND 13 INPUT BIAS ADDER LIMIT 13 ROUND , -bit LUT* 13 OUTPUT BIAS ADDER OUTPUT BIAS ADDER 13 13 13 13 INPUT 13 20 , -bit LUT* MUX SELECT 13 LIMIT INPUT BIAS ADDER ROUND 13 SELECT 13 XOUT12 , BIAS ADDER 13 13 YOUT12-0 DIN12-0 CF12-0 LD PAUSE 13 3-5 13 13 1 2 Logic Devices
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LF3311 LF3321 LMU217 digital video mixer - tbc ACCM 5 pin picture-in-picture motion interpolation 2002S
Abstract: 0° increments. The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via , Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control sec tion serially loads the frequency control word into the fre quency register. The Phase Accumulator and Phase Offset Adder compute the phase , Accumulator Section The phase accumulator and phase offset adder compute the phase of the sine wave from the , input register by asserting LOAD, which zeroes the feedback to the phase accumulator. The phase adder -
OCR Scan
HSP45102PC-40 HSP45102
Abstract: F o r m a t s and INPUT BIAS ADDER/OUTPUT BIAS ADDER 0 ro ro ro ro 0 (S ig , must be loaded and selected for each channel. If use of the Input Bias Adder is desired, at least one Input Bias Adder Register must be loaded and selected before use. If use of the Output Bias Adder is desired, at least one Output Bias Adder Register must be loaded and selected before use. If , initialization. R ESET w ill not reset the counter. Input/Output Bias Adder The program m able Input/O utput -
OCR Scan
4/08/99-L
Abstract: be loaded and selected for each channel. If use of the Input Bias Adder is desired, at least one Input Bias Adder Register must be loaded and selected before use. If use of the Output Bias Adder is desired, at least one Output Bias Adder Register must be loaded and selected before use. If use of the , will not reset the counter. Input/Output Bias Adder LOW, blanking level words are continu ally , 3. By using INBIASl-0, the user may select one of four pro grammed Input Bias Adder values (see -
OCR Scan
Abstract: . Applications · Direct Digital Synthesis The 13-bit output of the Phase Offset Adder is mapped to the sine , ACCUMULATOR 13 PHASE OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M , CLK. overline designates active low signals. 5-48 HSP45102 PHASE OFFSET ADDER R.P0-1 P0 , Phase Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control section serially loads the frequency control word into the frequency register. The Phase Accumulator and Phase Offset Adder Harris Semiconductor
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HSP45102PI-33 HSP45102SI-40 HI5731 HSP45102PC-33 HSP45102SC-33 HSP45102SC-40 NCO12 ISO9000 1-800-4-HARRIS
Abstract: 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM. The , CONTROL SECTION 32 32 PHASE ACCUMULATOR 13 PHASE OFFSET ADDER 13 SINE ROM 12 , CLK. Overline designates active low signals. 2 HSP45102 PHASE OFFSET ADDER A D D E R , Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control , Phase Offset Adder compute the phase angle using the frequency control word and the two phase Intersil
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HSP45102SC-33Z HSP45102SC-40Z HSP45102SI-3396 FN2810
Abstract: 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM. The , OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M 1 CAUTION: These , CLK. Overline designates active low signals. 2 HSP45102 PHASE OFFSET ADDER A D D E R , Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control , Phase Offset Adder compute the phase angle using the frequency control word and the two phase Intersil
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HSP45102SI-33
Abstract: 90o increments. The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via , SCLK FREQUENCY CONTROL SECTION LOAD TXFR ENPHAC SEL_L/M 32 32 PHASE ACCUMULATOR 13 PHASE OFFSET ADDER , HSP45102 PHASE OFFSET ADDER R.P0-1 P0-1 ENPHAC TXFR LOAD CLK 4-DLY R E G R.P0-1 R.ENPHAC R.TXFR R.LOAD CLK , Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control , Phase Offset Adder compute the phase angle using the frequency control word and the two phase modulation Intersil
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Abstract: The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM , 13 PHASE OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M 3-1 , CLK. Overline designates active low signals. 3-2 HSP45102 PHASE OFFSET ADDER A D D E R , NCO12 consists of a Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine , register. The Phase Accumulator and Phase Offset Adder compute the phase angle using the frequency Intersil
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Numerically Controlled Oscillator phase shift oscillator 13-bit adder 100MHz sine wave generator
Abstract: accumulator to offset the phase in 90° increments. The 13-bit output of the Phase Offset Adder is mapped to , FREQUENCY CONTROL SECTION 32 PHASE ACCUMULATOR 13 PHASE OFFSET ADDER 13 SINE ROM , designates active low signals. 3 FN2810.9 April 25, 2007 HSP45102 PHASE OFFSET ADDER A D D , NCO12 consists of a Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine , register. The Phase Accumulator and Phase Offset Adder compute the phase angle using the frequency Intersil
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17 - 33z HSP45102SI-33Z
Abstract: The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via the Sine ROM , 13 PHASE OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M 3-195 , designates active low signals. 3-196 HSP45102 PHASE OFFSET ADDER A D D E R R.P0-1 LOAD , of a Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The , Accumulator and Phase Offset Adder compute the phase angle using the frequency control word and the two Intersil
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M 3195
Abstract: Offset Adder is mapped to the sine wave amplitude via the Sine ROM. The output data format is offset , ACCUMULATOR 13 PHASE OFFSET ADDER 13 SINE ROM 12 OUT0-11 LOAD TXFR ENPHAC SEL_L/M , OFFSET ADDER A D D E R R.P0-1 LOAD CLK / R.ENPHAC SINE ROM 12 / CLK 2 , Accumulator, a Phase Offset Adder and a Sine ROM. The Frequency Control section serially loads the frequency control word into the frequency register. The Phase Accumulator and Phase Offset Adder compute the phase Intersil
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Abstract: 0° increments. The 13-bit output of the Phase Offset Adder is mapped to the sine wave amplitude via , consists of a Frequency Control Section, a Phase Accumulator, a Phase Offset Adder and a Sine ROM. The , Accumulator and Phase Offset Adder compute the phase angle using the frequency control word and the two phase , adder compute the phase of the sine wave from the frequency control word and the phase modulation bits , feedback to the phase accumulator. The phase adder sums the encoded phase modulation bits PO-1 and the -
OCR Scan
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