NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: / C4 128Mx4 64Mx8 8 Banks K4Y50084UE-JC K4Y50084UE-JC Code J Description BOC lead free 104ball BOC EOL 1.8V± 0.09 32K/16ms 104ball BOC Now 128Mx4 64Mx8 1.8V± 0.09 32K/16ms ... | Original |
3 pages, |
Rambus XDR 256Mx2 XDR Rambus XDR DRAM K4Y50164UE datasheet abstract |
| Abstract: 10 30 30 30 128Mx4 45 12 12 60 60 60 Unit Condition pF VIN = 0V DC INPUT , +40 +40 0.4 2.4 2.4 DC OPERATING CHARACTERISTICS Symbol 128Mx4 Min. Conditions , 128Mx4 32Mx4 64Mx4 128Mx4 32Mx4 64Mx4 128Mx4 32Mx4 64Mx4 128Mx4 32Mx4 64Mx4 128Mx4 32Mx4 64Mx4 128Mx4 8K 4K 8K 4K 8K 152 156 164 4 8 16 152 156 164 82 86 94 2 4 ... | Original |
10 pages, |
64Mx4 30A173-11 30A173-11 abstract |
| Abstract: 128Mx4 Mono 128Mx4 Stacked 256M x 4 Mono 256M x 4 Stacked *For speed and vendor specific part ... | Original |
2 pages, |
DDR333 DDR266 DDR200 datasheet abstract |
| Abstract: 128Mx4 128Mx4 MT46V64M8FN MT46V64M8FN 64Mx8 MT46V64M8TG MT46V64M8TG 64Mx8 MT46V32M16FN MT46V32M16FN LatticeECP/EC/XP , K4H511638B-TC/LB3 K4H511638B-TC/LB3,CC 32Mx16 DDR400 DDR400 DDR333 DDR333 200MHz 167MHz K4H510438B-TC/LB3 K4H510438B-TC/LB3 128Mx4 DDR333 DDR333 167MHz K4H510438B-NC/LB3 K4H510438B-NC/LB3 128Mx4 DDR333 DDR333 167MHz HYB25D128400AT HYB25D128400AT Samsung 512Mb B die , 200MHz 167MHz 167MHz DDR UG TN1050 TN1050_03.1J Oct. 2005 HYB25D512400AT HYB25D512400AT 128Mx4 DDR266 DDR266 133MHz HYB25D512400BT HYB25D512400BT 128Mx4 DDR333 DDR333 167MHz HYB25D512400BE HYB25D512400BE 128Mx4 DDR333 DDR333 167MHz ... | Original |
37 pages, |
TN1050 EC20 DDR-266 TN1050 abstract |
| Abstract: 128Mx4 DDR2 SDRAM Die B Features · Differential clock inputs · Data is read or written on both clock , on 128Mx4 DDR2 SDRAM (NT5TU128M4BE NT5TU128M4BE) · JEDEC Standard 240-pin Dual In-Line Memory Module · Error , 64Mx8 (NT512T72U89B0BV NT512T72U89B0BV), eighteen 128Mx4 (NT1GT72U4PB0BV NT1GT72U4PB0BV) or thirty-six 128Mx4 (NT2GT72U4NB0BV NT2GT72U4NB0BV , , 1 Rank, 128Mx4 DDR2 SDRAMs) ! ! ! ! ! ! ! " " " " " " " " ! # , DDR2-533/667 DDR2-533/667, 2 Ranks, 128Mx4 DDR2 SDRAMs) REV 1.3 05/2007 7 © NANYA TECHNOLOGY CORP. NANYA ... | Original |
25 pages, |
PC2-6400 PC2-5300 NT5TU64M8BE NT1GT72U4PB0BV-3C DDR2 DIMM 240 pinout NT2GT72U4NB0BV NT2GT72U4NB1BV NT512T72U89B0BV NT1GT72U4PB0BV 512MB NT5TU128M4BE NT2GT72U4NB0BV abstract |
| Abstract: DDR2 SDRAM DIMM 240pin Low Profile Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM Features , 128Mx4 DDR2 SDRAM · Bi-directional data strobe with one clock cycle preamble and · JEDEC Standard , module uses thirty-six 128Mx4 DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards , Functional Block Diagram (2Ranks, 128Mx4 DDR2 SDRAMs) Vss RS1 RS0 DQS0 DQS0 DQS9 DQS9 DQS DQS CS I , Detect - Part 1 of 2 256Mx72 2 BANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh ... | Original |
14 pages, |
SSTL-18 PC2-3200 NT2GT72U4NA0BU-5A DDR2-400 NT2GT72U4NA0BV NT2GT72U4NA0BV-5A NT2GT72U4NA0BU NT2GT72U4NA0BU abstract |
| Abstract: Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM Features · 128Mx72 Low Profile Registered DDR2 DIMM based on · Data is read or written on both clock edges 128Mx4 DDR2 SDRAM · Bi-directional data , one-bank 128Mx72 high-speed memory array. The module uses nine 128Mx4 DDR2 SDRAMs in FBGA packages. These , NT1GT72U4PA0FU NT1GT72U4PA0FU 1GB: 128M x 72 Low Profile Registered DDR2 SDRAM DIMM Functional Block Diagram (1Rank, 128Mx4 , Detect - Part 1 of 2 128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh ... | Original |
15 pages, |
SSTL-18 PC2-3200 NT1GT72U4PA0FU-5A DDR2-400 DDR2 DIMM 240 pinout NT1GT72U4PA0FU NT1GT72U4PA0FU abstract |
| Abstract: 240pin Low Profile Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM Features · 128Mx72 Low Profile Registered DDR2 DIMM based on · Data is read or written on both clock edges 128Mx4 DDR2 , Module (DIMM), organized as a one-bank 128Mx72 high-speed memory array. The module uses eighteen 128Mx4 , Registered DDR2 SDRAM DIMM Functional Block Diagram (1Rank, 128Mx4 DDR2 SDRAMs) VSS RS0 DQS0 DQS0 , 1 of 2 128Mx72 1 BANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 ... | Original |
14 pages, |
SSTL-18 PC2-3200 NT1GT72U4PA0BU-5A NT1G DDR2-400 NT1GT72U4PA0BV-5A NT1GT72U4PA0BU NT1GT72U4PA0BV NT1GT72U4PA0BU abstract |
| Abstract: Registered DDR2 SDRAM MODULE Based on 128Mx4 DDR2 SDRAM Features · 128Mx72 Registered DDR2 DIMM based on 128Mx4 DDR2 SDRAM · JEDEC Standard 240-pin Dual In-Line Memory Module · Error Check Correction (ECC , 128Mx4 DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad , ) 1GB: 128M x 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (1Rank, 128Mx4 DDR2 SDRAMs , 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte DDR2-400 DDR2-400 -5A ... | Original |
13 pages, |
SSTL-18 PC2-3200 DDR2-400 NT1GT72U4PA0BU-5A NT1GT72U4PA0BV-5A NT1GT72U4PA0BU NT1GT72U4PA0BV NT1GT72U4PA0BU abstract |
| Abstract: DIMM 184pin Low Profile Registered DDR SDRAM DIMM Based on 128Mx4 DDR SDRAM C Die device Features , device organized as 128Mx4 (NT5DS128M4CG-5T NT5DS128M4CG-5T). · Performance: · Data is read or written on both clock , NT1GD72S4PC0FV NT1GD72S4PC0FV has a single rank using eighteen 128Mx4 BGA devices. NT2GD72S4NC0FV NT2GD72S4NC0FV is double rank using thirty-six 128Mx4 BGA devices. Depending on the speed grade, these DIMMs are intended for use in , Registered DDR SDRAM DIMM Functional Block Diagram 1 Rank, 18 devices, 128Mx4 DDR SDRAMs , ,0 ,0 ,0 ... | Original |
15 pages, |
PC3200 NT5DS128M4CG-5T DDR400 NT1GD72S4PC0FV/NT2GD72S4NCOFV NT1GD72S4PC0FV/NT2GD72S4NCOFV abstract |
| Abstract: MPD Parts Directory (March 2002) Stack Technology Stack Memory Configuration Stack Part Number TSOP Memory Configuration SRAM (8M) 512K x 16 ISAS512K16LTD ISAS512K16LTD (4M) 256K x 16 EDO DRAM (128M) 16M x 8 ISED16M8LTB ISED16M8LTB (64M) 16M x 4 SDRAM SDRAM SDRAM SDRAM SDRAM (512M) (512M) (512M) (512M) (512M) 128M x 4 64M x 8 64M x 8 32M x 16 32M x 16 ISSD128M4STB ISSD128M4STB ISSD64M8STB ISSD64M8STB ISSD64M8STC ISSD64M8STC ISSD32M16STC ISSD32M16STC ISSD32M16STD ISSD32M16STD (256M) (256M) (256M) (256M) (256M) ... | Original |
1 pages, |
TSOP SDRAM SDRAM ISSD16M16STC ISSD128M4STB ISAS512K16LTD 512M DDR dRAM 512M 8M X 16 X 4 SDRAM 8M X 16 SDRAM datasheet abstract |
| Abstract: DTM60117 DTM60117 1024MB-128M 1024MB-128M x 72, 168-Pin Registered PC100 PC100 SDRAM DIMM Identification Part number: DTM60117 DTM60117 Performance range 100MHz (10ns@ CL=3) Features Description Burst mode operation The Dataram DTM60117 DTM60117 Assembly is a 128M bit x 72 Synchronous Dynamic RAM high density memory module. The DTM60091 DTM60091 consists of eighteen CMOS Stacked 128M x 4 bit Synchronous DRAMs in two TSOP-II 400MiI packages, three 20-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package ... | Original |
1 pages, |
DTM60117 DTM60091 Dataram 1024MB-128M PC100 DTM60117 abstract |
| Abstract: Memory Module Data Sheet L2572Y37 L2572Y37 2GB 256M x 72-bit ECC Registered DDR400 DDR400 (PC3200 PC3200) SPECIFICATIONS; · 2GB (256M x 72-bit) Registered DDR400 DDR400 DIMM · Error Check Correction (ECC) Capability · FBGA 128M x 4 (32M x 4 bit x 4 Bank/200Mhz) x Thirty Six DRAM · 184-pin Dual in-line memory module with Gold Plated Contacts · Dimm Dimensions 133.35 x 30.46 x 3.99 (mm) · Programmable CAS Latency Supported - CL 3 · Row Cycle Time (tRC) - 55ns · Auto Refresh Cycle Time (tRFC)- 120ns (min.) · Row Act ... | Original |
1 pages, |
DIMM DDR400 PC3200 DDR400 PC3200 L2572Y37 L2572Y37 abstract |
| Abstract: Memory Module Data Sheet L1272337-R41H2M1F L1272337-R41H2M1F 1GB 128M x 72-bit DDR2 400 (PC3200 PC3200) SPECIFICATIONS; · 1GB (128M x 72-bit) Registered DDR2 400 DIMM, 1 RANK · Error Check Correction (ECC) Capability · 84-ball FBGA 128M x 4 (32M x 4 bit x 4 Bank/200Mhz) x Eighteen DRAM · 240-pin Dual in-line memory module with Gold Plated Contacts · Dimm Dimensions 133.35 x 30 x 4 (mm) · Programmable CAS Latency Supported - CL 5 · Row Cycle Time (tRC) 55ns · Auto Refresh Cycle Time (tRFC) - 105 ns · Row Ac ... | Original |
1 pages, |
PC3200 ddr2 module ecc 128M 72 DDR2-400 L1272337-R41H2M1F L1272337-R41H2M1F abstract |
| Abstract: Memory Module Data Sheet L2572Y36 L2572Y36 2GB 256M x 72-bit ECC Registered DDR333 DDR333 (PC2700 PC2700) SPECIFICATIONS; · 2GB (256M x 72-bit) Registered DDR333 DDR333 DIMM · Error Check Correction (ECC) Capability · 60ball FBGA 128M x 4 (32M x 4 bit x 4 Bank/200Mhz) x Thirty Six DRAM · 184-pin Dual in-line memory module with Gold Plated Contacts · Dimm Dimensions 133.35 x 30.48 x 3.99 (mm) · Programmable CAS Latency Supported - CL 2.5 · Row Cycle Time (tRC) - 60ns · Auto Refresh Cycle Time (tRFC)- 72ns (min.) · ... | Original |
1 pages, |
PC2700 memory module DDR333 60ns L2572Y36 L2572Y36 abstract |
| Abstract: Memory Module Data Sheet L12723C7 L12723C7 1GB 128M x 72-bit DDR2 400 (PC3200 PC3200) SPECIFICATIONS; · 1GB (128M x 72-bit) Registered DDR2 400 DIMM, 1 RANK · Error Check Correction (ECC) Capability · 84-ball FBGA 128M x 4 (32M x 4 bit x 4 Bank/200Mhz) x Eighteen DRAM · 240-pin Dual in-line memory module with Gold Plated Contacts · Dimm Dimensions 133.35 x 30 x 4 (mm) · Programmable CAS Latency Supported - CL 5 · Row Cycle Time (tRC) 55ns · Auto Refresh Cycle Time (tRFC) - 105 ns · Row Active Time ... | Original |
1 pages, |
PC3200 ddr2 module ecc 128M 72 DDR2-400 L12723C7 L12723C7 abstract |
| Abstract: Samsung DDR2 for Servers Fully Buffered and Registered DIMMs Support Maximum Bandwidth and Fast Data Access DDR2 Features Optimize Server Performance Samsung's broad line of high-density memory modules delivers the ultimate in computing power, flexibility and performance for servers. The need for increased server performance is unrelenting, thus DDR2 SDRAM is now the high-density standard for server main memory. Its advanced architecture gives DDR2 a host of advantages over ... | Original |
2 pages, |
DDR333 DDR333 abstract |
| Abstract: ADVANCE D COM P ON E NTS PACKAG I NG 1 Gigabit CMOS DDR SDRAM DPDD128MX8XSAY5 DPDD128MX8XSAY5 DESCRIPTION: The Memory StackTM series is a family of interchangeable memory devices. The 1 Gb, CMOS DDR Synchronous DRAM assembly utilizes the space saving LP-StackTM technology to increase memory density. This stack is constructed with two 512Mb (128M x 4) DDR SDRAMs. FEATURES: · Electrical characteristics meet semiconductor manufacturers' datasheet · Memory organization: (2) 512Mb memory devices. Each ... | Original |
2 pages, |
DPDD128MX8XSAY5 IPC-A-610 DPDD128MX8XSAY5 abstract |