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Part : USB1T1104MHX Supplier : Fairchild Semiconductor Manufacturer : Rochester Electronics Stock : 10,382 Best Price : $0.72 Price Each : $0.72
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1104MH

Catalog Datasheet MFG & Type PDF Document Tags

PCS6105CT

Abstract: GRM40Z5U104M050A least 10 X the highest operating frequency (1.104MHz is the highest ADSL operating frequency). 20X or
Texas Instruments
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THS6093EVM THS6093 PCS6105CT GRM40Z5U104M050A SLMA002 SLMA004 THS6062 SLOU141 89F2885 SLOP396 THS6093CPWP

HC6094

Abstract: HC6094IN Peak to Peak GP Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS , FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth Stopband Attenuation
Harris Semiconductor
Original
HC6094 HC6094IN 5M-1982

GC114

Abstract: reverb effect ) Data Word Clock = 4.416MHz (2 Bits) Data Word Clock = 2.208MHz (2 Bits) Data Word Clock = 1.104MHz (2
Texas Instruments
Original
AFE1302 TQFP-48 GC114 reverb effect adsl modem input circuit 328MH 832MW
Abstract: Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS At 2.65MHz 14 , RX q u t ) RECEIVER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz -
OCR Scan
1-800-4-HARRIS

DAC Combo

Abstract: Combo Driver 138kHz/ 276kHz TX Out PAA and Line Driver 16 ADC 4.4MS/s RX LPF 552kHz/ 1.104MHz
DataPath Systems
Original
DPS8100 DAC Combo Combo Driver DPS8001

adsl lite

Abstract: ADSL Modem circuit diagram , should be 1.104MHz(276kHz) . DMT inherently transmits an optimized time-variable spectrum. This spectrum , ns Figure 5: AFE Data I/F Timing Diagram t2 t3 AFE_SEN_N AFE_SCL (1.104MHz) AFE_SDO
Samsung Electronics
Original
S5N8944B adsl lite ADSL Modem circuit diagram ATM timing diagram interleaver 8309 teaklite KS8944A 160-QFP

Dittmer RTD

Abstract: sp 201 adsl splitter circuit diagram 1.104MHz ADSL30kHz1.1MHz 10Mbps 12 2.2MHz ADSL 14 ADSL12 ADSL 14ADSL
Linear Technology
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Dittmer RTD sp 201 adsl splitter circuit diagram LTC2400 rtd sp 201 adsl splitter D link schematic circuit diagram adsl modem board ADSL Central Office CO Chipset 400MH LTC1645/LTC1735 D-85737 S-191 1-800-4-LINEAR

AN 7085

Abstract: DN70EP7-A100 frequency bands (138 KHz, 1.104MHz) - LNA input = â'11â' (max attenuation) - VCO dac and Echo path
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DN70EP7-A100 AN 7085 SIEMENS BST N 45 b 110 IDC bh Mg-Zn Ferrites MgZn 5M80MH 1M300MH 100BASE-T IEEE802 198310BASE5 1995F
Abstract: ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared Alcatel
Original
MTC-20144 MTC-20146 MTK-20140 MTC-20144TQ- 12/98-DS254
Abstract: . selection: Fc = 1.104MHz (¡nit) 0 0 1 1 0 1 0 HC freq. selection: Fc = 1.104MHz-43.75% = 621kHz , Frequency band 1.104MHz (0%setting, see below) Frequency tuning -43.75%->+0% Max. in-band ripple 1dB , Out-of-band noise 1.6|xVHz1/2 1.6|xVHz1/2 150nVHz~1/2 @ 34.5kHz -138kHz @138kHz @ 250kHz -1.104MHz For min Texas Instruments
Original

DIGITAL ECHO pcb

Abstract: 400khz xtal uc d 1Vpd 3rd order butterworth 1.104MHz (0% setting, see below) -43.75% -> +0% 1dB [B, A , group delay < 50µs @ 138kHz < f < 1.104MHz Total RX filter group delay distortion < 15µs @ 138kHz < f < 1.104MHz 8/22 s) t( ST70134A Figure 5 : HC Filter Mask for RX Amplitude ±1dB , -138kHz 500nVHz-1/2 @ 34kHz -138kHz @ 250kHz -1.104MHz For min AGC setting (=-15dB) In-band , ) * SC freq. selection: Fc ~ 170kHz HC freq. selection: Fc = 1.104MHz 0 * SC freq. selection
-
OCR Scan
STLC60134 STLC60135 TQFP64 DIGITAL ECHO pcb 400khz xtal Digital TV transmitter receivers block diagram 150De 35. 328m 138KHZ

ST70134

Abstract: ST70134A minimum value. - Nominal filter frequency bands (138 KHz, 1.104MHz) - LNA input = "11" (max attenuation
STMicroelectronics
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ST70134 ST70135A ST70235 ST70135

ST TX01

Abstract: lt 5234 consists of two programmable-gain amplifiers, a frequency equalizer, a 1.104-MHz low-pass analog filter, a 14-bit high speed ADC, and a 1.104-MHz low-pass digital filter. The clock circuit divides a 35.328 , the high resolution ADC. The receiver channel also has a 1.104-MHz low-pass filter with a 4.416 MSPS
Alcatel
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MTC-20144TQ-I ST TX01 lt 5234 VCO 35.328 MHz oscillator HC1 mtc 110 16 1104MH

TXM TX 2E

Abstract: TLV320AD11A ) Data Word Clock = 4.416MHz (2 Bits) Data Word Clock = 2.208MHz (2 Bits) Data Word Clock = 1.104MHz (2
Texas Instruments
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TLV320AD11A TXM TX 2E TMS320C6xx SLWS087B 100-P TLV320AD12

AFE1302

Abstract: TQFP-48 ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared
Texas Instruments
Original

24GC0

Abstract: rfid key programmable-gain amplifiers, a frequency equalizer, a 1.104-MHz low-pass analog filter, a 14-bit high speed ADC, and a 1.104-MHz low-pass digital filter. The clock circuit divides a 35.328-MHz frequency from an , receiver channel also has a 1.104-MHz low-pass filter with a 4.416 MSPS and a 14-bit ADC to provide a 2X
Texas Instruments
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24GC0 rfid key

TXM TX 2E

Abstract: (300kHz to 1.104MHz) > =15(30kHz to 300kHz) > =55(300kHz to 1.104 MHz) ADSL POTS Splitter Shapes
Texas Instruments
Original
SGLB002 SGYC003B TLV320AD11APZ TLV320AD11APZR

phone and modem splitter block diagram

Abstract: phone line splitter circuit diagram ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared
NEC/TOKIN
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BF-2005 PSR-1080 BF-2008 PSR-1180 phone and modem splitter block diagram phone line splitter circuit diagram phone and modem splitter circuit diagram low pass filter circuit 3.4khz NEC Tokin SPLITTER ADSL 1004H 104MH
Abstract: 40.0 1MHz 1.104MHz 30.0 20.0 10.0 0.0 5 7.5 10 20 30 40 50 60 70 , 300KHz 80 100 400KHz 1MHz 110 1.104MHz 110 50 90 80 70 90 100 70 Texas Instruments
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