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3022-010-N TE Connectivity Ltd ACCELEROMETER 10G ANALOG visit Digikey Buy
2231705-5 TE Connectivity (2231705-5) QSFP+, 10G FLEXIBLE, 5M, 26AWG visit TE Connectivity
RH73X2A10GNTN (1625862-1) TE Connectivity (1625862-1) RH73 2A 10G 30% 1000PPM visit TE Connectivity
RH73X1E10GKTN (1879237-4) TE Connectivity (1879237-4) RH73 1E 10G 10% 1000PPM visit TE Connectivity
2231705-1 TE Connectivity (2231705-1) QSFP+, 10G FLEXIBLE, 1M, 30AWG visit TE Connectivity
RH73X2B10GKTN (1625862-8) TE Connectivity (1625862-8) RH73 2B 10G 10% 1000PPM visit TE Connectivity

10G BERT

Catalog Datasheet MFG & Type PDF Document Tags

tx 2G transmitter

Abstract: tx 2G loopback, BIST, 10G BERT, and random Ethernet packet generation Compact 23-mm × 23-mm package with no , Cross-Link Application Diagram Rx OVERVIEW 10G XAUI_0 10G XAUI_2 Channel_0 (1­3.2G , ) Channel_3 (1­3.2G) Channel_3 (1­3.2G) Bus Mux 10G XAUI_1 10G XAUI_3 Channel_4 (1­3.2G
Broadcom
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BROADCOM "heat sink"

Abstract: BCM8020 Serial and parallel loopback, BIST, 10G BERT, and random Ethernet packet generation · IEEE (1149.1 , RX OVERVIEW 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI , _3 (1­3.2G) Channel_3 (TBI, RTBI) (Control/Clocking) Bus MUX 10G XAUI_1 10G XGMII_1 Channel
Broadcom
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10G serdes 2.5 xaui

Abstract: 10G serdes bert Serial and parallel loopback, BIST, 10G BERT, and random Ethernet packet generation · IEEE (1149.1 , 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI) Channel_1 (1­3.2G , Channel_3 (TBI, RTBI) (Control/Clocking) 10G XAUI_1 10G XGMII_1 Channel_4 (1­3.2G) Channel
Broadcom
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Abstract: capability â'¢ â'¢Enhanced testBIST, 10G BERT, and random Ethernet packet Full loopback, generation â , CML I/O. â'¢ 1GbE and 10GbE LAN, MAN, WAN Switches and Routers â'¢ 1x, 2x, or 10G Fibre Channel Broadcom
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10G serdes 2.5 quad

Abstract: 10G BERT equalization for copper interconnects Enhanced test capability · Serial and parallel loopback, BIST, 10G BERT , × XGMII/TBI 2× XAUI 2 Independent Quad SerDes Application Diagram Rx OVERVIEW 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI) Channel_1 (1­3.2G) Channel_1 (TBI , ) Bus Mux (Control/Clocking) 10G XAUI_1 10G XGMII_1 Channel_4 (1­3.2G) Channel_4 (TBI
Broadcom
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Abstract: interconnects â'¢ Enhanced test capability â'¢ Full loopback, BIST, 10G BERT, and random Ethernet packet , Rx B C M 8 0 4 0 O V E R V I E W BCM8040 Block Diagram 10G XAUI_0 10G XAUI_2 Channel , ) Channel_2 (1â'"3.2G) Channel_3 (1â'"3.2G) Bus Mux Channel_3 (1â'"3.2G) 10G XAUI_1 10G XAUI Broadcom
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IEEE802 OC-48 8040-PB03-R-04-15-03
Abstract: parallel loopback, BIST, 10G BERT, and random Serial and Decreases complexity and reduces â , , 2x, or 10G Fibre Channel, Infiniband, SONET Network Cards â'¢ Advanced Test Equipment (ATE Broadcom
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BCM8020 1875G 8020-PB00-R-3

10G BERT

Abstract: CX4 connector for copper interconnects Enhanced test capability · Full loopback, BIST, 10G BERT, and random
Broadcom
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10G BERT CX4 connector 8040-PB06-R
Abstract: loopback, BIST, 10G BERT, and random Ethernet packet generation Compact 23-mm × 23-mm package with no Broadcom
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8040-PB05-R

10G BERT

Abstract: MultiBERT connection tests over an ATCA backplane. MultiBERT is based on the Xilinx ATCA 10G 4X4 Line Card (hereafter , Introduction BERT BERT BERT Serial Mesh Backplane BERT BERT BERT PPC Platform ATCA Card PPC Platform ATCA Card Ethernet BERT BERT BERT PPC Platform ATCA Card X537 , Acronym Definition ATCA Advanced Telecom Computing Architecture BERT Bit Error Rate Test , system consists of the following components: · ATCA Backplane · ATCA 10G 4X4 Line Card ·
Xilinx
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XAPP537 MultiBERT PICMG 3.0 Revision 1.0 XC2VP70 UG024 ML300

10G BERT

Abstract: eprom ic sublayers of the 10G Ethernet and Fibre Channel standards. For WAN applications a standard OC-192/STM , bit error rate tester (BERT) usable for multiple atspeed diagnostic scenarios Includes the XGXS, PCS , Line Interface Gbit/s BERT BERT Framer Framer 4x 3.125 Sync & Sync & Deskew Deskew , XGXS Clock LA TIA Photodiode E²PROM I²C Interface Transponder Module 10G Ethernet
Infineon Technologies
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eprom ic GR-253-CORE STM64 STM-64 VC4-64c OC-192 51875G OC-192/STM-64 1413-D
Abstract: over SONET/SDH. â'¢ Packet BERT: Highly versatile and independent module used to gener ate and , , a SONET/SDH Framer, POS Mapper/DeMapper, and Packet Bit Error Rate Test (BERT). The Framer: STS , network cores from 10G (OC -192) to 40G (OC-768) to support higher -bandwidth â'triple-playâ' (voice , RxDCC/RxTOH/RxPOH 3 3 3 POS Mapper POS De-Mapper Packet BERT Generator TxDCC/TxTOH , Interlaken Interface Packet BERT Monitor SONET/SDH Framer Rx FIF O and C trl 17 L i ne Inter Cortina Systems
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CS1999

interlaken network processor

Abstract: OC-768 with industry standard 40G optical modules. The industry is upgrading network cores from 10G (OC , /DeMapper, and Packet Bit Error Rate Test (BERT). The 16 (data) 16 (address) 40G POS Mapper is connected , path overhead. POS Mapper: Single 40G mapper that maps packets over SONET/SDH. Packet BERT: Highly , POS Mapper POS De-Mapper Packet BERT Generator 16 RxDCC/RxTOH/RxPOH TxDCC/TxTOH/TxPOH GPIO , Overhead Processor Path Overhead Processor Interlaken Interface SFI-5.1 Packet BERT Monitor
Cortina Systems
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interlaken network processor overhead processor Cortina Systems 10G serdes bert

10G BERT

Abstract: K line interface Integrated bit error rate tester (BERT) usable for multiple atspeed diagnostic scenarios Includes the XGXS , Block Diagram XAUI Interface 4x 3.125 Gbit/s Sync & Sync & Deskew Deskew BERT BERT 8B , Module Management Interface I²C Interface E²PROM (optional) 10G Ethernet / Fibre Channel
Infineon Technologies
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K line interface

MDIO clause 22

Abstract: "programmable on-chip termination" budgets. Data I/O is handled by two 10G Attachment Unit Interface (XAUI) ports. Configuration , ) for re-timing, deserializer, code word synchronizer, lane aligner, Idle/BERT logic, serializer , /S Idle and Bert Logic Idle and Bert Logic P/S Equalizer and FAUI XMTR I n ter , polarity · Programmable on-chip termination resistors s BERT generators/checkers with error counters , resistors s BERT generators/checkers with error counters s Helps reduce time and equipment for
Intel
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LXT35401 MDIO clause 22 lazer lazer diode intel xenpak LXT11001 10GBASE-LX4 8B/10B USA/0102/5K/MGS/DC

MAX15059

Abstract: 10G APD 1310nm 10G Electrical Loopback BERT CLK TXREFCLK TXPICLK DEMUX 622M x16 MUX Optical TX , phase delay element, a CDR (clock-anddata-recovery) unit, and a serial BERT (bit-error-rate tester). At , TDIP TDIN 0-100ps DELAY 50 ohm 10G CDR RxREFCLK TCOP RDIP TDOP Figure 4. Setup , signal to received signal delay is varied by one UI (100-psec). Device under test is a 10G bidirectional , Integrated Products Page 6 of 9 TITLE: 10G BIDIRECTIONAL TRANSCEIVER CHIP 10G BIDIRECTIONAL TRANSCEIVER
Maxim Integrated Products
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MAX15059 10G APD 1310nm 10G CDR MAX3799 for APD bias 14-Gbps HFTA-12 DS1874

1310nm 10Gbps DML

Abstract: hall 04E 10G Electrical Loopback BERT CLK TXREFCLK TXPICLK DEMUX 622M x16 MUX Optical TX , phase delay element, a CDR (clock-anddata-recovery) unit, and a serial BERT (bit-error-rate tester). At , TDIP TDIN 0-100ps DELAY 50 ohm 10G CDR RxREFCLK TCOP RDIP TDOP Figure 4. Setup , signal to received signal delay is varied by one UI (100-psec). Device under test is a 10G bidirectional , Integrated Products Page 6 of 9 TITLE: 10G BIDIRECTIONAL TRANSCEIVER CHIP 10G BIDIRECTIONAL TRANSCEIVER
Maxim Integrated Products
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1310nm 10Gbps DML hall 04E MAX3872 HALL EFFECT 21E hall effect 44e hall ic 01e 155MH

microstripline FR4

Abstract: rogers 4403 full-duplex 10G Serial RocketIOTM X transceivers (embedded) Up to 2 IBM® PowerPC® RISK Processor blocks , Backplane Daughtercard 0XT SIP 1000 MK 322 MK322 TX Thru RX TX DCA BERT LoopBack , sent out to Agilent 71612 BERT box · Better than 10-12 BER for 10Gb/s NRZ after 32" FR4 and 2 0XT , k Src Agilent 71612C BERT Rack 50 Conclusion · Importance of crosstalk in high-speed
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microstripline FR4 rogers 4403 microstripline rogers* 4403 rogers Agilent 322 81134AC
Abstract: BCM8320 PRODUCT Brief DUAL 10G B C M 8 3 2 0 FABRIC F E AT U R E S â'¢ Highly integrated, scalable switch fabric â'¢ Single-chip bandwidth of up to 40 Gbps interfaces side â'¢ â'¢Supports two CSIX32, 64, or 128to line speeds up to Each CSIX supports bits at 166 MHz â , scheduling â'¢ â'¢Proven high-speed 3.125 Gbps SerDes technology Built-in BERT INTERFACE S U M M A R , . â'¢ Supports dual 10G interfaces in a single device. â'¢ Excellent redundancy: all links that are Broadcom
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BCM8332 BCM83XX 125-G 8320-PB02-R-6

10G serdes bert

Abstract: prbs pattern generator Bit-Error Rate Tester (BERT) combined with a Time Interval Analyzer (TIA) to generate transmit jitter , components and levels as defined for the 10G Ethernet XAUI standard3. The test setup for this method is , Random Noise Clock Source DDJ Source BERT Hybrid Pattern Generator Clock Source Error
Lattice Semiconductor
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ORT82G5 8656B prbs pattern generator 10G serdes 2.5 quad TN1032 HP83480A 10GFC T11/P
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