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Part Manufacturer Description Datasheet BUY
LT1397CDE#TR Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, PDSO14, 4 X 3 MM, PLASTIC, MO-229, DFN-14, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices
LT1228IS8 Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, PDSO8, 0.150 INCH, PLASTIC, SOP-8, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices
LT1223MJ8 Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, CDIP8, 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices
LT1228MJ8#TR Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, CDIP8, 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices
LT1223CN8#TRPBF Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, PDIP8, 0.300 INCH, LEAD FREE, PLASTIC, DIP-8, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices
LT1397CDE Linear Technology IC 1 CHANNEL, VIDEO AMPLIFIER, PDSO14, 4 X 3 MM, PLASTIC, MO-229, DFN-14, Audio/Video Amplifier visit Linear Technology - Now Part of Analog Devices

1024k x 8 bits fifo Video Frame

Catalog Datasheet MFG & Type PDF Document Tags

82C9001A

Abstract: 1024k x 8 bits fifo Video Frame 's internal FIFO and is stored in the frame buffer. The acquisition process is synchronized to the input video , supported at resolutions up to 1024 x 512 pixels. PC Video may be programmed to capture a full-size video , graphical user interfaces. MEMORY INTERFACE PC Video operates with 256K x 4 100 ns VRAMs. Three , below. The X:Y:Z numbers refer to the number of samples for the three input video components. 1) 4:1:1 - , video data as part of the acquisition process. The scaled image is stored in the frame buffer. When
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60 pin LCD connector to vga 15 pin conversion

Abstract: crt monitor repair / SVGA up to 768 x 1024 Pixel 64k Colors TFT: 640 x 480 , 800 x 600, 1024 x 768 with 8,9,12,15,16,18 Bits STN: 640 x 480 , 800 x 600, 1024 x 768 Monochrome STN: 640 x 480 with 64 colors 2-2/3 and 5-1/3 , is set to 6 bits of R, G & B. If DAC is set to 8-Bit output mode, the number of available colors is , x 768 1024 x 768 1024 x 768 1024 x 768 640 x 480 640 x 480 1024 x 768 1024k 1024k 1024k , . 17 8 8.1 8.2 9 POSSIBLE FAILURES
DIGITAL-LOGIC
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Abstract: AL4V4M422/AL4V8M422 consists of 4M/8M-bits of DRAM, and is configured as 512K/1,024K x 8 bit FIFO (first in , to keep real estate to a minimum. 2.0 Features 4M/8Mbits (512K/1,024K x 8 bits) FIFO , / AL4V8M422 are configured as 512K/1,024K x 8-bit FIFO to accommodate NTSC, PAL or up to SVGA/XGA resolution , /AL4V8M422 January 30, 2004 2 AL4V4M422/AL4V8M422 AL4V4M422/AL4V8M422 4M/8M-Bits FIFO Field , correction (TBC) Frame synchronizer Digital video camera Buffer for communications systems 4.0 AverLogic Technologies
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AL4V4M422
Abstract: /O accesses and memory accesses as either an 8- or 16-bit device. CPU FIFO The CPU FIFO contains a , BLANK signals required by the RAMDAC. Video FIFO The Video FIFO allows the Memory Sequencer to , , using Fast Page Mode cycles to fill the Video FIFO. This allows the maximum possible time for the host , access for write to display â'¢ Screen Refresh Data Caching (Video FIFO) mini­ mize memory contention , CL-GD5410 supports extensions to VGA, including 1024-X-768, 8-bit pixel modes and 800x-600, 16-bit pixel -
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1024K

82C9001A

Abstract: 82c9001 's internal FIFO and is stored in the frame buffer. The acquisition process is synchronized to the input video , broadcast quality video bandwidth â  Up to 800 x 600 display resolution â  Supports NTSC, PAL, SECAM , factors of 2,4 and 8 â  Full-motion color video support on flat-panel displays with the 82C457 Video , .5 System Configuration Examples.6 PC Video class="hl">8 Video class="hl">8 Signal class="hl">8
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82C9001A 82c9001 TTL parallel to vga TDA8708 Mask08 SAA7192 1024H

F82C9001

Abstract: F82C9001A and 8 n Full-motion color video support on flat-panel displays with the 82C457 n Input resolutions up to 1024H x 512V pixels with full broadcast quality video bandwidth n Up to 800 x 600 , 5 System Configuration Examples. 6 PC Video Description . 8 Video Formats . 8 Signal Flow . 8 , . MEMORY INTERFACE PC Video operates with 256K x 4 100 ns VRAMs. Three configurations are supported: 4
Chips and Technologies
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F82C9001A F82C9001 tda 3050 SAA9057 82C411 philips 107 crt monitor vga connector CHIPS/230 CHIPS/250 CHIPS/280 CHIPS/450 160-P

M5M4V18160CTP

Abstract: M5M4V18160C to record the incoming compressed video data on disk and display full frame rate on screen , sources (4:4:4, 4:2:2, 16 or 8-bit bus) · Selectable Raw/Compressed video out · Variable , internal pull-up to Vdd. When forced to '0', host computer is automatically informed that a video frame , UR_LST_ROW parameter d2: Bit 8 of FDL_1ST_ROW parameter d4-d3: Bits 17-16 of FDL_LST_WORD param. d5: Bit 8 , : Bits 7-0 of VDW_1ST_ROW parameter 26 DRM_PRM8 d7-d0: Bits 7-0 of VDW_LST_ROW parameter Video Setup
Zoran
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ZR36504 ZR36505 M5M4V18160CTP M5M4V18160C nt1003 M5M4V18160 NT1003-1 planar YUV display input

MSM486V500

Abstract: Cyrix 486slc . 4 channels 8 bits 3 channels 16 bits DMA: Interrupts: 8259 comp. 8 + 7 levels PC , up to 768 x 1024 pixels 16/256 colors TFT: 640 x 480 with 8/16/256 colors STN: 640 x 480 , : Size: Bits: Capacity: Banks: 70ns piggy-pack Module MSMRAM 16 Bit 0.5, 1, 2, 4, 8 MBytes , . 8 2.1 STANDARD FEATURES. 8 2.2 UNIQUE FEATURES
DIGITAL-LOGIC
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CH-4542 MSM486V500 Cyrix 486slc 80386 microprocessor interface keyboard monitor TI486SXLC2 floppy disk interface 80486SLC PC/104 MSM486V

hm8694

Abstract: mc1377 , the TP6508 can set some of the video memory as the frame buffer for panel display to decrease video , frame buffer build in video memory that is used by the chipset to accelerate panel refresh rate without , . When using 256kx16 by 2 or 256kx4 by 8, memory size is 1M byte and data size is 32 bits. TP6508 can , bits. All display-memory can be linear addressing. The Video-in interface accept video signal from , FIFO for graphics engine access - Offer 20 stages CRT FIFO and 8 stages Attribute FIFO . Integrates
Topro Technology
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hm8694 mc1377 AOER2 GEC 180 PSX Topro Technology 97c4 32KHZ

nt1004

Abstract: M5M4V4260CTP-6 ) Connects to various YUV sources (4:4:4, 4:2:2, 16 or 8-bit bus) Selectable Raw/Compressed video out , -99 Page 8 of 64 USBvisionTM II Video Compression with Audio & Data ZR36504 Data Sheet PIN , . When forced to '0', host computer is automatically informed that a video frame capture was requested by , parameter d2: Bit 8 of FDL_1ST_ROW parameter d4-d3: Bits 17-16 of FDL_LST_WORD param. d5: Bit 8 of VDW_1ST_ROW parameter d6: Bit 8 of VDW_LST_ROW parameter d7: Bit 18 of FDL_LST_WORD param (16M only). d7-d0: Bits 7-0 of
Zoran
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nt1004 M5M4V4260CTP-6 ZR36 REG64

ITU-R BT.1120 to BT.656

Abstract: BT.1120 , single field/frame captures. An example of Y/C capture is shown in Figure 8. Analog video from a DVD , support BT.656 video I/O, HDTV Y/C I/O at upto 10-bits per component, RGB I/O, MPEG-2 Transport stream , support. Examples include glueless interfaces for BT.656 video I/O, HDTV Y/C I/O at upto 10-bits per , 16-Bit Instruction Set Extensions Operation Quad 8-Bit Dual 16-Bit X X Multiply , video ports to move data from the video port FIFO to external SDRAM through the EMIF. On cycle 2, the
Texas Instruments
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ITU-R BT.1120 to BT.656 BT.1120 1024k x 8 bits fifo Video Frame dm642 video motion jpeg spi NTSC Encoders SPRU615 TMS320DM642 C6000 DM642

amd 486

Abstract: 486DX-CPU Management: none Green PC features, dynamic clock switching 8237A comp. 4 channels 8 bits 3 channels 16 bits DMA: Interrupts: 8259 comp. 8 + 7 levels PC compatible Timers: 8254 comp , 1024 pixels 16/256 colors TFT: 640 x 480 with 8/16/256 colors STN: 640 x 480 monochrome STN: 640 , FIFO Option: COM 1/2: 82C735 (C&T): 2 x 16C550 compatible serial interfaces with FIFO up , . 8 2.1 Standard Features
DIGITAL-LOGIC
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amd 486 486DX-CPU sharp lm64p80 26 pin male FRC connector crt terminal interfacing in 8086 80486DX RS485 INT60

MSE-P5AT-166

Abstract: AT96 8237A comp. 4 channels 8 Bits 3 channels 16 Bits DMA: Interrupts: 8259 comp. 8 + 7 levels , 2 x 72pins SIMM 36 or 32 Bit 4 MBytes, 8 MBytes, 16 MBytes, 32 MBytes 1 Size combinations: Bank1 1 MB x 36 2 MB x 36 4 MB x 36 8 MB x 36 ? Total 2pc. 2pc. 2pc. 2pc. 8 MBytes , . 8 MSE-P5AT specifications , . 79 8 CABLE INTERFACE
DIGITAL-LOGIC
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MSE-P5AT96 MSE-P5AT-166 AT96 interfacing of 8253 devices with 8085 ami bios intel 80586

MD-720-3

Abstract: srf 2417 expansion for 8- or 16-bit pixels â'" True packed-pixel addressing for 4, 8, 16, and 24 bits per pixel â , video playback â'¢ Mixed graphics/video color depths (multi-format frame accelerator) â'¢ Supports 4:2 , or the CL-PX4072) â'¢ Two-chip MPEG solution (MPEG decoder and 256K x 16 DRAM) â'¢ 1024 x 768 video , x 600) â'" Dithering algorithm automatically adds up to 6 bits per primary color without decreasing , single-chip NTSC/PAL video decoder or MPEG decoder by eliminating the need for an additional video frame
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MD-720-3 srf 2417 HDE 3515 cl-gd7543 capacitor lsk 561 VGA 20 PIN LCD MONITOR CABLE CONNECTION DIAGRAM CL-GD7541/7543 CL-GD7548 SAA7110

HDE 3515

Abstract: Cirrus Logic Voyager addressing for 4, 8, 16, and 24 bits per pixel â'" Programmable linear memory addressing â'" 32 x 32 or 64 , /video color depths (multi-format frame accelerator) â'¢ Supports 4:2:2 YCrCb, RGB 5-5-5, and AccuPak , CL-PX4072) â'¢ Two-chip MPEG solution (MPEG decoder and 2 5 6 K x 16 DRAM) â'¢ 1024 x 768 video using , C O L O R LC D (640 X 480 , 8 0 0 x 600, or 1 02 4 x 7 6 8 ) Version 1.2 April 1996 , DRAMs â'" Four 512 K x 8 DRAMs â'" Hardware expansion to 800 x 600 with lower-resolution VGA modes
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Cirrus Logic Voyager

intel pentium p5

Abstract: MSe586 : Size: Bits: Capacity: Bank: 60ns 2 x 72pins SIMM 36 or 32 Bit 4 MBytes, 8 MBytes, 16 MBytes, 32 MBytes 1 Size combinations: Bank1 1 2 4 8 MB MB MB MB x x x x Total 36 , Management: none Green PC features, dynamic clock switching 8237A comp. 4 channels 8 Bits 3 channels 16 Bits DMA: Interrupts: 8259 comp. 8 + 7 levels PC compatible Timers: 8254 comp. 3 programmable counter/timers Memory: DRAM 2 x 72p SIMM: 4, 8, 16, 32, 64 MBytes 60ns
DIGITAL-LOGIC
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intel pentium p5 MSe586 hosiden DC motor 12V intel pentium microprocessor 80586 FRC 40 PIN Male connector 65545

MSM486SV8

Abstract: 80386 microprocessor interface keyboard / Protected 8086 ­ 80386 8 kByte write-back 16 Bits 24 lines 64 Mbytes 10, 33, 66, (99) MHz selectable , . 2 channels 8 Bits DMA: Interrupts: 8259 comp. 8 + 2 levels PC compatible Timers: 8254 , : 640 x 480 with 8/16/256 colors STN: 640 x 480 monochrome STN: 640 x 480 with 256 colors Plasma , . 8 Technical Support . 8 Limited Warranty
DIGITAL-LOGIC
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MSM486SV8 80386 microprocessor interface keyboard MSM486sv4 msm486sv Manual V1 MSM486SN SN 104 SCR image MSM486SN/SV MSM486SV/SN RS422/485

EL640.480.aa1

Abstract: EL640.480 ad4 . Display FIFO The Display FIFO is an 8 stage FIFO that is used to buffer the video data from display memory , Description MA[9:0] O Multiplexed row/column address bits for video display memory. Data bits for , FAX the Acknowledgment of Receipt form to (408) 922-0238 Software · · · · · Video BIOS OEM , one or two 256K x 16 self-refresh DRAM, respectively (CAS or WE controlled; symmetrical or asymmetrical addressing) · Hardware Bit Block Transfer engine · Hardware 64 x 64 pixel 2-bit cursor · Hardware
Seiko Epson
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X07G-Q-001-05 EL640.480.aa1 EL640.480 ad4 el640.480 c3 486dx schematic LCD 640X200 OPTREX LD4 SMD diode SPC8110F0A 74LS374 74LS74 74LS04 DMF-50418NF-FW

NEC C900 transistor

Abstract: TI486SLC2-50 Management: none clock switching 8237A comp. 4 channels 8 bits 3 channels 16 bits DMA , MByte - 16 Bit VGA, SVGA up to 768 x 1024 pixels 16/256 colors TFT: 640 x 480 with 8/16/256 colors , : Bank: 70ns 2 x 30 pins SIMM 18 Bit 2 MBytes, 8 Mbytes 1 4.3 Interface 4.3.1 (needs , . 7 2 class="hl">8 , . 8 2.2 Unique Features
DIGITAL-LOGIC
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MSE486V NEC C900 transistor TI486SLC2-50 TI486SXL 80486 microprocessor addressing modes 486SLC2-50 vga bios 65550

lg crt monitor circuit diagram

Abstract: hs 8109 for zero wait-state write operation. Display FIFO This is an 8 stage FIFO that is used to buffer the video data from display memory. VGA Palette This block implements the standard 256word x 18 , row/column address bits for video display memory. MDA[15:0] I/O w/ PD 2 MDB[15:0] I/O , 50% duty cycle. Data bits for video display memory. The output drivers of these pins are placed , respectively. Data bits for video display memory when 1024KB of memory is present. The output drivers of
Seiko Epson
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SPC8110 lg crt monitor circuit diagram hs 8109 486dx isa bios pin assignment DS-17 SANYO SP1137 hitachi plasma electronic diagram X07-GQ-001-01 X07-GG-002-01 LM334
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