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0x0010

Catalog Datasheet MFG & Type PDF Document Tags

PM7390-BI

Abstract: 1878H 0x000C 0x0010 0x0014 0x0018 (lowest priority) Table D.1 ADSP-2101/2115 Interrupts & Interrupt , Timer Interrupt Vector Address 0x0000 0x0004 (highest priority) 0x0010 0x0014 0x0018 (lowest , 0x0000 0x0004 (highest priority) 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 (lowest , 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (lowest priority) Table D , Timer Interrupt Vector Address 0x0000 (highest priority) 0x002C 0x0004 0x0008 0x000C 0x0010
PMC-Sierra
Original
PM7390 MACH48 PM7390-BI 1878H DS35112 STS-48C D28Ch PMC-2001532 PMC-1990823

ADSP-2105

Abstract: 0X0004 = *ip; I2C1DXR = 0x10; while(!(I2C1SR & 0x0010); I2C1DXR = (dacp & 0xFF00) >>8; while(!(I2C1SR & 0x0010); I2C1DXR = (dacp & 0xFF); while(!(I2C1SR & 0x0010); ip+; // re-point ip back to , the receive register (I2CDRR). I2C1DXR = 0x10; while(!(I2C1SR & 0x0010); I2C1DXR = (dacp & 0xFF00) >>8; while(!(I2C1SR & 0x0010); I2C1DXR = (dacp & 0xFF); while(!(I2C1SR & 0x0010 , 0x0010 4 Flash configuration enable RESERVED 13:5 DESCRIPTION Reserved RTI_CTRL
Analog Devices
Original
ADSP-2100 ADSP-2105 ADSP-2171 ADSP-2181 0X0004 0x0000 ADSP-2111 ADSP-21

ADC1110

Abstract: tms470 i2c 0x00060,1,0x0020,ram ;On-Chip RAM B2 ma 0x00100,1,0x0100,ram ;On-Chip RAM B0 if CNF=0 ma 0x00300,1,0x0100,ram ;On-Chip RAM B1 ma 0x07010,1,0x0010,ioport ;Peripheral ­ System Config & Control ma 0x07020,1,0x0010,ioport ;Peripheral ­ WDT / RTI ma 0x07030,1,0x0010,ioport ;Peripheral - ADC ma 0x07040,1,0x0010,ioport ;Peripheral - SPI ma 0x07050,1,0x0010,ioport ;Peripheral - SCI ma 0x07070,1,0x0010,ioport ;Peripheral ­ Ext Ints ma 0x07090,1,0x0010,ioport ;Peripheral ­ Digital I/O ma 0x07400,1,0x000D,ioport
Texas Instruments
Original
SPNA098A TMS470 ADC1110 tms470 i2c ADS1110 TMS470R1B1M kickstart

SPRU151

Abstract: C240 ROM bootloader resides in the ROM of the device beginning at ROM address 0x00100000. The ROM boot , 0x0010 0000 0010 Master 0x0010 0000 1 Reserved ­ ­ ­ ­ ­ 0011 0 or 1 , Bypass /1 CLKIN 0x0010 0000 0110 0 or 1 16-bit SPI Boot [McBSP0] Master Bypass /1 CLKIN 0x0010 0000 0111 0 or 1 NAND Flash Boot Master Bypass /1 CLKIN 0x0010 0000 1000 0 or 1 UART Boot without Hardware Flow Control [UART0] Master Bypass
Texas Instruments
Original
TMS320 TMS320C240 SPRU151 C240 F240 SPRA276

spraag0d

Abstract: 0x6C6E10CD 0x0010 for all valid ISB settings, and the address table should be programmed so that the corresponding address table entry for the ISB setting points to 0x0010. All entries in the table point to 0x0010, as shown in Figure 2. EPROM Address 0x0000 0x0010 0x0002 0x0010 0x0004 0x0010 0x0006 0x0010 0x0008 xxxx 0x000A 0x0010 0x000C 0x0010 0x000E 0x0010 Address Table , stored starting at address 0x0010. A total of 32 bytes are written to the EPROM before the stop
Texas Instruments
Original
spraag0d 0x6C6E10CD 0x5853590A SPRU580 TMS320C6000 hpi script TMS320DM643 DM643

AN2549

Abstract: MSC8101 entry for the ISB setting points to 0x0010. All entries in the table point to 0x0010, as shown in , starting at address 0x0010. A total of 32 bytes are written to the EPROM before the stop condition is sent , 0x0F000000 0x0C 111 0x0FF00000 0x0E In this example, the code should load from 0x0010 for all , Semiconductor, Inc. Serial EPROM Boot Procedure 0x0010 0x0002 0x0010 0x0004 0x0010 0x0006 0x0010 0x0008 xxxx 0x000A 0x0010 0x000C 0x0010 0x000E Freescale Semiconductor
Freescale Semiconductor
Original
AN2549 MSC8101 MSC8101ADS SCL 8018 90c07352

BTM110

Abstract: 71CA Clock Control #define ADC_CL_8MHz 0x0000 #define ADC_CL_4MHz 0x0010 #define ADC_CL_2MHz 0x0020 , 0x0040 #define STATUS_B2STAT_DAV 0x0020 #define STATUS_AXSTAT_DAV 0x0010 #define STATUS_T1STAT_DAV , ////////// // Internal Reference Mode #define REF_INT_EXTERNAL 0x0000 #define REF_INT_INTERNAL 0x0010 // Power-Up , _276 0x0010 #define CFG_PRE_340 0x0018 #define CFG_PRE_1044 0x0020 #define CFG_PRE_1108 0x0028 #define , _2 0x0010 #define AUDCTL1_DACFS_3 0x0018 #define AUDCTL1_DACFS_4 0x0020 #define AUDCTL1_DACFS_5 0x0028
Freescale Semiconductor
Original
BTM110 71CA 8030 watchdog BTM-110 0x0010 AN2549/D

PAX270

Abstract: PXA270 ­ ­ ­ ­ 0 HPI Boot Slave Bypass /1 CLKIN 0x0010 0000 0010 Master 0x0010 0000 1 Reserved ­ ­ ­ ­ ­ 0011 0 or 1 Reserved ­ ­ ­ ­ , 0x0010 0000 0110 0 or 1 16-bit SPI Boot [McBSP0] Master Bypass /1 CLKIN 0x0010 0000 0111 0 or 1 NAND Flash Boot Master Bypass /1 CLKIN 0x0010 0000 1000 , 0x0010 0000 1001 0 or 1 Reserved 1010 0 or 1 VLYNQ Boot 1011 0 or 1 1100 0
Texas Instruments
Original
TSC2100 PAX270 PXA270 sadi GPIO113 SLAA198 SLAA292 PXA27 TSC2100W

SPRU237

Abstract: SPRU580 timeCnt +1; bertec0 = read_reg (0x518); - Read value of BERTEC0 temp = (bertec0 & 0x0010) = 0x0010 , , 0x0010 & 0x003c);- Disable BERTC0.RINV Page 6 of 8 break; - Set to repetitive pattern
Texas Instruments
Original
SPRU237 nand toggle ddr 0x409 0x0000000b TMS320C642x 0X41504954 TMS320C642

AN3818

Abstract: APP3818 &= ~0x0002; } DACE0 = 1; } DACE0 = 0; } TMMK04 = 0; TS0 |= 0x0010; } TMMK04 = 1; TT0 |= 0x0010 , U19000JJ3V0AN00 29 3 3. 4. 5 TMMK04 0 TS0 TS0 |= 0x0010 #define START_125() { TMMK04 = 0; TS0 |= 0x0010; } 3. 4. 6 TMMK04 1 TT0 TT0 TMIF04 0 |= 0x0010 #define STOP_125() { TMMK04 = 1; TT0 |= 0x0010; TMIF04 = 0
Maxim Integrated Products
Original
DS31256 AN3818 APP3818

0x0002

Abstract: 0x04e1 ~0x300F EEPROM_Byte_change( 0x3000,0x3C00,0x3001 ,0xAA, 0x0010 ); //The customer code area from 0x3000 , EEPROM_Byte_change_Eram( 0x3000,0x3001 ,0x55, 0x0010 ) ; //The customer code area from 0x3000 to 0x31FF; // The Buffer
NEC
Original
0x0002 0x04e1 PWM125 0X00FD 78K0R-KH3 78K0R U19000JJ3V0AN003 M8E0909J 78K0RADPCM-SP 78K0R/KE3 U17854J

SM59D04G2

Abstract: 0x11FF TSM_INT_LEVEL3 0x01000000 #define TSM_INT_LEVEL4 0x00400000 #define TSM_INT_LEVEL5 0x00100000 #define , #define TSM_CISR_INT_CHANNEL4 0x0010 #define TSM_CISR_INT_CHANNEL5 0x0020 #define , start_position = 0x0010; /* Initial value for desired_ & current_position */ UINT16 table_siz_index = 0x1C00 , priority in the TPU */ /* -Initial desired position of 0x0010, */ /* -Initial current position of 0x0010, */ /* -Table Size of 0x18 (d24), Table Index of 0x00, */ /* -Slew
SyncMOS Technologies
Original
SM59D04G2 0x11FF IRFWX-A046

0x0809

Abstract: MPC500 following example that although a breakpoint is placed on address 0x0010, the break occurs the first time in the put_string routine because that address, 0x0010, was pre-fetched before branching to put_string , memory 02 00 5F 12 FF F3 12 F9 7D 7E 00 7F 4E 12 FF D5 >B0001003 Breakpoint 0, address = 0x0010 , BP0-Con BP1-Con 00 00 00 0B 0000 0058 0010 0012-83 0000-80 now PC at 0x0010 $B0002203 Breakpoint
Freescale Semiconductor
Original
0x0809 MPC500 MPC555 AN2364/D

MSC1210 ROM.a51

Abstract: 7F59 and ALTDTRx, is 0x0010. Writing a value less than 0x0010 will cause either or both the PWMxH and PWMxL outputs not to function. The minimum acceptable dead time value is 0x0010. As a result of this , cycle value is 0x0010. Duty cycle values less than 0x0010 should cause the PWM outputs to display , , do not load the duty cycle register with a value less than or equal to 0x0010. If the immediate duty , errata described in this document: 1. If a value less than 0x0010 is written to the DTRx and
Texas Instruments
Original
SBAA079 MSC1210 MSC1210 ROM.a51 7F59 sample code read and write flash memory 82H-83H 033H

dsPIC30F Family Reference Manual ds70046

Abstract: DSPIC30F2020 written to the dead time registers, DTRx and ALTDTRx, is 0x0010. Writing a value less than 0x0010 will , value is 0x0010. As a result of this errata, the minimum usable dead time is 16 ns. Dead time , is 0x0010. Duty cycle values less than 0x0010 should cause the PWM outputs to display states , value less than or equal to 0x0010. If immediate duty cycle updates are not enabled, no action is , following list summarizes the errata described in this document: 1. If a value less than 0x0010 is
Microchip Technology
Original
DS70178 DS70157 DS70046 dsPIC30F Family Reference Manual ds70046 DSPIC30F2020 Family Reference Manual ds70046 PWM control dsPIC 33f PWM control dsPIC 33f in C PIC30F1010/202X PIC30F/33F PIC30F

PWM control dsPIC 33f

Abstract: DS70178 0x0010. Writing a value less than 0x0010 will cause either or both the PWMxH and PWMxL outputs not to , that the minimum PWM duty cycle value is 0x0010. Duty cycle values less than 0x0010 should cause the , less than or equal to 0x0010. Affected Silicon Revisions A1 A2 A3 X X X Affected , PWM Dead Time 1. If a value less than 0x0010 is written to the DTRx and ALTDTRx registers , than or equal to 0x0010 causes the PWM outputs to flip to the inverted state. X X X PWM
Microchip Technology
Original
AN10 AN11 ASM30 DS70268 PWM generating code dsPIC30f in C PIC30F1010 PIC30F2020 PIC33F2023 DS80319D-

DS70178C

Abstract: AN10 0x0000 0x1000 0x0024 0x0000 0x0010 0x0010 0x0010 0x0010 0x0000 0x0010 0x0260 0x0022 0x0904 0x0000 0x0000 , 0x0010 (16) = 1x gain 2B Blue gain, default = 0x0010 (16) = 1x gain 2C Red gain, default = 0x0010 (16) = 1x gain 2D Green2 gain, default = 0x0010 (16) = 1x gain 2E Global gain, default = 0x0010 (16) = 1x , gain of 1 (register set to 0x0010) corresponds to the lowest setting where the pixel signal is
Microchip Technology
Original
DS70178C DS80445D-

MT9V043

Abstract: .00dd : */ e_SARDEC_ST.mfbahR1_UW = 0x0010; /* address: 0x00100000 */ e_SARDEC_ST.mfbalR1_UW = 0x00B0; /* size , */ e_SARDEC_ST.mfbalR4_UW = 0x0010; /* size: */ e_SARMMC_ST.smcR1_UW 1 kB */ */ /* user access on all , */ e_SARSYS_ST.GlbCtrl_UW |= 0x0010; /* - setup Flash Banks - */ FWPROGRAM->FMMAC2 = 0xFFF8; /* bank0 , ACCESS - */ e_SARSYS_ST.GlbCtrl_UW &= ~0x0010; 2.3 Additional Memory Map To control the memory , ) */ GEL_MapAdd(0x00000000, 0, 0x00100000, 1, 0); /* 1st Flash (1MB) */ GEL_MapAdd(0x00100000, 0
Micron Technology
Original
MT9V043 r gb 489 3915-05 MT9V043P11ST

TMS470 F05

Abstract: interrupt programming in TMS470 value that can be written to the dead-time registers, DTRx and ALTDTRx, is 0x0010. Writing a value , value is 0x0010. Duty cycle values less than 0x0010 should cause the PWM outputs to display states , load the duty cycle register with a value less than or equal to 0x0010. If immediate duty cycle , following list summarizes the errata described in this document: 1. If a value less than 0x0010 is , cycle value less than or equal to 0x0010 causes the PWM outputs to flip to the inverted state. 6
Texas Instruments
Original
TMS470 F05 interrupt programming in TMS470 tms470 Interrupt Bootloader, tms470 0X0072 0xfffffe10 SPNA066 TMS470R1 SE470R1VB8AD

DS70178

Abstract: PWM control dsPIC 33f in C errata described in this document: 1. If a value less than 0x0010 is written to the DTRx and , enabled, any duty cycle value less than or equal to 0x0010 causes the PWM outputs to flip to the , and ALTDTRx, is 0x0010. Writing a value less than 0x0010 will cause either or both the PWMxH and PWMxL outputs not to function. The minimum acceptable dead time value is 0x0010. As a result of this , have a value of 0x0010 or greater. If zero dead time is required, configure the DTC bits in the
Microchip Technology
Original
dspic spi code example dsPIC33F2023 DS80391A-page DS80391A-

SCI15

Abstract: 16-FACH following list summarizes the errata described in this document: 1. If a value less than 0x0010 is , , any duty cycle value less than or equal to 0x0010 causes the PWM outputs to flip to the inverted , written to the dead time registers, DTRx and ALTDTRx, is 0x0010. Writing a value less than 0x0010 will , value is 0x0010. As a result of this errata, the minimum usable dead time is 16 ns. Dead time , (DTC = 2) or DTRx and ALTDRx must have a value of 0x0010 or greater. If zero dead time is
iC-Haus
Original
16-FACH MQFP52 SCI15 DCH11 induktive PN11 18 701
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