256KB Application Note 750CXe and 750CXr Differences Abstract This application note - Datasheet Archive

 

Application Note 750CXe and 750CXr Differences Abstract This application note describes the programming model, performance,

 

® Application Note 750CXe and 750CXr Differences Abstract This application note describes the programming model, performance, package, and power differences between the PowerPC 750CXr and the PowerPC 750CXe processors. Overview The PowerPC 750CXr is a 32-bit implementation of the PowerPC Architecture TM in a 0.18 micron copper technology. The PowerPC 750CXr processor is derived from the 750CXe; it is a cost reduced version and is offered at lower operating frequencies. The 750CXr revision 4.0 processor is identical to the 750CXe revision 3.1 processor in program function, with the exception of PVR differences. In addition to the PVR differences, there are a few minor specification differences between the 750CXr and the 750CXe. The following sections describe these differences, but also point out attributes that remain the same. · Programming Model · Performance · Power, Voltage, Frequency · Timings · Package · Start-up Functions Programming Model Processor Version Register (PVR) The 750CXr processor version number (PVR) is 0x0008. The only difference between the 750CXr and 750CXe PVRs is in the design revision level designation. Table 1. Design Revision Levels and Processor Version Registers (PVR) Design Revision Level PVR 750CXe dd2.2 00082202 750CXe dd2.4 00083214 or 00082214 750CXe dd3.1 00083311 or 00082311 750CXr dd4.0 00083410 750CXe_Cxrdiffs.doc February 14, 2005 Page 1 of 6 ® Application Note 750CXe and 750CXr Differences Configuration The 750CXr has the same integrated 256KB 256KB L2 cache array as the 750Cxe, although some product offerings may have a "no L2" option, where L2 operation is not guaranteed. This means that users should not expect to have a fully functional L2 on chip, and must ensure that the L2 is disabled via software to prevent its operation. The 750CXr internal L2 cache uses ECC for error detection and correction, same as the 750CXe. There are no changes required for HID or L2CR register programming for 750CXr, although users of the "no L2" versions must disable L2 operation by setting L2CR [L2E], bit 0, to 0. Untested PLL Ratios The 750CXr characterization testing did not include verification of operation at Processor-to-60x bus ratios of 7.5x, 8x, 9x, and 10x, so these are not officially supported. 60x bus operation was verified only at 100Mhz and 133Mhz operation; however, we know of no reason why lower speed operation would not be possible. Errata The 750CXr contains the same errata items as the 750CXe dd3.1 revision. 750CXr Errata 1, 2, 3, and 4 previously existed in the 750CXe 2.4 and 3.1 revisions. 750CXr errata #5, 6, and 7 correspond to 750CXe dd3.x errata #6, 7, and 8, respectively. Refer to the specific errata listings for further details. Performance The 750CXr incorporates these design enhancements over the existing 750 processor: · Wider L1 data cache reload bus (256-bit); same as in the 750CXe. · Additional FPU reservation station; same as in the 750CXe. · Higher precision results from the reciprocal estimate instructions; same as 750CXe. The 750CXr and 750CXe L1 data cache supports hit-under-miss access, meaning that with one miss outstanding, the cache can continue to be accessed for accesses that hit. Once a second miss occurs, the corresponding instruction stalls, waiting for the first miss to be serviced. The data bus width for bus interface unit (BIU) accesses of the L1 data cache array is 256 bits on the 750CXr and 750CXe. As a result, cache line data bursts can be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. The floating-point execution unit in the 750 has a single reservation station, which causes it to stall whenever the three stages of the FPU execution pipeline are full. A second reservation station has been added to the 750CXr and 750CXe FPU, which eliminates this stall and results in higher throughput for optimized floating-point intensive applications. On the 750, the floating reciprocal estimate single (fres) instruction provides an estimate of the reciprocal of its input value to a precision of 8 bits and the floating reciprocal square root estimate (frsqrte) instruction provides an estimate of the square root of its input value to a precision of 5 bits. Both of these computations are improved on the 750CXr and 750CXe to yield results, which contain 12 bits of precision. 750CXe_Cxrdiffs.doc Page 2 of 6 February 14, 2005 ® Application Note 750CXe and 750CXr Differences This reduces, or eliminates the need for iterative refinement of these values in applications that use these functions. Power, Voltage, and Frequency The 750CXr and 750CXe are both manufactured in the same 0.18 micron 8SE technology; however, changes in manufacturing line tailoring and sort criteria can result in differences in power consumption and operating parameters. Customers should review the appropriate 750CXr data sheet for specifics such as power consumption, core voltage tolerances, and supported frequencies for operation. Table 2. Power and Operating Condition Differences Spec Differences 750CXr 750CXe Core Vdd 1.8 ­ 1.9V for