NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| P2010NSN2MHB | Freescale Semiconductor | P2010 STD 1200/800 PBFR | 
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| P2010NSN2HHC | Freescale Semiconductor | P2010 ST 800/800 R2.1 |
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| P2010NSE2KHB | Freescale Semiconductor | OBSOLETE - P2010 ENC 1000/800 PBFR |
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| P1010NSN5FHA | Freescale Semiconductor | P1010 IND STD NE 667/800 |
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| P1010NSN5HHA | Freescale Semiconductor | P1010 IND STD NE 800/800 |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Type Time Delay range Time Delay Tolerance Characteristic Impedance DS1L 0.12.0ns (0.10ns step , H 7.50max 0.11.2ns 0.05ns 1.32.6ns 0.05ns 2.8ns 0.10ns 12.00max 3.05.0ns 0.25ns ... | Original |
2 pages, |
1110NS DL1L5 datasheet abstract |
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| Abstract: 88ps 163ps 0.8ns Max. *(2) 0-5ns DC 3V ECL10KH ECL10KH 175ps 325ps 1.3ns Max. *(2) 0-10ns Max. 50±10% , Max. 0-10ns FACT 350ps 650ps 3.5ns Max. *(3) Voltage 0-20ns *(1) Changes at a ratio of 1.75% ... | Original |
2 pages, |
VDS5020 ECL10K ECL10KH variable analog delay VDS1110 VDS1120 VDS2110 VDS2120 VDS5010 0-30ns VDS3110 datasheet abstract |
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| Abstract: Number VDJ1010 VDJ1010 Delay Time Range±10% 0-1.0ns Increment Resolution 33ps 30 Steps Rise Time ... | Original |
2 pages, |
waveform variable time delay VDJ1010 variable analog delay VDJ1010 abstract |
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| Abstract: Transmit Interface RdClk B A CelAvl* A RdEn XXXX FFD[17:0] A = 0-10ns 4.2. H1 , Receive Interface Clk C A CLAV B B FFRD[0] XXXX FFD[17:0] A = 0-10ns 5. H1 , H2 H3 C = 0-10ns UTOPIA-to-SARA Interface Implementation Both transmit and receive , TxData[7:0] XXXX A = 0-10ns H1 H2 H3 B = 4 cycles delay H4 H5 P1 P2 P3 P44 P45 P46 P47 P48 XX H1 H2 H3 H4 H5 P1 P2 C = 0-10ns D = ... | Original |
16 pages, |
TXC-05601 TXC-05501 MACH110 TXC-05501-0002-AN TXC-05501-0002-AN abstract |
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| Abstract: Height (inches) 0.250" 0.250" 0.362" Time delay increments 0.10ns steps 0.25ns steps ... | Original |
2 pages, |
DS02M530 marking A00 DS02M530 abstract |
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| Abstract: 28ps 47ps 0.06ns 0.10ns 0.12ns 0.06ns 0.10ns 718K - 2 (KG/mm ) I/O ... | Original |
18 pages, |
TX49 P-FBGA 169 rsf-11 SoC hdd TC190 TC200 TC200E TC223 TC260 TC280 TC300C toshiba tx99 Celaro TOSHIBA TC203 LSI CMOS GATE ARRAY datasheet abstract |
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| Abstract: Time delay values: 0.1 to 0.8ns: 0.05ns steps 0.9 to 1.3ns: 0.10ns steps Above 1.3ns: in ... | Original |
3 pages, |
datasheet abstract |
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| Abstract: steps (3.5ns to 4.5ns) �05ns �05ns (1.1ns to 2.9ns) -0.05ns/+0.10ns (3.0ns) �10ns (3.5ns to ... | Original |
2 pages, |
GL2L5MS450D-T5-C GL2L5MS450D GL02M541 GL02M541 abstract |
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| Abstract: coef. of time delay 2.6ns 0.10ns steps Time delay increments DC Resistance 2.1 ~ 2.5ns ... | Original |
2 pages, |
DL1L5XK200S-C DL1L5ZK510S-C DL02M510 DL02M510 abstract |
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| Abstract: 34 Data Signal Input Setup Time (tDS) 0.15ns 15 0.1ns 10 0.10ns 10 0.050 ns ... | Original |
2 pages, |
HYNIX HYMP164S64AP6-Y5 HYMP164S64AP6-S5 HYMP164S64AP6-E3 HYMP164S64AP6-C4 DDR2 SODIMM SPD JEDEC HYMP164S64AP6-E3 abstract |
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| Abstract: HM6707 HM6707 Series 262144-word x 1 -bit High Speed Hi-BiCMOS Static RAM The HM6707 HM6707 Series has been converted to the HM6707A HM6707A Series. The new A Series is completely compatible with the non-A Series. Please refer to the specification comparison below to assist in your conversion. HM6707 HM6707 HM6707A HM6707A Unit 20 25 15 20 25 min. max. min. max. min. max. min. max. min. max. DC ILj 2 2 2 2 2 MA ILo 10 10 10 10 10 M Icc 100 100 100 100 100 mA Iccl 120 120 140 120 120 mA ... | OCR Scan |
1 pages, |
HM6707 HM6707A HM6707 abstract |
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| Abstract: ANALOG DIGITAL AUDIO MODEL NUMBER Vss Volts Idd Iee mA Gain Range mA dB VCA Gain Range dB Gain Gain Range dB Pre Amp Gain Range dB -3dB BW Input Spectral Noise Mhz Input Resis tance Slew Rate Accu racy 25C ohms V/usec % Control Input Input Resis tance Kohms CH Separtion 4000 VOLTAGE CONTROLLED AMPLIFIERS I3P dB 1 dB Comp @ 10Mhz Grade Temp Range 0 70C NA # pins -40 85 ... | Original |
1 pages, |
SSM2164 SSM2122 SSM2118T SSM2024 SSM2018T SSM2120 datasheet abstract |
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| Abstract: National Semiconductor NMC6551 NMC6551 1024-Bit (256 x 4) Static RAM CMOS RAMs General Description The NMC6551 NMC6551 is a static CMOS random access read/write memory organized as 256 words of 4 bits each. This device is fabricated with National Semiconductor's silicon-gate CMOS technology and is fully compatible with the TTL environment. Synchronous operation is provided by on-chip address input and data output latches. The ENABLE input serves as the device strobe controlling the latching functions. The I ... | OCR Scan |
6 pages, |
NMC6551N-5 NMC6551J-9 NMC6551J-5 NMC6551J-2 NMC6551 N22A J22A NMC6551 abstract |
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| Abstract: «M If) U) (O O National Semiconductor NMC6552 NMC6552 1024-Bit (256 x 4) Static RAM General Description The NMC6552 NMC6552 is a static CMOS random access read/write memory organized as 256 words of 4 bits each. This device is fabricated with National Semiconductor's silicon-gate CMOS technology and is fully compatible with the TTL environment. Synchronous operation is provided by the on-chip address input and data output registers. The ENABLE input serves as the device strobe controlling the latching func ... | OCR Scan |
6 pages, |
NMC6552J-9 NMC6552J-5 N18A mc6552 J18A a7e semiconductor NMC6552 NMC6552 abstract |
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| Abstract: HEF4737B HEF4737B HEF4737V HEF4737V LSI QUADRUPLE STATIC DECADE COUNTERS The HEF4737B HEF4737B and HEF4737V HEF4737V are static quadruple decade counters for frequencies from 0 to 10 MHz. The counters are supplied with an extra overload flip-flop giving a total count capability of 19 999. The counter has the following inputs and outputs: a count input (CP), an asynchronous reset input (MR), an asynchronous preset input (PL), a transfer input (T), an output enable input (EO) (which controls the BCD outputs), the digit select inputs ... | OCR Scan |
7 pages, |
HEF4737B HEF4737V HEF4737B abstract |
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| Abstract: HEF4737B HEF4737B HEF4737V HEF4737V LSI QUADRUPLE STATIC DECADE COUNTERS The HEF4737Band HEF4737V HEF4737V are static quadruple decade counters for frequencies from 0 to 10 MHz. The counters are supplied with an extra overload flip-flop giving a total count capability of 19999. The counter has the following inputs and outputs: a count input (CP), an asynchronous reset input (MR), an asynchronous preset input (PL), a transfer input (T), an output enable input (EO) (which controls the BCD outputs), the digit select inputs ( ... | OCR Scan |
7 pages, |
HEF4737VD HEF4737V HEF4737BP HEF4737BD HEF4737B HEF4737VP HEF4737B abstract |
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| Abstract: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B HE4000B Logic Package Outlines/Information HEF, HEC HEF4737B HEF4737B HEF4737V HEF4737V LSI Quadruple static decade counters Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4737B HEF4737B HEF4737V HEF4737V Quadruple static decade counters The complementary MOS struct ... | Original |
9 pages, |
HEF4737VP HEF4737VD HEF4737V HEF4737BP HEF4737BD HEF4737B HE4000B HE4000B abstract |
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| Abstract: HEr47ofö HEF4737V HEF4737V LSI QUADRUPLE STATIC DECADE COUNTERS The HEF4737B HEF4737B and HEF4737V HEF4737V are static quadruple decade counters for frequencies from 0 to 10 MHz. The counters are supplied with an extra overload flip-flop giving a total count capability of 19 999. The counter has the following inputs and outputs: a count input (CP), an asynchronous reset input (MR) an asynchronous preset input (PL), a transfer input (T), an output enable input (EO) (which controls the BCD outputs), the digit select inp ... | OCR Scan |
7 pages, |
HEF4737VP HEF4737VD HEF4737V HEF4737BP HEF4737BD HEF4737B HEF4737V abstract |
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| Abstract: MCC omponents 21201 Itasca Street Chatsworth !"# $ % !"# BAS21WX BAS21WX Features · · · Plastic case Preferred devices are recommended choices for future use and best overall value. Device Marking: JS High Voltage Switching Diode Maximum Ratings Symbol VR IF IFM(surge) Rating Continuous Reverse Voltage Peak Forward Current Peak Forward Surge Current Value 250 200 625 Thermal Characteristics Symbol PD RJA TJ, TSTG SOD-323 Unit Vdc mAdc ... | Original |
1 pages, |
MarKING JS datasheet fr 107 BAS21WX diode fr 107 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| ns17p008 ns18p003 ns18p004 ns18p005 ns18p006 ns18p007 ns18p010 ns18p011 ns19p002 ns19p003 ns19p004 ns19p006 ns19p007 ns19p010 ns19p011 ns19p012 ns19p013 ns19p015 ns20p002 ns20p003 ns20p004 ns20p006 ns20p007 ns20p008 ns20p009 ns20p010 ns20p011 ns21p002 ns21p003 ns21p004 ns21p005 ns21p006 ns21p007 ns21p008 ns21p009 ns21p010 ns21p011 ns13p001 ns13p002 ns13p003 ns13p004 ns13p005 ns13p006 ns13p007 ns13p008 ns13p009 ns13p010 www.datasheetarchive.com/files/texas-instruments/data/other.srt |
Texas Instruments | 12/05/1997 | 0.75 Kb | SRT | other.srt |
| tperiod_CLKIN : VitalDelayType := 0.010 ns; should be changed to: tperiod_CLKIN_POSEDGE : VitalDelayType := 0.010 ns; 2) simprim_VITAL.vhd line 1631 reads tperiod_CLKIN : VitalDelayType := 0.010 ns; should change to tperiod_CLKIN_POSEDGE : VitalDelayType := 0.010 ns; line 1798 reads Period => tperiod_CLKIN should change to Period www.datasheetarchive.com/files/xilinx/docs/rp0001b/rp01b3b.htm |
Xilinx | 29/02/2000 | 5.23 Kb | HTM | rp01b3b.htm |
| 47.010ns. - All delay: 47.010ns Analysis completed Mon Jan 26 17:32:27 1998 - www.datasheetarchive.com/download/56350136-985943ZC/wcd010c6.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd010c6.z |
| 47.010ns. - All delay: 47.010ns Analysis completed Mon Jan 26 17:32:27 1998 - www.datasheetarchive.com/download/52057314-987199ZC/wcd02ee0.z |
Xilinx | 13/07/1998 | 13034.22 Kb | Z | wcd02ee0.z |
| DelayType01 := (0.100 ns, 0.100 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.010 ns; MAXPERCLKIN : time := 100 ns; tpw_CLKIN_posedge : VitalDelayType := 0.010 ns; tpw_CLKIN_negedge : VitalDelayType := 0.010 ns; tpw_RST_posedge : VitalDelayType := 0.010 ns; DUTY_CYCLE_CORRECTION : Boolean := TRUE; CLKDV_DIVIDE : real www.datasheetarchive.com/download/31141550-995890ZC/xapp132.zip (dll_2x.vhd) |
Xilinx | 07/09/2000 | 8.63 Kb | ZIP | xapp132.zip |
| ); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.010 ns; MAXPERCLKIN : time := 100 ns; tpw_CLKIN_posedge : VitalDelayType := 0.010 ns; tpw_CLKIN_negedge : VitalDelayType := 0.010 ns; tpw_RST_posedge : VitalDelayType := 0.010 ns; DUTY www.datasheetarchive.com/download/31141550-995890ZC/xapp132.zip (dll_mirror_1.vhd) |
Xilinx | 07/09/2000 | 8.63 Kb | ZIP | xapp132.zip |
| DelayType01 := (0.100 ns, 0.100 ns); tperiod_CLKIN_POSEDGE : VitalDelayType := 0.010 ns; MAXPERCLKIN : time := 100 ns; tpw_CLKIN_posedge : VitalDelayType := 0.010 ns; tpw_CLKIN_negedge : VitalDelayType := 0.010 ns; tpw_RST_posedge : VitalDelayType := 0.010 ns; DUTY_CYCLE_CORRECTION : Boolean := TRUE; CLKDV_DIVIDE : real www.datasheetarchive.com/download/31141550-995890ZC/xapp132.zip (dll_mirror_2.vhd) |
Xilinx | 07/09/2000 | 8.63 Kb | ZIP | xapp132.zip |
| _CLKIN_POSEDGE : VitalDelayType := 0.010 ns; MAXPERCLKIN : time := 100 ns; tpw_CLKIN_posedge : VitalDelayType := 0.010 ns; tpw_CLKIN_negedge : VitalDelayType := 0.010 ns; tpw_RST_posedge : VitalDelayType := 0.010 ns; DUTY_CYCLE_CORRECTION : Boolean www.datasheetarchive.com/download/31141550-995890ZC/xapp132.zip (dll_standard.vhd) |
Xilinx | 07/09/2000 | 8.63 Kb | ZIP | xapp132.zip |
| - Total (0.010ns logic, 2.568ns route) 2.578ns (0.4% logic, 99.6%% route - Total (0.010ns logic, 1.786ns route) 1.796ns (0.6% logic, 99.4%% route) Note: clkp is the www.datasheetarchive.com/files/xilinx/docs/rp00016/rp0165c.htm |
Xilinx | 29/02/2000 | 5.96 Kb | HTM | rp0165c.htm |
| - Total (0.010ns logic, 2.568ns route) 2.578ns (0.4% logic, 99.6%% route - Total (0.010ns logic, 1.786ns route) 1.796ns (0.6% logic, 99.4%% route) Note: clkp is the www.datasheetarchive.com/files/xilinx/docs/wcd0000c/wcd00caa.htm |
Xilinx | 16/02/1999 | 5.18 Kb | HTM | wcd00caa.htm |