NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Interrupt request register 1 (address 003C16) b7 b0 IREQ1 0 No timer X interrupt request issued , ) (address 003C16),bit7 (address 003D16 003D16),bit0 (address 003E16 003E16),bit7 (address 003F16 003F16),bit0 (address 002516 , interrupt routine и Judgment whether timer X underflows IREQ1 (address 003C16),bit7 ? 1 , (address 002B16 002B16) IREQ1 (address 003C16),bit7 TXH (address 002B16 002B16) TXL (address 002A16 002A16) 255 0 0 ... | Original |
9 pages, |
T12M datasheet abstract |
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| Abstract: (Address: 003A16 003A16), bit 1 0 NOP IREQ1 (Address: 003C16), bit 1 0 0 IREQ1 (Address: 003C16), bit 3 , interrupt request issued 0 IREQ1 (Address: 003C16), bit 1? · Detect INT1 falling edge 1 IREQ1 (Address: 003C16), bit 1 0 · Write transmission data TBRB (Address: 001816) The first byte of ... | Original |
10 pages, |
001C 001B datasheet abstract |
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| Abstract: b0 0 INTEDGE INT1 falling edge active Interrupt request register 1 (address: 003C16) b7 , : 003E16 003E16), bit 1 0 INTEDGE (address: 003A16 003A16), bit 1 0 NOP IREQ1 (address: 003C16), bit 1 0 ICON1 ... | Original |
6 pages, |
datasheet abstract |
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| Abstract: (address 003C16) b7 b0 0 IREQ1 No INT1 interrupt request Interrupt control register 1 , ),bit1 INTEDGE (address 003A16 003A16),bit1 NOP IREQ1 (address 003C16),bit1 ICON1 (address 003E16 003E16),bit1 ... | Original |
7 pages, |
datasheet abstract |
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| Abstract: (Address: 003C16) b7 b0 0 IREQ1 No timer 2 interrupt request issued Interrupt control register , : 003C16), bit 6 (Address: 003E16 003E16), bit 2 X00000002 X00000002 256-1 256-1 0 0 0 1 · Timer 2 count ... | Original |
7 pages, |
datasheet abstract |
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| Abstract: (address 003C16) b7 b0 IREQ1 0 No timer X interrupt request issued Interrupt request register , ) (address 0FF416 0FF416) (address 0FF716 0FF716) (address 002A16 002A16) (address 002B16 002B16) (address 003C16),bit7 (address ... | Original |
8 pages, |
datasheet abstract |
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| Abstract: , 1) [Address 002C16 002C16, 003C16] DMiCON(i = 0, 1) 1 Transfer unit bit select bit 1 : 8 bits , b7 b0 1 DMAi control register (i = 0, 1) [Address 002C16 002C16, 003C16] DMiCON(i = 0, 1) DMA ... | Original |
7 pages, |
M16C/62A M16C/62A abstract |
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| Abstract: 002C16 002C16, 003C16] DMiCON(i = 0, 1) 1 0 Transfer unit bit select bit 0 : 16 bits Repeat transfer , 1 DMAi control register (i = 0, 1) [Address 002C16 002C16, 003C16] DMiCON(i = 0, 1) DMA enable bit 1 ... | Original |
6 pages, |
055AAH M16C/62A M16C/62A abstract |
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| Abstract: falling edge active · No INT1 interrupt request issued (address 003C16),bit1 0 0 IREQ1 (address 003C16),bit1? · Confirm SRDY1 signal (INT1 falling edge detecting) 1 IREQ1 (address 003C16 ... | Original |
12 pages, |
LDM-1000 example1 datasheet abstract |
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| Abstract: ) 003B16 003B16 CPU mode register (CPUM) CPU mode register (CPUM) 003C16 Interrupt request register 1 , 4 003A16 003A16 (Interrupt edge selection register) 003C16 (Interrupt request register 1) 003D16 003D16 ... | Original |
12 pages, |
tz1m datasheet abstract |
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| Abstract: Interrupt request register 1 (address: 003C16) b7 IREQ1 b0 0 0 No timer X interrupt request ... | Original |
7 pages, |
datasheet abstract |
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| Abstract: APPLICATION NOTE 3823 Group Timer X Operation (Real Time Port Control: Stepping Motor Control) 1. Abstract The following article introduces and shows an example of Timer X Operation (Real Time Port Control: Stepping Motor Control) on the 3823 group device. 2. Introduction The explanation of this issue is applied to the following conditions: Applicable MCU: 3823 Group Oscillation frequency: 8 MHz This sample program may include operations of unused bit functions for the convenience ... | Original |
7 pages, |
datasheet abstract |
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| Abstract: : (address: (address: (address: XXX0XXXX2 1011XXX02 1011XXX02 002016) 002116) 003C16), bit 4 003D16 003D16 ... | Original |
7 pages, |
datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| ,015,007,008,016,024,032,031 0039 15 003A 07 003B 08 003C 16 003D 24 003E 32 003F 31 20 0040 www.datasheetarchive.com/files/national/software/misc/keyboard/asm_keyb/k_outs/codeset1.lis |
National | 05/01/1999 | 4.15 Kb | LIS | codeset1.lis |
| ; File e:\sources\lowlvl\sarlib\config.c ; /* ; ;= ; ; Config.c ; ; Copyright 1995 ; ; Integrated Device Technology, Inc ; ; All rights reserved public, and private. ; ; ; ; PCI Configuration information ; ; PCI config space read/write routines ; ; for the SAR. ; ; ; ; Author: Michael Sprong ; ; Comments: myk@idtinc.com myk@qmail.idtinc.com ; ; ; ; Revision 1.5d3 ; ; ; ; Last Change: added consprintf ; ; Date: 3/29/95 ; ; www.datasheetarchive.com/download/38862127-131549ZC/sarlib.zip (CONFIG.COD) |
IDT | 03/03/1996 | 1333.05 Kb | ZIP | sarlib.zip |
| ; File e:\sources\lowlvl\sarlib\config.c ; /* ; ;= ; ; Config.c ; ; Copyright 1995 ; ; Integrated Device Technology, Inc ; ; All rights reserved public, and private. ; ; ; ; PCI Configuration information ; ; PCI config space read/write routines ; ; for the SAR. ; ; ; ; Author: Michael Sprong ; ; Comments: myk@idtinc.com myk@qmail.idtinc.com ; ; ; ; Revision 1.5d3 ; ; ; ; Last Change: added consprintf ; ; Date: 3/29/95 ; ; www.datasheetarchive.com/files/idt/atm software/idt driver modules/sarlib.unz/config.cod |
IDT | 29/02/1996 | 312.14 Kb | COD | config.cod |
| ; File e:\sources\lowlvl\sarlib\config.c ; /* ; ;= ; ; Config.c ; ; Copyright 1995 ; ; Integrated Device Technology, Inc ; ; All rights reserved public, and private. ; ; ; ; PCI Configuration information ; ; PCI config space read/write routines ; ; for the SAR. ; ; ; ; Author: Michael Sprong ; ; Comments: myk@idtinc.com myk@qmail.idtinc.com ; ; ; ; Revision 1.5d3 ; ; ; ; Last Change: added consprintf ; ; Date: 3/29/95 ; ; www.datasheetarchive.com/download/54231381-715785ZC/sarlib.zip (CONFIG.COD) |
Scantec | 03/03/1996 | 1333.05 Kb | ZIP | sarlib.zip |
| ; File e:\sources\lowlvl\sarlib\config.c ; /* ; ;= ; ; Config.c ; ; Copyright 1995 ; ; Integrated Device Technology, Inc ; ; All rights reserved public, and private. ; ; ; ; PCI Configuration information ; ; PCI config space read/write routines ; ; for the SAR. ; ; ; ; Author: Michael Sprong ; ; Comments: myk@idtinc.com myk@qmail.idtinc.com ; ; ; ; Revision 1.5d3 ; ; ; ; Last Change: added consprintf ; ; Date: 3/29/95 ; ; www.datasheetarchive.com/files/scantec/idt/atm_soft/idt_driv/sarlib_u/config.cod |
Scantec | 29/02/1996 | 312.14 Kb | COD | config.cod |
| /* * * Name: xmac_ii.h * Project: GEnesis, PCI Gigabit Ethernet Adapter * Version: $Revision: 1.46 $ * Date: $Date: 2003/01/28 09:47:45 $ * Purpose: Defines and Macros for Gigabit Ethernet Controller * */ /* * * (C)Copyright 1998-2003 SysKonnect GmbH. * * www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (xmac_ii.h) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| " [REGISTER] SIRAM16 SIRAM16 SIRAM16 SIRAM16, 0x003C, 16, 11, "SI RAM Entry 16", B2 [FIELDS] LOOP, 15, 1, 0, "Loop www.datasheetarchive.com/files/motorola/mot-cd's/cdronetcom-d/mcuinit3/siram2.sub |
Motorola | 13/08/1998 | 132.13 Kb | SUB | siram2.sub |