500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
EL7156CS Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil
EL7156CS-T13 Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil
EL7155CS-T13 Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil
EL7155CS Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil
EL7156CS-T7 Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil
EL7155CS-T7 Intersil Corporation 3.5A HALF BRIDGE BASED PRPHL DRVR, PDSO8, SO-8 visit Intersil

"PCIe Bridge"

Catalog Datasheet MFG & Type PDF Document Tags

pex8311 fpga interface

Abstract: 250MB Feature-Rich PCI Express Bridge The bridge offers PCI ExpressTM (PCIe) bridging capability from a Generic Local , local bus devices including processors and FPGAs to a downstream PCIe port. The bridge can also function , translation. The bridge is equipped with a standard PCIe port that operates as a single x1 link with a maximum , other as well with downstream PCIe devices. In this case, the bridge's configuration and system hierarchy comes through the Local Bus. In EndPoint mode, the bridge is configured through the PCIe port
PLX Technology
Original

HDMI to vga converter ic

Abstract: VGA to HDMI converter ic SATA South Bridge SATA Switch DVI/HDMI PCIe Clock Buffer PCIe Bridge PCI slot 1GigE HDD PCIe PCIe TMDS Switch PCIe Bridge PCIe Packet Switch PCIe Packet , . Xlator PON DDR 2 or 3 XO HDD HDD PCIe to PCI-X Bridge Legacy PCI-X slot , and 2.0 PCIe* Clock Buffer FBDIMM I/O Bridge Level Shifter PCIe FBDIMM Embedded , ReDriver PCIe* to PCI-X Bridge 10GbE /iSCSI PCI-X PCI-X 10GbE LVPECL X0 PCIe 2.0
Pericom Semiconductor
Original

PEB20N1

Abstract: BGA 23X23 layers and is compliant with PCIe Base specification Revision 1.0a. The bridge core stack offers a highly , up to 133 MHz. PCIe to PCI-X Bridge Supports both forward (PCI Express to PCI/PCIX, see Figure 2) as , , and support all bridging functions as described in the PCIe Bridge Specification. PCI I/O or Slots Processor North Bridge x4 PCIe Memory Memory Memory Memory PEB20N1 PCI-X I/O or Slots Figure , PCI-X Mode 1 to PCI-Express Bridge 89PEB20N1 Product Brief Preliminary Information* Device
Integrated Device Technology
Original
BGA 23X23

nFORCE 430

Abstract: nvidia nforce 430 , SAS/SATA, XAUI, Fibre Channel Fully featured PCIe Bridge and Packet Switch families 2. Industry , HUB PCIe PCIe Bridge Bridge PCI Legacy Bus HDD PCIe PCIe Clock Clock Buffer Buffer , Asynchronous Asynchronous NOW Introducing Next Generation: PCI Express PCIe Bridge PCIe Bridge Family , Semiconductor 2006 Pericom PCIe Bridge Solutions www.pericom.com/pcie PCI Express to PCI Reversible Bridge PI7C9X110A: Reversible ­ Configurable via PCIe or PCI PCI port - 32-bit / 66MHz 3.3V signaling
Pericom Semiconductor
Original
nFORCE 430 nvidia nforce 430 nforce 410 mcp NVIDIA nForce pcie x16 mcp 430 nvidia

SPARTAN-6 GTP

Abstract: msi g31 Bridge for PCI Express (v1.03.a) Functional Description The AXI Bridge for PCIe Intellectual Property , Express system. The AXI Bridge for PCIe translates the AXI4 memory read or writes to PCIe Transaction , AXI4-Stream Enhanced Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a , PCIe generated read or write TLPs. The Register Block contains registers used in the AXI Bridge for PCI , AXI4 read requests with pending completions. The Master Bridge processes both PCIe MemWr and MemRd
Xilinx
Original
DS820 SPARTAN-6 GTP msi g31 axi wrapper state machine diagram for axi bridge XC6SLX4 state machine axi 3 protocol TM-7000

AMBA AXI4

Abstract: AMBA AXI4 verilog code LogiCORE IP AXI EP Bridge for PCI Express (v1.01.a) Functional Description The AXI PCIe Intellectual , Express system. The AXI PCIe bridge translates the AXI4 memory read or writes to PCIe Transaction Layer , Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a register block and two , Master Bridge connects to the AXI4 Interconnect as a master to process the PCIe generated read or write , addresses for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the write
Xilinx
Original
AMBA AXI4 AMBA AXI4 verilog code Xilinx DS820 pci to pci bridge verilog code AMBA AXI specifications 0X138

realtek 8112

Abstract: LPC & SPI lash Audio Codec ALC888 Audio 7.1 Channel PCIe to PCI bridge GPIO / SDIO , bridge with PCIe x1 input from PEX8505 switch Super I/O Winbond WF83627DHG on LPC bus Audio Codec PCIE2 (x1) Realtek ALC886 High Deinition Audio Codec I2C to GPIO bridge PCA9535 PCIe (x1 , Six PCI Express® x1 (5 slots, 1 PCIe Mini Card slot) PCIe-to-PCI bridge, two PCI slots SDVO ADD2 , Express® Type 1/10 Reference Carrier Board with onboard PCIe to PCI bridge SD socket for bootable
Adlink Technology
Original
realtek 8112 RJ-45 PEX8112 W83627DHG 10/100/1000BASE-T
Abstract: GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 PERp I PCIe Receive , . hot reset initiated by PCIe host. SSTL, 1.8V, output GN4121 x1 Lane PCI Express to Local Bridge , PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 local bus, PCIe to local (inbound , GN4121 x1 Lane PCI Express to Local Bridge Data Sheet GN4121 x1 Lane PCI Express to Local Bridge Data Sheet 51539 - 0 June 2009 www.gennum.com 1 of 30 Proprietary & Confidential GENNUM
Original

PEX8311

Abstract: 21mmx21mm interfacing multiple local bus devices including processors and FPGAs to a downstream PCIe port. The bridge , independent data transfers with the bridge initiating both the PCIe and local bus. With dual channels, data , 8311 provides a complete local bus to PCIe translation. The bridge is equipped with a standard PCIe , PCIe devices. In this case, the bridge's configuration and system hierarchy comes through the Local Bus. In EndPoint mode, the bridge is configured through the PCIe port. The PEX 8311 also supports
PLX Technology
Original
PEX8311 21mmx21mm 8311 PCIE bridge NT/98/2000/M 8311-AA66BC 8311RDK PEX8311-SIL-PB-P1-1

PEX8311-AA66BCF

Abstract: pex8311 fpga interface Feature-Rich PCI Express Bridge The bridge offers PCI ExpressTM (PCIe) bridging capability from a Generic Local , utilizing PCI today can easily migrate to PCIe. The ExpressLaneTM PEX 8311 bridge can be used in Root , FPGAs to a downstream PCIe port. The bridge can also function in an EndPoint type application connecting , . These channels provide independent data transfers with the bridge initiating both the PCIe and local bus , Signaling The PEX 8311 provides a complete local bus to PCIe translation. The bridge is equipped with a
PLX Technology
Original
PEX8311-AA66BCF pex8311 fpga interface pex8311aa66bcf interface of camera fpga PEX8311-AA66BC pex8311-aa66 862-PEX8311-AA66BC-F

abstract for UART simulation using VHDL

Abstract: VIRTEX-5 DDR2 controller the PLBv46 Endpoint Bridge for PCI Express®. The simulation consists of a PCIe® Downstream Port Model communicating over a PCIe link to an EDK system containing the PLBv46 Endpoint Bridge for PCI , invoke the PLBv46 _PCIe generics editor. The generics are used to configure the PLBv46 Endpoint Bridge , viewer contains dividers for the PCIe Bridge, Downstream Port Model, BRAM, DDR2, and Central DMA signals , PLBv46 Endpoint Bridge documentation. Several examples are given in "Abnormal PCIe to PLBv46
Xilinx
Original
XAPP1110 ML505 ML555 abstract for UART simulation using VHDL VIRTEX-5 DDR2 controller pcie microblaze BFM 4a XILINX PCIE XPS Central DMA UG197 UG341 XAPP1030 XAPP1111

GN4124

Abstract: GN412x PCIe Transmit +Bus Lane A. CML GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 - 1 May , GN4124 x4 Lane PCI Express to Local Bridge Data Sheet GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 - 1 May 2009 www.gennum.com 1 of 31 Proprietary & Confidential Revision , Bridge User Manual (Document ID: 47719) to this data sheet. This User Manual is no longer a stand-alone , .8 GN4124 x4 Lane PCI Express to Local Bridge Data Sheet 48407 - 1 May 2009 2 of 31 Proprietary
GENNUM
Original
GN412x GN4124-CBE3 C4 to BGA E15 52624 PCIe phy
Abstract: PCI Express to PCI-X Mode 1 Bridge ◠Supports forward (PCIe to PCI/PCI-X) bridging ◠Allows , /PCI-X bus. The PEB20T1 bridge is based on a flexible and efficient layered architecture. The PCIe layer , devices on each PCI/PCI-X bus running at frequencies up to 133 MHz. PCIe to PCI-X Bridge Supports , Bridge Specification, Revision 1.0. The device will treat the PCIe port as connected to the primary bus , described in the PCIe Bridge Specification. Processor Memory Memory Memory Memory North Bridge Integrated Device Technology
Original
89PEB20T1

PEX8532

Abstract: pci root bridge : Medical Imaging Systems PLX Product: PEX 8311 ­ Local Bus to PCIe Bridge Key Benefit: Full Connectivity to PCIe Components New Medical Imaging Systems Migrating to PCI Express Designs Medical , ) Four GPIO, 1 GPI, 1 GPO to a PCIe port. In this conversion, the bridge completely translates data I2O , through the bridge. The bridge converts traffic to PCIe and passes it through an aggregation switch , -1- Issue No. 38 PEX 8311 Key Features Generic Local Bus to PCI Express Bridge Root
PLX Technology
Original
8311-SIL-EA-1 PEX8532 pci root bridge EX8311 264MB/ 250MB/

PXP-100a

Abstract: vhdl code for traffic light control Endpoint Bridge. PCIe transactions are generated and analyzed by Catalyst and LeCroy test equipment. For , generate PCIe traffic. A Catalyst script which configures the PLBv46 Endpoint Bridge and performs memory , Bridge is a PCIe endpoint instantiated in a Xilinx FPGA which communicates with a root complex. The , System: PLBv46 Endpoint Bridge for PCI Express in a ML505 Embedded Development Platform Author: Lester Sanders This reference system demonstrates the functionality of the PLBv46 Endpoint Bridge for PCI
Xilinx
Original
PXP-100a vhdl code for traffic light control catalyst tester X1030 vhdl code for TRAFFIC LIGHT CONTROLLER SINGLE WAY pcie connector XC5VLX50T PPC405 PPC440 XAPP1022

XILINX PCIE

Abstract: abstract for UART simulation using VHDL Endpoint Bridge for PCI Express® core. The simulation consists of a PCIe® Downstream Port Model communicating over a PCIe bus to an EDK system containing the PLBv46 Endpoint Bridge for PCI Express. The , Bridge is a PCIe endpoint instantiated in a Xilinx FPGA. An endpoint normally communicates with a root , PLBv46 _PCIe generics editor. The generics are used to configure the PLBv46 Endpoint Bridge. The Xilinx , viewer contains dividers for the PCIe Bridge, BRAM, DDR2, and Central DMA signals. In the waveform
Xilinx
Original
0xC000004 H60000000 XC5VLX50TFF1136 XPS IIC GT11 verilog code for pci express XAPP1000

PCIe Bridge

Abstract: with PCIe Base specification Revision 1.0a. The bridge core stack offers a highly efficient and , Express to PCI/PCI-X Bridge Specification, Revision 1.0. The device will treat the PCIe port as connected , supported as described in the PCIe Bridge Specification. Processor North Bridge x4 PCIe Memory , PCI Express® to PCI-X Mode 1 Bridge 89PEB20T1 Product Brief Device Overview The PEB20T1 PCI Express® to PCI-X mode 1 Bridge is a member of IDT's PRECISETM family of PCI Express bridging and
Integrated Device Technology
Original

TSI384

Abstract: TSI384-133ILV Titl Tsi384TM PCIe-to-PCI/X Bridge User Manual Formal February 2008 80E1000 , . . . . . . . . . . . . . . . . . 1.2.2 PCIe Features . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCIe , . . . . . . . . . 4.7.1 PCIe to PCI/X Non-prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 PCIe to PCI/X Prefetchable Address Remapping . .
Tundra Semiconductor
Original
TSI384 TSI384-133ILV 384TM MA001

651 y

Abstract: Titl Tsi999TM PCIe-to-PCI/X Bridge User Manual Formal March 2008 80E1999 , . . . . . . . . . . . . . . . . . 1.2.2 PCIe Features . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCIe , . . . . . . . . . 4.7.1 PCIe to PCI/X Non-prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 PCIe to PCI/X Prefetchable Address Remapping . .
Tundra Semiconductor
Original
651 y 999TM

RS780M

Abstract: RS780MC .1-1 Chapter 2: Register Space Access 2.1 PCIE Core/Port Indirect Register Space (PCIEIND) .2-1 2.2 PCIE Port Indirect Register Space (PCIEIND_P , .3-1 3.2 PCIE Ports , .5-5 5.7.3 Northbridge PCIE Early Initialization , .5-15 5.7.6 Northbridge PCIE Late Post Initialization
Advanced Micro Devices
Original
RS780 RS780C RS780D RS780M RS780E RS780MC RX781 M780G
Showing first 20 results.