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Part Manufacturer Description Datasheet BUY
SN54S114W Texas Instruments S SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, FP-14 visit Texas Instruments
SN74F112N-10 Texas Instruments F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 visit Texas Instruments
CD4027BEE4 Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-PDIP -55 to 125 visit Texas Instruments
CD4027BNSR Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-SO -55 to 125 visit Texas Instruments
CD4027BF3A Texas Instruments CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125 visit Texas Instruments
SNJ54AS109FK Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops 20-LCCC -55 to 125 visit Texas Instruments

"J-K Flip flop"

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 32 x 34 MCC702 MCC802 MCC902 R-S Flip Flop 6ML 25 x 30 MCC703 MCC803 MCC903 3-lnput NOR Gate 2MH 25 , Flip Flop 1JD 48 x 57 MCC714 MCC814 MCC914 Dual 2-lnput NOR Gate 9KM 30 x 37 MCC715 MCC815 MCC915 Dual 3-lnput NOR Gate IMF 35 x 33 Not Avail. MCC816 MCC916 J-K Flip Flop 78M 43 x 43 MCC717 MCC817 , MCC819* MCC919 Dual 4-lnput NOR Gate 1MF 35 x 33 MCC720 MCC820" MCC920 J-K Flip Flop 810 60 x 60 MCC721 MCC821 * MCC921 Dual 2-lnput Gate Expander 7JC 38 x 31 MCC722 MCC822* MCC922 J-K Flip Flop 87A 54 x 58 -
OCR Scan
MCC775 MCC977 MCC783 MCC890 half adder JK flip flop MCC900 MCc700 MCC806 for half adder MIL-STD-883 MCC726 MCC826 MCC926 MCC727 MCC827
Abstract: D-type latch 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 -
OCR Scan
counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu counter 74169 MSM70V000 MSM-71V000 MSM72V000 MSM73V000 MSM74V000 MSM79V000
Abstract: 3 (2) 93 L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F1 13 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with set 7 (3) 102 DF 1 D-type flip flop with set/reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type -
OCR Scan
74183 adder 74169 binary counter 74381 alu 74151 8 by 1 Multiplexer flip flop 74379 74175 flip flops MSM75V000 MSM-76V000 MSM77V000 MSM78V000
Abstract: L205 D-type latch with reset 4 (2) D-type flip flops 94 DFF D-type flip flop 6 (3) 95 DFR D-type flip flop with reset 8 (3) 96 F112 D-type flip flop with reset 7 (3) 97 F113 D-type flip flop with set 7 (3) 98 DF D-type flip flop with set/reset 9 (3) 99 F114 D-type flip flop with set/reset 8 (3) 100 F115 D-type flip flop with reset 7 (3) 101 F116 D-type flip flop with sit 7 (3) 102 DF1 D-type flip flop with set /reset 8 (3) 103 F121 D-type flip flop 6 (4) 104 F125 D-type flip flop with -
OCR Scan
74139 for bcd to excess 3 code design a bcd counter using jk flip flop ttl 74118 priority encoder 74148 alu 74381 jk flip flop to d flip flop conversion MSM70H000 MSM-71H000 MSM72H000 MSM73H000 MSM74H000 MSM79H000
Abstract: B93 60x60 MCC851 MCC951 Monostable Multivibrator 29H 55x55 MCC852 MCC952 Dual J-K Flip Flop (common Clock and CD) 45 N 60x62 MCC853 MCC953 Dual J-K Flip Flop (Separate Clock and SD) 45N 60x62 MCC855 MCC955 Dual J-K Flip Flop (2K Pullup Resistor) 45N 60x62 MCC856 MCC956 Dual J-K Flip Flop (2K Pullup , VCC= Pin 14 GND = Pin 7 MCC852/MCC952 Dual J-K Flip Flop (common clock and Cp) MCC855/MCC955 Dual J-K Flip Flop (2k pullup resistor) MCC853/MCC953 Dual J-K Flip Flop (separate clock and Sq) MCC856 -
OCR Scan
MCC931 MCC930 MCC832 MCC831 MCC830 MCC1741C MCC1806 MCC1906 MCC1807 MCC1907 MCC1808 MCC1908
Abstract: are inhibited. A jo in t (JK) input is provided fo r all flip -flop s in this fam ily. The com mon , provided on all flip -flop s except the 9020, which because of a logic trade-off has only clear inputs. The , . This operation is represented sym bolically by AND gates in the logic symbol for each flip -flop . , CHARACTERISTICS (Ta = 25°C, Vcc = 5.0 V, C l = Ci = 15 pF of all flip -flop s unless otherwise noted) SYMBOL Clock , aterial 5-4 9XXX Series FUNCTIONAL DESCRIPTION - The T T L 9000 series has fo u r flip -flo p s -
OCR Scan
JK flip flop IC RS flip flop IC 9022 ic 9022 JK flipflop 9001 toggle type flip flop ic 9000DC 9020DC 9022DC 9000FC 9001FC 9020FC
Abstract: PO74G112A www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET , NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Maximum Ratings , www.potatosemi.com DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise , DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz , J-K FLIP FLOP WITH CLEAR AND PRESET 74 Series Noise Cancellation GHz Logic Packaging Mechanical Potato Semiconductor
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T flip flop pin configuration JK flip flop IC diagram 750MH 5000-VH A114-A 200-VM A115-A PO74G112ASU
Abstract: input/output D FLIP FLOP WITH RESET 1 1 O 1 DFFB - Oscillator buffers (interfacing with external , (reset) - Latch with S (set) - Latch with R - Latch with § - D Flip Flop - D Flip Flop with R (reset) - D Flip Flop with S (set) - D Flip Flop with R - D Flip Flop with S - D Flip Flop with R and S - D Flip Flop with R and S - D Flip Flop with 1 clock - JK Flip Flop - JK Flip Flop with R (reset) - JK Flip Flop with S (set) - JK Flip Flop with R - JK Flip Flop with S - JK Flip Flop with S -
OCR Scan
RS FLIP FLOP LAYOUT RS flip flop cmos 7400 2-input nand gate Matra-Harris Semiconductor Matra-Harris MATRA MHS HMT* 28 pins 0250-MA 0800-MA 0400-MA D-12OOAOO
Abstract: D-Flip Flop, Dual, with Set and Reset, TTL Inputs, Rad-Hard, Advanced Logic, CMOS CD4013BMS D-Type Flip Flop, Dual, Rad-Hard, CMOS, Logic CD4027BMS J-K Flop Flop, Master-Slave, Dual, Rad-Hard, CMOS, Logic HCS109MS Flip Flop, JK, Dual, Rad-Hard, High-Speed, CMOS, Logic HCS74MS Flip Flop, D-Type, with Set and Reset, Dual, Rad-Hard, High-Speed, CMOS, Logic HCTS74MS Flip Flop , Device Information ACS74MS Printer Friendly Version D-Flip Flop, Dual, with Set and Reset Intersil
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ACS74DMSR 5962F9679901VCC ACS74HMSR ACS74KMSR 5962F9679901VXC ACTS74MS flip flop of D-flip flop JK flipflop Flip flop JK cmos J-STD-020
Abstract: slave flip flop Dual J-K flip-flop with clear Dual J-K pos. edge trig. flip flop with preset.+clear Dual J-K Neg edge triggered flip flop with preset and clear Dual J-K Neg edge triggered flip flop , Quad 2-input NOR gate with N-input JK-master-slave flip flop with 2J and K inputs and N-input on slave section JK-master-slave flip flop with N-input on master slave section JK-master-slave flip flop with N-input on master slave section Dual JK-master-slave flip flop with set and reset inputs Electro Value
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FZH115B fzh261 FZK105 FZH131 FZJ111 FZH115 74INTEGRATED 16-DIL
Abstract: cell library is given on Fig. 7. D FLIP FLOP WITH RESET DFFR a -o B- f* Q Data sheet of Bbrary , Flop D Flip Flop with R (reset) D Flip Flop with S> (set) D Flip Flop with R D Flip Flop with S D Flip Flop with R and S D Flip Flop with R and S D Flip Flop with 1 clock JK Flip Flop JK Flip Flop with R (reset) JK Flip Flop with S (set) â  JK Flip Flop with R - JK Flip Flop with S - JK Flip Flop with S and R - JK Flip Flop with S and R - RS Flip Flop with NAND - RS Flip Flop with NOR 3 2 5 3 7 9 4 -
OCR Scan
transistor 6bn T flip flop IC 74LS series logic gates 3 input or gate 1 bit full adder 1 bit full adder with carry 1-Bit full adder MA1D-1200A00 6S20U
Abstract: Latch with S - D Flip Flop - D Flip Flop with R (reset) \ - D Flip Flop with S (set) - D Flip Flop with R _ - D Flip Flop with S - D Flip Flop with R and S - D Flip Flop with R and S - D Flip Flop with 1 clock JK Flip JK Flip JK Flip JK Flip JK Flip JK Flip JK Flip Flop Flop with Flop with Flop with Flop , MACROCELL Sequential Logic Functions (cont'd) - Toggle Flip Flop with asynchronous parallel load Interface , state internal bus driver - RS Flip Flop with NAND - RS Flip Flop with NOR EQU1VALEMT MACROCELL -
OCR Scan
1d1200a MIL883B
Abstract: Latch with 5 - D Flip Flop - D Flip Flop with R {reset) - D Flip Flop with S(set) - D Flip Flop with R - D Flip Flop with S - D Flip Flop with R and S - D Flip Flop with R and S - D Flip Flop with 1 clock - JK Flip Flop - JK Flip Flop with R (reset) · JK Flip Flop with S (set) - JK Flip Flop with R - JK Flip Flop with S - JK Flip Flop with S and R - JK Flip Flop with S and R - RS Flip Flop with NAND - RS Flip Flop with NOR 1-3 MA 0250/0400/0800/1200 MACROCELL S e q u e n tia l L o g ic F u n c -
OCR Scan
internal structure of ic 4017 4017 equivalent hc 7400 sentry 0250-M 0400-M 0800-M
Abstract: B93 60x60 MCC851 MCC951 Monostable Multivibrator 29H 55x55 MCC852 MCC952 Dual J-K Flip Flop (common Clock and CD) 45 N 60x62 MCC853 MCC953 Dual J-K Flip Flop (Separate Clock and SD) 45N 60x62 MCC855 MCC955 Dual J-K Flip Flop (2K Pullup Resistor) 45N 60x62 MCC856 MCC956 Dual J-K Flip Flop (2K Pullup , Vcc = Pin 14 GND = Pin 7 MCC848/MCC948 Clocked Flip Flop 44x46 (47P) PIN CONNECTIONS F,L, Si P -
OCR Scan
MC945 MCC950 MCC847 MC1741CP1 MC1741C mdtl logic chips MCC863 MCC963 MCC1800 MCC1900 MCC1801 MCC1901
Abstract: B93 60x60 MCC851 MCC951 Monostable Multivibrator 29H 55x55 MCC852 MCC952 Dual J-K Flip Flop (common Clock and CD) 45 N 60x62 MCC853 MCC953 Dual J-K Flip Flop (Separate Clock and SD) 45N 60x62 MCC855 MCC955 Dual J-K Flip Flop (2K Pullup Resistor) 45N 60x62 MCC856 MCC956 Dual J-K Flip Flop (2K Pullup , '¢ [3] * Applies to MC861/MC961 VCC = Pin 14 GND = Pin 7 MCC831 /MCC931 Clocked Flip Flop 55 x 55 -
OCR Scan
MCC1802 MCC1902 MCC1803 MCC1903 MCC1804 MCC1904
Abstract: B93 60x60 MCC851 MCC951 Monostable Multivibrator 29H 55x55 MCC852 MCC952 Dual J-K Flip Flop (common Clock and CD) 45 N 60x62 MCC853 MCC953 Dual J-K Flip Flop (Separate Clock and SD) 45N 60x62 MCC855 MCC955 Dual J-K Flip Flop (2K Pullup Resistor) 45N 60x62 MCC856 MCC956 Dual J-K Flip Flop (2K Pullup , /930 Series (continued) MCC845/MCC945 Clocked Flip Flop 44x46 (47P) PIN CONNECTIONS F,L, & P -
OCR Scan
k 98m MCC1805 MCC1905 MCC1809 MCC1909 MCC1810 MCC1910
Abstract: -input AND-OR-INVERT gate Vcc DM54H62/DM74H62 3-2-2-3-input expander GNo Vc DM54H73/DM74H73 dual J-K flip flop , 1 2 1» 6 17 ana DM54H74/DM74H74 dual D edge-triggered flip flop DM54H76/DM74H76 dual J-K master-slave flip flop DM54H78/DM74H78 dual J-K flip flop with preset and clear inputs ac test circuits , . NOTE 0: CL iodudes proba and jig capacitance. Flip Flop Propagation Delay Times » * OV, t, = to * 3 , ,PRR = tMHi. NOTEC: CL includes jig capacitence. Flip Flop Preset/Clear Propagation Delay Times -
OCR Scan
54h04 DM74H00 54h electrical characteristics 54H00 74H00 54H/74H DM54H/DM74H DM54H00/DM74H00 DM54H01 DM54H04/DM74H04
Abstract: Primitive Cells (Cont.) Name Flip Flop FD1x FD1SX FD2x FD2Sx FD3x FD3SX FD4x FD4Sx FJK1X FJKISx FJK2X , D-Flip flop D-flip flop with scan D-flip flop with clear D-flip flop with clear/scan D-flip flop with preset/clear D-flip flop with preset/clear and scan D-flip flop with preset D-flip flop with preset/scan J-K flip flop J-K flip flop with scan J-K flip flop with clear J-K flip flop with clear/scan J-K flip flop with preset/clear J-K flip flop with preset/clear and scan Toggle flip flop with clear Toggle flip -
OCR Scan
TC110G siemens master drive circuit diagram SR flip flop IC toshiba tc110g SC11C1 scxc1 M33S004
Abstract: Dual 4-input Expanders _ â'¢ FLIP FLOPS Function HD74 Series IID74S Series J-K Master-Flip Flop (AND Input») 72 â'" Dual J-K Flip Klops 73 - â'" Dual D-tvpe Edge-triggercd Klip Flop« 74 ^ 74 Dual J-K Flip Flops (with FR and CI.RJ 76 Dual J-K Flip Flop* 107 /S Dual J-K Negiitivc-cd*e-triggered Flip Flops (with PR and CI.R) _ 112 - Dual J-K Ncgative-rdge-trigger«! Flip Flops (wich PR) â'" 113 DmI J-K Nefahte-edgr-tr^ered Flip Flops (with PR. Common CLR. and CnDM CK) 1U - Monostable -
OCR Scan
DP-14 Flip Flops 74 series logic gates 2 input nand gate 24v 74 series 7 segment decoders H183 HD74/HD74S HD74S HD74/74S DP-16 DP-20
Abstract: â'¢ Independent input and output terminals for each flip flop â'¢ Direct-coupled set and reset â , T Notes 1. Measurement made for each flip flop. 2. Cl includes probe and tool floating , 5X Ri. put y I ^ C : Li ^ame load circuit as above Outputs 1. Measurement made for each flip flop. 2. CL includes probe and tool floating capacitance. 3. Diodes are all MA161 or equivalent -
OCR Scan
DN74LS76 DN74LS SO-16D
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